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rockchip: rk3328: migrate u-boot node to -u-boot.dtsi

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Move all the nodes only shown in u-boot to -u-boot.dtsi to make
rk3328.dtsi clean.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2019-08-15 11:40:56 +08:00
parent 8e5c8571fe
commit 2e91e2025c
5 changed files with 66 additions and 85 deletions
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31
arch/arm/dts/rk3328-evb-u-boot.dtsi
View File

@ -1,33 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+ // SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd * (C) Copyright 2016-2019 Rockchip Electronics Co., Ltd
*/ */
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-ddr3-666.dtsi" #include "rk3328-sdram-ddr3-666.dtsi"
/ { &usb_host0_xhci {
aliases { vbus-supply = <&vcc5v0_host_xhci>;
mmc0 = &emmc; status = "okay";
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
};
&cru {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
}; };

5
arch/arm/dts/rk3328-evb.dts
View File

@ -116,11 +116,6 @@
status = "okay"; status = "okay";
}; };
&usb_host0_xhci {
vbus-supply = <&vcc5v0_host_xhci>;
status = "okay";
};
&i2c1 { &i2c1 {
clock-frequency = <400000>; clock-frequency = <400000>;
i2c-scl-rising-time-ns = <168>; i2c-scl-rising-time-ns = <168>;

33
arch/arm/dts/rk3328-rock64-u-boot.dtsi
View File

@ -1,38 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/* /*
* (C) Copyright 2018 Rockchip Electronics Co., Ltd * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
*
* SPDX-License-Identifier: GPL-2.0+
*/ */
#include "rk3328-u-boot.dtsi"
#include "rk3328-sdram-lpddr3-1600.dtsi" #include "rk3328-sdram-lpddr3-1600.dtsi"
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
};
&cru {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&emmc {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};
&usb_host0_xhci { &usb_host0_xhci {
status = "okay"; status = "okay";
}; };

58
arch/arm/dts/rk3328-u-boot.dtsi Normal file
View File

@ -0,0 +1,58 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
/ {
aliases {
mmc0 = &emmc;
mmc1 = &sdmmc;
};
chosen {
u-boot,spl-boot-order = &emmc, &sdmmc;
};
dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-dmc";
reg = <0x0 0xff400000 0x0 0x1000
0x0 0xff780000 0x0 0x3000
0x0 0xff100000 0x0 0x1000
0x0 0xff440000 0x0 0x1000
0x0 0xff720000 0x0 0x1000
0x0 0xff798000 0x0 0x1000>;
};
usb_host0_xhci: usb@ff600000 {
compatible = "rockchip,rk3328-xhci";
reg = <0x0 0xff600000 0x0 0x100000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
snps,dis-enblslpm-quirk;
snps,phyif-utmi-bits = <16>;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-u2-susphy-quirk;
status = "disabled";
};
};
&cru {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
clock-frequency = <24000000>;
};
&emmc {
u-boot,dm-pre-reloc;
};
&sdmmc {
u-boot,dm-pre-reloc;
};

24
arch/arm/dts/rk3328.dtsi
View File

@ -186,7 +186,6 @@
}; };
grf: syscon@ff100000 { grf: syscon@ff100000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>; reg = <0x0 0xff100000 0x0 0x1000>;
@ -232,7 +231,6 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk"; clock-names = "baudclk", "apb_pclk";
clock-frequency = <24000000>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
dmas = <&dmac 6>, <&dmac 7>; dmas = <&dmac 6>, <&dmac 7>;
@ -351,17 +349,6 @@
status = "disabled"; status = "disabled";
}; };
dmc: dmc {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-dmc";
reg = <0x0 0xff400000 0x0 0x1000
0x0 0xff780000 0x0 0x3000
0x0 0xff100000 0x0 0x1000
0x0 0xff440000 0x0 0x1000
0x0 0xff720000 0x0 0x1000
0x0 0xff798000 0x0 0x1000>;
};
cru: clock-controller@ff440000 { cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>; reg = <0x0 0xff440000 0x0 0x1000>;
@ -512,17 +499,6 @@
status = "disabled"; status = "disabled";
}; };
usb_host0_xhci: usb@ff600000 {
compatible = "rockchip,rk3328-xhci";
reg = <0x0 0xff600000 0x0 0x100000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
snps,dis-enblslpm-quirk;
snps,phyif-utmi-bits = <16>;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-u2-susphy-quirk;
status = "disabled";
};
gic: interrupt-controller@ffb70000 { gic: interrupt-controller@ffb70000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
#interrupt-cells = <3>; #interrupt-cells = <3>;