pwm: Add driver for Amlogic Meson PWM controller
This adds the driver for the PWM controller found in the Amlogic SoCs. This PWM is only a set of Gates, Dividers and Counters: PWM output is achieved by calculating a clock that permits calculating two periods (low and high). The counter then has to be set to switch after N cycles for the first half period. The hardware has no "polarity" setting. This driver reverses the period cycles (the low length is inverted with the high length) for PWM_POLARITY_INVERSED. Disabling the PWM stops the output immediately (without waiting for the current period to complete first). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
parent
38c1c6f816
commit
2d481b2e3e
@ -23,6 +23,13 @@ config PWM_IMX
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help
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This PWM is found i.MX27 and later i.MX SoCs.
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config PWM_MESON
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bool "Enable support for Amlogic Meson SoCs PWM"
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depends on DM_PWM
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help
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This PWM is found on Amlogic Meson SoCs. It supports a
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programmable period and duty cycle for 2 independant channels.
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config PWM_MTK
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bool "Enable support for MediaTek PWM"
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depends on DM_PWM
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@ -12,6 +12,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o
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obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
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obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
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obj-$(CONFIG_PWM_MESON) += pwm-meson.o
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obj-$(CONFIG_PWM_MTK) += pwm-mtk.o
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obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
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obj-$(CONFIG_PWM_SANDBOX) += sandbox_pwm.o
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528
drivers/pwm/pwm-meson.c
Normal file
528
drivers/pwm/pwm-meson.c
Normal file
@ -0,0 +1,528 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Copyright (C) 2020 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2014 Amlogic, Inc.
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*
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* This PWM is only a set of Gates, Dividers and Counters:
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* PWM output is achieved by calculating a clock that permits calculating
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* two periods (low and high). The counter then has to be set to switch after
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* N cycles for the first half period.
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* The hardware has no "polarity" setting. This driver reverses the period
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* cycles (the low length is inverted with the high length) for
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* PWM_POLARITY_INVERSED.
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* Setting the polarity will disable and re-enable the PWM output.
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* Disabling the PWM stops the output immediately (without waiting for the
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* current period to complete first).
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*/
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#include <common.h>
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#include <clk.h>
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#include <div64.h>
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#include <dm.h>
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#include <pwm.h>
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#include <regmap.h>
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#include <linux/io.h>
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#include <linux/math64.h>
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#define NSEC_PER_SEC 1000000000L
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#define REG_PWM_A 0x0
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#define REG_PWM_B 0x4
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#define PWM_LOW_MASK GENMASK(15, 0)
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#define PWM_HIGH_MASK GENMASK(31, 16)
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#define REG_MISC_AB 0x8
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#define MISC_B_CLK_EN BIT(23)
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#define MISC_A_CLK_EN BIT(15)
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#define MISC_CLK_DIV_MASK 0x7f
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#define MISC_B_CLK_DIV_SHIFT 16
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#define MISC_A_CLK_DIV_SHIFT 8
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#define MISC_B_CLK_SEL_SHIFT 6
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#define MISC_A_CLK_SEL_SHIFT 4
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#define MISC_CLK_SEL_MASK 0x3
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#define MISC_B_EN BIT(1)
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#define MISC_A_EN BIT(0)
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#define MESON_NUM_PWMS 2
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static struct meson_pwm_channel_data {
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u8 reg_offset;
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u8 clk_sel_shift;
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u8 clk_div_shift;
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u32 clk_en_mask;
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u32 pwm_en_mask;
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} meson_pwm_per_channel_data[MESON_NUM_PWMS] = {
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{
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.reg_offset = REG_PWM_A,
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.clk_sel_shift = MISC_A_CLK_SEL_SHIFT,
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.clk_div_shift = MISC_A_CLK_DIV_SHIFT,
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.clk_en_mask = MISC_A_CLK_EN,
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.pwm_en_mask = MISC_A_EN,
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},
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{
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.reg_offset = REG_PWM_B,
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.clk_sel_shift = MISC_B_CLK_SEL_SHIFT,
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.clk_div_shift = MISC_B_CLK_DIV_SHIFT,
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.clk_en_mask = MISC_B_CLK_EN,
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.pwm_en_mask = MISC_B_EN,
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}
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};
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struct meson_pwm_channel {
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unsigned int hi;
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unsigned int lo;
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u8 pre_div;
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uint period_ns;
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uint duty_ns;
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bool configured;
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bool enabled;
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bool polarity;
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struct clk clk;
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};
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struct meson_pwm_data {
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const long *parent_ids;
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unsigned int num_parents;
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};
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struct meson_pwm {
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const struct meson_pwm_data *data;
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struct meson_pwm_channel channels[MESON_NUM_PWMS];
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void __iomem *base;
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};
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static int meson_pwm_set_enable(struct udevice *dev, uint channel, bool enable);
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static int meson_pwm_set_config(struct udevice *dev, uint channeln,
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uint period_ns, uint duty_ns)
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{
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struct meson_pwm *priv = dev_get_priv(dev);
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struct meson_pwm_channel *channel;
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struct meson_pwm_channel_data *channel_data;
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unsigned int duty, period, pre_div, cnt, duty_cnt;
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unsigned long fin_freq;
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if (channeln >= MESON_NUM_PWMS)
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return -ENODEV;
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channel = &priv->channels[channeln];
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channel_data = &meson_pwm_per_channel_data[channeln];
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period = period_ns;
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if (channel->polarity)
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duty = period_ns - duty_ns;
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else
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duty = duty_ns;
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debug("%s%d: polarity %s duty %d period %d\n", __func__, channeln,
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channel->polarity ? "true" : "false", duty, period);
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fin_freq = clk_get_rate(&channel->clk);
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if (fin_freq == 0) {
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printf("%s%d: invalid source clock frequency\n", __func__, channeln);
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return -EINVAL;
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}
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debug("%s%d: fin_freq: %lu Hz\n", __func__, channeln, fin_freq);
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pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL);
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if (pre_div > MISC_CLK_DIV_MASK) {
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printf("%s%d: unable to get period pre_div\n", __func__, channeln);
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return -EINVAL;
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}
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cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1));
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if (cnt > 0xffff) {
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printf("%s%d: unable to get period cnt\n", __func__, channeln);
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return -EINVAL;
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}
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debug("%s%d: period=%u pre_div=%u cnt=%u\n", __func__, channeln, period, pre_div, cnt);
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if (duty == period) {
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channel->pre_div = pre_div;
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channel->hi = cnt;
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channel->lo = 0;
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} else if (duty == 0) {
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channel->pre_div = pre_div;
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channel->hi = 0;
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channel->lo = cnt;
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} else {
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/* Then check is we can have the duty with the same pre_div */
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duty_cnt = div64_u64(fin_freq * (u64)duty, NSEC_PER_SEC * (pre_div + 1));
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if (duty_cnt > 0xffff) {
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printf("%s%d: unable to get duty cycle\n", __func__, channeln);
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return -EINVAL;
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}
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debug("%s%d: duty=%u pre_div=%u duty_cnt=%u\n",
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__func__, channeln, duty, pre_div, duty_cnt);
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channel->pre_div = pre_div;
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channel->hi = duty_cnt;
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channel->lo = cnt - duty_cnt;
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}
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channel->period_ns = period_ns;
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channel->duty_ns = duty_ns;
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channel->configured = true;
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if (channel->enabled) {
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meson_pwm_set_enable(dev, channeln, false);
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meson_pwm_set_enable(dev, channeln, true);
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}
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return 0;
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}
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static int meson_pwm_set_enable(struct udevice *dev, uint channeln, bool enable)
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{
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struct meson_pwm *priv = dev_get_priv(dev);
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struct meson_pwm_channel *channel;
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struct meson_pwm_channel_data *channel_data;
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u32 value;
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if (channeln >= MESON_NUM_PWMS)
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return -ENODEV;
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channel = &priv->channels[channeln];
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channel_data = &meson_pwm_per_channel_data[channeln];
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if (!channel->configured)
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return -EINVAL;
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if (enable) {
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if (channel->enabled)
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return 0;
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value = readl(priv->base + REG_MISC_AB);
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value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift);
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value |= channel->pre_div << channel_data->clk_div_shift;
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value |= channel_data->clk_en_mask;
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writel(value, priv->base + REG_MISC_AB);
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value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) |
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FIELD_PREP(PWM_LOW_MASK, channel->lo);
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writel(value, priv->base + channel_data->reg_offset);
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value = readl(priv->base + REG_MISC_AB);
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value |= channel_data->pwm_en_mask;
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writel(value, priv->base + REG_MISC_AB);
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debug("%s%d: enabled\n", __func__, channeln);
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channel->enabled = true;
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} else {
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if (!channel->enabled)
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return 0;
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value = readl(priv->base + REG_MISC_AB);
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value &= channel_data->pwm_en_mask;
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writel(value, priv->base + REG_MISC_AB);
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debug("%s%d: disabled\n", __func__, channeln);
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channel->enabled = false;
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}
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return 0;
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}
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static int meson_pwm_set_invert(struct udevice *dev, uint channeln, bool polarity)
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{
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struct meson_pwm *priv = dev_get_priv(dev);
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struct meson_pwm_channel *channel;
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if (channeln >= MESON_NUM_PWMS)
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return -ENODEV;
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debug("%s%d: set invert %s\n", __func__, channeln, polarity ? "true" : "false");
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channel = &priv->channels[channeln];
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channel->polarity = polarity;
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if (!channel->configured)
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return 0;
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return meson_pwm_set_config(dev, channeln, channel->period_ns, channel->duty_ns);
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}
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static int meson_pwm_ofdata_to_platdata(struct udevice *dev)
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{
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struct meson_pwm *priv = dev_get_priv(dev);
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priv->base = dev_read_addr_ptr(dev);
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return 0;
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}
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static int meson_pwm_probe(struct udevice *dev)
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{
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struct meson_pwm *priv = dev_get_priv(dev);
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struct meson_pwm_data *data;
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unsigned int i, p;
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char name[255];
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int err;
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u32 reg;
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data = (struct meson_pwm_data *)dev_get_driver_data(dev);
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if (!data)
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return -EINVAL;
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for (i = 0; i < MESON_NUM_PWMS; i++) {
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struct meson_pwm_channel *channel = &priv->channels[i];
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struct meson_pwm_channel_data *channel_data = &meson_pwm_per_channel_data[i];
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snprintf(name, sizeof(name), "clkin%u", i);
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err = clk_get_by_name(dev, name, &channel->clk);
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/* If clock is not specified, use the already set clock */
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if (err == -ENODATA) {
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struct udevice *cdev;
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struct uclass *uc;
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/* Get parent from mux */
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p = (readl(priv->base + REG_MISC_AB) >> channel_data->clk_sel_shift) &
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MISC_CLK_SEL_MASK;
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if (p >= data->num_parents) {
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printf("%s%d: hw parent is invalid\n", __func__, i);
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return -EINVAL;
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}
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if (data->parent_ids[p] == -1) {
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/* Search for xtal clk */
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const char *str;
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err = uclass_get(UCLASS_CLK, &uc);
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if (err)
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return err;
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uclass_foreach_dev(cdev, uc) {
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if (strcmp(cdev->driver->name, "fixed_rate_clock"))
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continue;
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str = ofnode_read_string(cdev->node, "clock-output-names");
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if (!str)
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continue;
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if (!strcmp(str, "xtal")) {
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err = uclass_get_device_by_ofnode(UCLASS_CLK,
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cdev->node,
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&cdev);
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if (err) {
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printf("%s%d: Failed to get xtal clk\n", __func__, i);
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return err;
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}
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break;
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}
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}
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if (!cdev) {
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printf("%s%d: Failed to find xtal clk device\n", __func__, i);
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return -EINVAL;
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}
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channel->clk.dev = cdev;
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channel->clk.id = 0;
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channel->clk.data = 0;
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} else {
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/* Look for parent clock */
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err = uclass_get(UCLASS_CLK, &uc);
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if (err)
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return err;
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uclass_foreach_dev(cdev, uc) {
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if (strstr(cdev->driver->name, "meson_clk"))
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break;
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}
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if (!cdev) {
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printf("%s%d: Failed to find clk device\n", __func__, i);
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return -EINVAL;
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}
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err = uclass_get_device_by_ofnode(UCLASS_CLK, cdev->node, &cdev);
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if (err) {
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printf("%s%d: Failed to get clk controller\n", __func__, i);
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return err;
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}
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channel->clk.dev = cdev;
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channel->clk.id = data->parent_ids[p];
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channel->clk.data = 0;
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}
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/* We have our source clock, do not alter HW clock mux */
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continue;
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} else
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return err;
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/* Get id in list */
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for (p = 0 ; p < data->num_parents ; ++p) {
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if (!strcmp(channel->clk.dev->driver->name, "fixed_rate_clock")) {
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if (data->parent_ids[p] == -1)
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break;
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} else {
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if (data->parent_ids[p] == channel->clk.id)
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break;
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}
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}
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/* Invalid clock ID */
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if (p == data->num_parents) {
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printf("%s%d: source clock is invalid\n", __func__, i);
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return -EINVAL;
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}
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/* switch parent in mux */
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reg = readl(priv->base + REG_MISC_AB);
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debug("%s%d: switching parent %d to %d\n", __func__, i,
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(reg >> channel_data->clk_sel_shift) & MISC_CLK_SEL_MASK, p);
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reg &= MISC_CLK_SEL_MASK << channel_data->clk_sel_shift;
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reg |= (p & MISC_CLK_SEL_MASK) << channel_data->clk_sel_shift;
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writel(reg, priv->base + REG_MISC_AB);
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}
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return 0;
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}
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static const struct pwm_ops meson_pwm_ops = {
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.set_config = meson_pwm_set_config,
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.set_enable = meson_pwm_set_enable,
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.set_invert = meson_pwm_set_invert,
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};
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#define XTAL -1
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/* Local clock ids aliases to avoid define conflicts */
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#define GXBB_CLKID_HDMI_PLL 2
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#define GXBB_CLKID_FCLK_DIV3 5
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#define GXBB_CLKID_FCLK_DIV4 6
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#define GXBB_CLKID_CLK81 12
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static const long pwm_gxbb_parent_ids[] = {
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XTAL, GXBB_CLKID_HDMI_PLL, GXBB_CLKID_FCLK_DIV4, GXBB_CLKID_FCLK_DIV3
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};
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static const struct meson_pwm_data pwm_gxbb_data = {
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.parent_ids = pwm_gxbb_parent_ids,
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.num_parents = ARRAY_SIZE(pwm_gxbb_parent_ids),
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};
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/*
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* Only the 2 first inputs of the GXBB AO PWMs are valid
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* The last 2 are grounded
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*/
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static const long pwm_gxbb_ao_parent_ids[] = {
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XTAL, GXBB_CLKID_CLK81
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};
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static const struct meson_pwm_data pwm_gxbb_ao_data = {
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.parent_ids = pwm_gxbb_ao_parent_ids,
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.num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_ids),
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};
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/* Local clock ids aliases to avoid define conflicts */
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#define AXG_CLKID_FCLK_DIV3 3
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#define AXG_CLKID_FCLK_DIV4 4
|
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#define AXG_CLKID_FCLK_DIV5 5
|
||||
#define AXG_CLKID_CLK81 10
|
||||
|
||||
static const long pwm_axg_ee_parent_ids[] = {
|
||||
XTAL, AXG_CLKID_FCLK_DIV5, AXG_CLKID_FCLK_DIV4, AXG_CLKID_FCLK_DIV3
|
||||
};
|
||||
|
||||
static const struct meson_pwm_data pwm_axg_ee_data = {
|
||||
.parent_ids = pwm_axg_ee_parent_ids,
|
||||
.num_parents = ARRAY_SIZE(pwm_axg_ee_parent_ids),
|
||||
};
|
||||
|
||||
static const long pwm_axg_ao_parent_ids[] = {
|
||||
AXG_CLKID_CLK81, XTAL, AXG_CLKID_FCLK_DIV4, AXG_CLKID_FCLK_DIV5
|
||||
};
|
||||
|
||||
static const struct meson_pwm_data pwm_axg_ao_data = {
|
||||
.parent_ids = pwm_axg_ao_parent_ids,
|
||||
.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_ids),
|
||||
};
|
||||
|
||||
/* Local clock ids aliases to avoid define conflicts */
|
||||
#define G12A_CLKID_FCLK_DIV3 3
|
||||
#define G12A_CLKID_FCLK_DIV4 4
|
||||
#define G12A_CLKID_FCLK_DIV5 5
|
||||
#define G12A_CLKID_CLK81 10
|
||||
#define G12A_CLKID_HDMI_PLL 128
|
||||
|
||||
static const long pwm_g12a_ao_ab_parent_ids[] = {
|
||||
XTAL, G12A_CLKID_CLK81, G12A_CLKID_FCLK_DIV4, G12A_CLKID_FCLK_DIV5
|
||||
};
|
||||
|
||||
static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
|
||||
.parent_ids = pwm_g12a_ao_ab_parent_ids,
|
||||
.num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_ids),
|
||||
};
|
||||
|
||||
static const long pwm_g12a_ao_cd_parent_ids[] = {
|
||||
XTAL, G12A_CLKID_CLK81,
|
||||
};
|
||||
|
||||
static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
|
||||
.parent_ids = pwm_g12a_ao_cd_parent_ids,
|
||||
.num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_ids),
|
||||
};
|
||||
|
||||
static const long pwm_g12a_ee_parent_ids[] = {
|
||||
XTAL, G12A_CLKID_HDMI_PLL, G12A_CLKID_FCLK_DIV4, G12A_CLKID_FCLK_DIV3
|
||||
};
|
||||
|
||||
static const struct meson_pwm_data pwm_g12a_ee_data = {
|
||||
.parent_ids = pwm_g12a_ee_parent_ids,
|
||||
.num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_ids),
|
||||
};
|
||||
|
||||
static const struct udevice_id meson_pwm_ids[] = {
|
||||
{
|
||||
.compatible = "amlogic,meson-gxbb-pwm",
|
||||
.data = (ulong)&pwm_gxbb_data
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-gxbb-ao-pwm",
|
||||
.data = (ulong)&pwm_gxbb_ao_data
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-axg-ee-pwm",
|
||||
.data = (ulong)&pwm_axg_ee_data
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-axg-ao-pwm",
|
||||
.data = (ulong)&pwm_axg_ao_data
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-g12a-ee-pwm",
|
||||
.data = (ulong)&pwm_g12a_ee_data
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-g12a-ao-pwm-ab",
|
||||
.data = (ulong)&pwm_g12a_ao_ab_data
|
||||
},
|
||||
{
|
||||
.compatible = "amlogic,meson-g12a-ao-pwm-cd",
|
||||
.data = (ulong)&pwm_g12a_ao_cd_data
|
||||
},
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(meson_pwm) = {
|
||||
.name = "meson_pwm",
|
||||
.id = UCLASS_PWM,
|
||||
.of_match = meson_pwm_ids,
|
||||
.ops = &meson_pwm_ops,
|
||||
.ofdata_to_platdata = meson_pwm_ofdata_to_platdata,
|
||||
.probe = meson_pwm_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct meson_pwm),
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user