mmc: Tegra: Add SD bus power/voltage function and MMC pad init call.
Tegra30 requires the SD Bus Voltage & Power bits be set in the SD Power Control register. Tegra20 works w/o them set, but do it anyway for those SoCs as it's part of the SD spec. Also call a common board pad init routine (pad_init_mmc) in mmc_reset(), used by Tegra30 only for now. Note that Tegra20 SD/MMC HW differs enough from Tegra20 that a new compatible entry is used in the fdt compat_names/id tables. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
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@ -21,7 +21,6 @@
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#include <bouncebuf.h>
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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@ -38,6 +37,38 @@ struct mmc_host mmc_host[MAX_HOSTS];
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#error "Please enable device tree support to use this driver"
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#endif
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static void mmc_set_power(struct mmc_host *host, unsigned short power)
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{
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u8 pwr = 0;
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debug("%s: power = %x\n", __func__, power);
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if (power != (unsigned short)-1) {
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switch (1 << power) {
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case MMC_VDD_165_195:
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pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
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break;
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case MMC_VDD_29_30:
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case MMC_VDD_30_31:
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pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
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break;
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case MMC_VDD_32_33:
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case MMC_VDD_33_34:
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pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
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break;
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}
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}
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debug("%s: pwr = %X\n", __func__, pwr);
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/* Set the bus voltage first (if any) */
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writeb(pwr, &host->reg->pwrcon);
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if (pwr == 0)
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return;
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/* Now enable bus power */
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pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
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writeb(pwr, &host->reg->pwrcon);
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}
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static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
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struct bounce_buffer *bbstate)
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{
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@ -334,8 +365,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
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debug(" mmc_change_clock called\n");
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/*
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* Change Tegra SDMMCx clock divisor here. Source is 216MHz,
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* PLLP_OUT0
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* Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
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*/
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if (clock == 0)
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goto out;
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@ -410,7 +440,7 @@ static void mmc_set_ios(struct mmc *mmc)
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debug("mmc_set_ios: hostctl = %08X\n", ctrl);
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}
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static void mmc_reset(struct mmc_host *host)
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static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
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{
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unsigned int timeout;
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debug(" mmc_reset called\n");
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@ -436,6 +466,14 @@ static void mmc_reset(struct mmc_host *host)
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timeout--;
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udelay(1000);
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}
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/* Set SD bus voltage & enable bus power */
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mmc_set_power(host, fls(mmc->voltages) - 1);
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debug("%s: power control = %02X, host control = %02X\n", __func__,
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readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
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/* Make sure SDIO pads are set up */
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pad_init_mmc(host);
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}
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static int mmc_core_init(struct mmc *mmc)
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@ -444,7 +482,7 @@ static int mmc_core_init(struct mmc *mmc)
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unsigned int mask;
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debug(" mmc_core_init called\n");
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mmc_reset(host);
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mmc_reset(host, mmc);
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host->version = readw(&host->reg->hcver);
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debug("host version = %x\n", host->version);
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@ -642,12 +680,21 @@ void tegra_mmc_init(void)
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const void *blob = gd->fdt_blob;
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debug("%s entry\n", __func__);
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/* See if any Tegra30 MMC controllers are present */
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count = fdtdec_find_aliases_for_id(blob, "sdhci",
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COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
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debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);
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if (process_nodes(blob, node_list, count)) {
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printf("%s: Error processing T30 mmc node(s)!\n", __func__);
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return;
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}
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/* Now look for any Tegra20 MMC controllers */
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count = fdtdec_find_aliases_for_id(blob, "sdhci",
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COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS);
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debug("%s: count of sdhci nodes is %d\n", __func__, count);
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debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);
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if (process_nodes(blob, node_list, count)) {
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printf("%s: Error processing mmc node(s)!\n", __func__);
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printf("%s: Error processing T20 mmc node(s)!\n", __func__);
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return;
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}
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}
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