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arm: Add support for LEGO MINDSTORMS EV3

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This is based on the davinci da850evm. It can boot from either the
on-board 16MB flash or from a microSD card. It also reads board
information from an I2C EEPROM.

The EV3 itself initally boots from write-protected EEPROM, so no
u-boot SPL is needed.

Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
David Lechner 2016-02-26 00:46:07 -06:00 committed by Tom Rini
parent 6f6e9439e4
commit 2ac07f75d1
10 changed files with 518 additions and 0 deletions
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4
arch/arm/mach-davinci/Kconfig
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@ -22,6 +22,9 @@ config TARGET_OMAPL138_LCDK
config TARGET_CALIMAIN
bool "Calimain board"
config TARGET_LEGOEV3
bool "LEGO MINDSTORMS EV3"
endchoice
config SYS_SOC
@ -31,5 +34,6 @@ source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
source "board/davinci/ea20/Kconfig"
source "board/omicron/calimain/Kconfig"
source "board/lego/ev3/Kconfig"
endif

10
arch/arm/mach-davinci/da850_pinmux.c
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@ -12,6 +12,16 @@
#include <asm/arch/pinmux_defs.h>
/* SPI pin muxer settings */
const struct pinmux_config spi0_pins_base[] = {
{ pinmux(3), 1, 0 }, /* SPI0_CLK */
{ pinmux(3), 1, 2 }, /* SPI0_SOMI */
{ pinmux(3), 1, 3 }, /* SPI0_SIMO */
};
const struct pinmux_config spi0_pins_scs0[] = {
{ pinmux(4), 1, 1 }, /* SPI0_SCS[0] */
};
const struct pinmux_config spi1_pins_base[] = {
{ pinmux(5), 1, 2 }, /* SPI1_CLK */
{ pinmux(5), 1, 4 }, /* SPI1_SOMI */

1
arch/arm/mach-davinci/include/mach/hardware.h
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@ -503,6 +503,7 @@ struct davinci_syscfg_regs {
#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
#define DAVINCI_SYSCFG_SUSPSRC_UART1 (1 << 19)
#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)

12
board/lego/ev3/Kconfig Normal file
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@ -0,0 +1,12 @@
if TARGET_LEGOEV3
config SYS_BOARD
default "ev3"
config SYS_VENDOR
default "lego"
config SYS_CONFIG_NAME
default "legoev3"
endif

6
board/lego/ev3/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
LEGOEV3 BOARD
M: David Lechner <david@lechnology.com>
S: Maintained
F: board/lego/ev3/
F: include/configs/legoev3.h
F: configs/legoev3_defconfig

10
board/lego/ev3/Makefile Normal file
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@ -0,0 +1,10 @@
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += legoev3.o

32
board/lego/ev3/README Normal file
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@ -0,0 +1,32 @@
Summary
=======
LEGO MINDSTORMS EV3 is a toy robot produced by the LEGO Group. It is based
on the davinci da850 evm. The EV3 has a 16MB spi flash and a SDHC microSD card
reader.
Booting
=======
The EV3 contains a bootloader in EEPROM that loads u-boot.bin from address 0x0
of the spi flash memory. Using the default configuration, u-boot will check to
see if there is a boot.scr file on the first FAT partition of the mmc. If there
is, it will run the script and boot the kernel from the uImage file also in
the FAT partition. Otherwise, it will load a kernel and rootfs from the flash.
The kernel must be stored at address 0x50000 on the flash and have a maximum
size of 3MiB. The rootfs must be a squasfs image and stored at 0x350000 in the
flash and have a maximum size of 9.3MiB. The flash starting at 0xCB0000 is
reserved for user data.
Writing image to flash
======================
The EEPROM contains a program for uploading an image file to the flash memory.
The program is started by holding down the right button on the EV3 when powering
it on. You can also `run fwupdateboot` in the u-boot shell to reboot into this
mode. The image can then be uploaded using the official LEGO MINDSTORMS EV3
software or a 3rd party program capable of uploading a firmware file.
If you are booting from the microSD card, it is enough to just write uboot.bin
to the flash. If you are not using a microSD card, you will need to create an
image file using the layout described above.

176
board/lego/ev3/legoev3.c Normal file
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@ -0,0 +1,176 @@
/*
* Copyright (C) 2016 David Lechner <david@lechnology.com>
*
* Based on da850evm.c
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* Based on da830evm.c. Original Copyrights follow:
*
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <net.h>
#include <netdev.h>
#include <spi.h>
#include <spi_flash.h>
#include <asm/arch/hardware.h>
#include <asm/arch/pinmux_defs.h>
#include <asm/io.h>
#include <asm/arch/davinci_misc.h>
#include <asm/errno.h>
#include <hwconfig.h>
#ifdef CONFIG_DAVINCI_MMC
#include <mmc.h>
#include <asm/arch/sdmmc_defs.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
u8 board_rev;
#define EEPROM_I2C_ADDR 0x50
#define EEPROM_REV_OFFSET 0x3F00
#define EEPROM_MAC_OFFSET 0x3F06
#ifdef CONFIG_DAVINCI_MMC
static struct davinci_mmc mmc_sd0 = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.version = MMC_CTLR_VERSION_2,
};
int board_mmc_init(bd_t *bis)
{
mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
/* Add slot-0 to mmc subsystem */
return davinci_mmc_init(bis, &mmc_sd0);
}
#endif
const struct pinmux_resource pinmuxes[] = {
PINMUX_ITEM(spi0_pins_base),
PINMUX_ITEM(spi0_pins_scs0),
PINMUX_ITEM(uart1_pins_txrx),
PINMUX_ITEM(i2c0_pins),
PINMUX_ITEM(mmc0_pins),
};
const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
const struct lpsc_resource lpsc[] = {
{ DAVINCI_LPSC_SPI0 }, /* Serial Flash */
{ DAVINCI_LPSC_UART1 }, /* console */
{ DAVINCI_LPSC_MMC_SD },
};
const int lpsc_size = ARRAY_SIZE(lpsc);
u32 get_board_rev(void)
{
u8 buf[2];
if (!board_rev) {
if (i2c_read(EEPROM_I2C_ADDR, EEPROM_REV_OFFSET, 2, buf, 2)) {
printf("\nBoard revision read failed!\n");
} else {
/*
* Board rev 3 has MAC address at EEPROM_REV_OFFSET.
* Other revisions have checksum at EEPROM_REV_OFFSET+1
* to detect this.
*/
if ((buf[0] ^ buf[1]) == 0xFF)
board_rev = buf[0];
else
board_rev = 3;
}
}
return board_rev;
}
/*
* The Bluetooth MAC address serves as the board serial number.
*/
void get_board_serial(struct tag_serialnr *serialnr)
{
u32 offset;
u8 buf[6];
if (!board_rev)
board_rev = get_board_rev();
/* Board rev 3 has MAC address where rev should be */
offset = (board_rev == 3) ? EEPROM_REV_OFFSET : EEPROM_MAC_OFFSET;
if (i2c_read(EEPROM_I2C_ADDR, offset, 2, buf, 6)) {
printf("\nBoard serial read failed!\n");
} else {
u8 *nr;
nr = (u8 *)&serialnr->low;
nr[0] = buf[5];
nr[1] = buf[4];
nr[2] = buf[3];
nr[3] = buf[2];
nr = (u8 *)&serialnr->high;
nr[0] = buf[1];
nr[1] = buf[0];
nr[2] = 0;
nr[3] = 0;
}
}
int board_early_init_f(void)
{
/*
* Power on required peripherals
* ARM does not have access by default to PSC0 and PSC1
* assuming here that the DSP bootloader has set the IOPU
* such that PSC access is available to ARM
*/
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
return 1;
return 0;
}
int board_init(void)
{
#ifndef CONFIG_USE_IRQ
irq_init();
#endif
/* arch number of the board */
/* LEGO didn't register for a unique number and uses da850evm */
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
/* address of boot parameters */
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
/* setup the SUSPSRC for ARM to control emulation suspend */
writel(readl(&davinci_syscfg_regs->suspsrc) &
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
DAVINCI_SYSCFG_SUSPSRC_UART1),
&davinci_syscfg_regs->suspsrc);
/* configure pinmux settings */
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1;
/* enable the console UART */
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
DAVINCI_UART_PWREMU_MGMT_UTRST),
&davinci_uart1_ctrl_regs->pwremu_mgmt);
return 0;
}

12
configs/legoev3_defconfig Normal file
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@ -0,0 +1,12 @@
CONFIG_ARM=y
CONFIG_ARCH_DAVINCI=y
CONFIG_TARGET_LEGOEV3=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
CONFIG_AUTOBOOT_STOP_STR="l"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SYS_NS16550=y

255
include/configs/legoev3.h Normal file
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@ -0,0 +1,255 @@
/*
* Copyright (C) 2016 David Lechner <david@lechnology.com>
*
* Based on da850evm.h
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* Based on davinci_dvevm.h. Original Copyrights follow:
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* SoC Configuration
*/
#define CONFIG_MACH_DAVINCI_DA850_EVM
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_DA850_PLL_INIT
#define CONFIG_SYS_DA850_DDR_INIT
#define CONFIG_SYS_TEXT_BASE 0xc1080000
/*
* Memory Info
*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
DAVINCI_SYSCFG_SUSPSRC_SPI0 | \
DAVINCI_SYSCFG_SUSPSRC_UART1 | \
DAVINCI_SYSCFG_SUSPSRC_EMAC | \
DAVINCI_SYSCFG_SUSPSRC_I2C)
/*
* PLL configuration
*/
#define CONFIG_SYS_DV_CLKMODE 0
#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
#define CONFIG_SYS_DA850_PLL0_PLLM 24
#define CONFIG_SYS_DA850_PLL1_PLLM 21
/*
* DDR2 memory configuration
*/
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
DV_DDR_PHY_EXT_STRBEN | \
(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
(0x3 << DV_DDR_SDCR_CL_SHIFT) | \
(0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
(14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
(2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
(1 << DV_DDR_SDTMR1_WR_SHIFT) | \
(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
(8 << DV_DDR_SDTMR1_RC_SHIFT) | \
(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
(0 << DV_DDR_SDTMR1_WTR_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
(0 << DV_DDR_SDTMR2_XP_SHIFT) | \
(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
(17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
(0 << DV_DDR_SDTMR2_CKE_SHIFT))
#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
/*
* Serial Driver info
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SPI
#define CONFIG_CMD_SF
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
/*
* I2C Configuration
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*
* U-Boot general configuration
*/
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_OF_LIBFDT
/*
* Linux Information
*/
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SETUP_INITRD_TAG
#define CONFIG_BOOTDELAY 0
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTCOMMAND \
"if mmc rescan; then " \
"if run loadbootscr; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcargs; " \
"run mmcboot; " \
"else " \
"run flashargs; " \
"run flashboot; " \
"fi; " \
"fi; " \
"else " \
"run flashargs; " \
"run flashboot; " \
"fi"
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=EV3\0" \
"memsize=64M\0" \
"filesyssize=10M\0" \
"verify=n\0" \
"console=ttyS1,115200n8\0" \
"bootscraddr=0xC0600000\0" \
"loadaddr=0xC0007FC0\0" \
"filesysaddr=0xC1180000\0" \
"fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \
"mmcargs=setenv bootargs mem=${memsize} console=${console} root=/dev/mmcblk0p2 rw rootwait lpj=747520\0" \
"mmcboot=bootm ${loadaddr}\0" \
"flashargs=setenv bootargs mem=${memsize} initrd=${filesysaddr},${filesyssize} root=/dev/ram0 rw rootfstype=squashfs console=${console} lpj=747520\0" \
"flashboot=sf probe 0; sf read ${loadaddr} 0x50000 0x300000; sf read ${filesysaddr} 0x350000 0x960000; bootm ${loadaddr}\0" \
"loadimage=fatload mmc 0 ${loadaddr} uImage\0" \
"loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \
"bootscript=source ${bootscraddr}\0" \
/*
* U-Boot commands
*/
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif
#define CONFIG_CMD_SPI
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (16 << 10)
/* SD/MMC configuration */
#define CONFIG_MMC
#define CONFIG_DAVINCI_MMC_SD1
#define CONFIG_GENERIC_MMC
#define CONFIG_DAVINCI_MMC
/*
* Enable MMC commands only when
* MMC support is present
*/
#ifdef CONFIG_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT3
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MMC
#endif
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
#define CONFIG_SYS_INIT_SP_ADDR 0x80010000
#endif /* __CONFIG_H */