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Initialise correct GPMC WAITx irq for AM33xx

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Currently WAIT0 irq is reset and then WAIT1 irq is enabled.
Fix it such that WAIT0 irq is enabled instead.

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
This commit is contained in:
Mark Jackson 2013-02-21 02:49:38 +00:00 committed by Tom Rini
parent fc33705e66
commit 296de3bbec
1 changed files with 1 additions and 1 deletions
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arch/arm/cpu/armv7/am33xx/mem.c
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@ -83,7 +83,7 @@ void gpmc_init(void)
/* global settings */
writel(0x00000008, &gpmc_cfg->sysconfig);
writel(0x00000100, &gpmc_cfg->irqstatus);
writel(0x00000200, &gpmc_cfg->irqenable);
writel(0x00000100, &gpmc_cfg->irqenable);
writel(0x00000012, &gpmc_cfg->config);
/*
* Disable the GPMC0 config set by ROM code