IXP42x PCI rewrite
clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc. code and use u-boot's PCI infrastructure instead. Move board-specific PCI setup code (clock/reset) to board directory. Signed-off-by: Michael Schwingen <michael@schwingen.org>
This commit is contained in:
Michael Schwingen
Albert ARIBAUD
parent
904ec57b33
commit
29161f47d0
@ -22,88 +22,21 @@
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* MA 02111-1307 USA
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*/
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#ifndef _IXP425PCI_H_
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#define _IXP425PCI_H_
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#ifndef _IXP425PCI_H
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#define _IXP425PCI_H
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#define TRUE 1
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#define FALSE 0
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#define OK 0
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#define ERROR -1
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#define BOOL int
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#define IXP425_PCI_MAX_BAR_PER_FUNC 6
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#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
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IXP425_PCI_MAX_FUNC_ON_BUS)
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enum PciBarId
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{
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CSR_BAR=0,
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IO_BAR,
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SD_BAR,
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NO_BAR
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};
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/*Base address register descriptor*/
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typedef struct
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{
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unsigned int size;
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unsigned int address;
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} PciBar;
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typedef struct
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{
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unsigned int bus;
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unsigned int device;
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unsigned int func;
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unsigned int irq;
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BOOL error;
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unsigned short vendor_id;
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unsigned short device_id;
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/*We need an extra entry in this array for dummy placeholder*/
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PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
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} PciDevice;
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struct pci_controller;
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extern void pci_ixp_init(struct pci_controller *hose);
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/* Mask definitions*/
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#define IXP425_PCI_TOP_WORD_OF_LONG_MASK 0xffff0000
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#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK 0xff000000
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#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK 0x0000ffff
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#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff
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#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f
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#define IXP425_PCI_MAX_UINT32 0xffffffff
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#define IXP425_PCI_BAR_QUERY 0xffffffff
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#define IXP425_PCI_BAR_MEM_BASE 0x100000
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#define IXP425_PCI_BAR_IO_BASE 0x000000
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/*define the maximum number of bus segments - we support a single segment*/
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#define IXP425_PCI_MAX_BUS 1
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/*define the maximum number of cards per bus segment*/
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#define IXP425_PCI_MAX_DEV 4
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/*define the maximum number of functions per device*/
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#define IXP425_PCI_MAX_FUNC 8
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/* define the maximum number of separate functions that we can
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potentially have on the bus*/
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#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC * \
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IXP425_PCI_MAX_DEV * \
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IXP425_PCI_MAX_BUS)
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/*define the maximum number of BARs per function*/
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#define IXP425_PCI_MAX_BAR_PER_FUNC 6
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#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
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IXP425_PCI_MAX_FUNC_ON_BUS)
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#define PCI_NP_CBE_BESL (4)
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#define PCI_NP_AD_FUNCSL (8)
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#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
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#define REG_READ(b,o,v) ((v)=(*(volatile unsigned int*)((b+o))))
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#define PCI_DELAY 500
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#define USEC_LOOP_COUNT 533
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#define PCI_SETTLE_USEC 200
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#define PCI_MIN_RESET_ASSERT_USEC 2000
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/*Register addressing definitions for PCI controller configuration
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and status registers*/
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@ -150,28 +83,6 @@ typedef struct
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#define NP_CMD_CONFIGWRITE (0xb)
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*/
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/*define the default setting of the AHB memory base reg*/
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#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
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#define IXP425_PCI_AHBIOBASE_DEFAULT 0x0
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#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
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/*define the default settings for the controller's BARs*/
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#ifdef IXP425_PCI_SIMPLE_MAPPING
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#define IXP425_PCI_BAR_0_DEFAULT 0x00000000
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#define IXP425_PCI_BAR_1_DEFAULT 0x01000000
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#define IXP425_PCI_BAR_2_DEFAULT 0x02000000
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#define IXP425_PCI_BAR_3_DEFAULT 0x03000000
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#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
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#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
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#else
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#define IXP425_PCI_BAR_0_DEFAULT 0x40000000
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#define IXP425_PCI_BAR_1_DEFAULT 0x41000000
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#define IXP425_PCI_BAR_2_DEFAULT 0x42000000
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#define IXP425_PCI_BAR_3_DEFAULT 0x43000000
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#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
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#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
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#endif
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/*Configuration Port register bit definitions*/
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#define PCI_CRP_WRITE BIT(16)
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@ -228,17 +139,6 @@ typedef struct
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#define PCI_CFG_SPECIAL_USE 0x41
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#define PCI_CFG_MODE 0x43
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/*Specify the initial command we send to PCI devices*/
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#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE \
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| PCI_CMD_MEM_ENABLE \
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| PCI_CMD_MASTER_ENABLE \
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| PCI_CMD_WI_ENABLE)
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/*define the sub vendor and subsystem to be used */
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#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
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#define PCI_IRQ_LINES 4
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#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
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#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
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#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
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@ -287,26 +187,4 @@ typedef struct
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#define PCI_DMACTRL_PADC1 BIT(14)
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#define PCI_DMACTRL_PADE1 BIT(15)
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/* GPIO related register */
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#undef IXP425_GPIO_GPOUTR
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#undef IXP425_GPIO_GPOER
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#undef IXP425_GPIO_GPINR
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#undef IXP425_GPIO_GPISR
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#undef IXP425_GPIO_GPIT1R
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#undef IXP425_GPIO_GPIT2R
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#undef IXP425_GPIO_GPCLKR
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#define IXP425_GPIO_GPOUTR 0xC8004000
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#define IXP425_GPIO_GPOER 0xC8004004
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#define IXP425_GPIO_GPINR 0xC8004008
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#define IXP425_GPIO_GPISR 0xC800400C
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#define IXP425_GPIO_GPIT1R 0xC8004010
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#define IXP425_GPIO_GPIT2R 0xC8004014
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#define IXP425_GPIO_GPCLKR 0xC8004018
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#define READ_GPIO_REG(addr,val) \
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(val) = *((volatile int *)(addr));
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#define WRITE_GPIO_REG(addr,val) \
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*((volatile int *)(addr)) = (val);
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#endif
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@ -50,7 +50,6 @@ PCI_HOSE_OP(write, byte, u8)
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PCI_HOSE_OP(write, word, u16)
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PCI_HOSE_OP(write, dword, u32)
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#ifndef CONFIG_IXP425
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#define PCI_OP(rw, size, type, error_code) \
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int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
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{ \
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@ -71,7 +70,6 @@ PCI_OP(read, dword, u32 *, *value = 0xffffffff)
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PCI_OP(write, byte, u8, )
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PCI_OP(write, word, u16, )
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PCI_OP(write, dword, u32, )
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#endif /* CONFIG_IXP425 */
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#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
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int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
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@ -190,7 +188,6 @@ int pci_last_busno(void)
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return hose->last_busno;
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}
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#ifndef CONFIG_IXP425
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pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
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{
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struct pci_controller * hose;
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@ -246,7 +243,6 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
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return (-1);
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}
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#endif /* CONFIG_IXP425 */
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pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
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{
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@ -11,7 +11,7 @@
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#include <common.h>
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#if (!defined(__I386__) && !defined(CONFIG_IXDP425))
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#if !defined(__I386__)
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#include <asm/processor.h>
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#include <asm/io.h>
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@ -20,15 +20,6 @@
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#define cfg_read(val, addr, type, op) *val = op((type)(addr))
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#define cfg_write(val, addr, type, op) op((type *)(addr), (val))
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#ifdef CONFIG_IXP425
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extern unsigned char in_8 (volatile unsigned *addr);
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extern unsigned short in_le16 (volatile unsigned *addr);
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extern unsigned in_le32 (volatile unsigned *addr);
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extern void out_8 (volatile unsigned *addr, char val);
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extern void out_le16 (volatile unsigned *addr, unsigned short val);
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extern void out_le32 (volatile unsigned *addr, unsigned int val);
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#endif /* CONFIG_IXP425 */
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#if defined(CONFIG_MPC8260)
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#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
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static int \
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@ -134,4 +125,4 @@ void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
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hose->cfg_data = (unsigned char *) cfg_data;
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}
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#endif /* !__I386__ && !CONFIG_IXDP425 */
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#endif /* !__I386__ */
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@ -1,5 +1,8 @@
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/*
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* IXP PCI Init
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*
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* (C) Copyright 2011
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* Michael Schwingen, michael@schwingen.org
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* (C) Copyright 2004 eslab.whut.edu.cn
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* Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
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*
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@ -22,7 +25,6 @@
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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@ -30,542 +32,336 @@
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#include <asm/arch/ixp425.h>
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#include <asm/arch/ixp425pci.h>
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static void non_prefetch_read (unsigned int addr, unsigned int cmd,
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unsigned int *data);
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static void non_prefetch_write (unsigned int addr, unsigned int cmd,
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unsigned int data);
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static void configure_pins (void);
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static void sys_pci_gpio_clock_config (void);
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static void pci_bus_scan (void);
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static int pci_device_exists (unsigned int deviceNo);
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static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus,
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unsigned int dev, unsigned int func);
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static void sys_pci_device_bars_write (void);
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static void calc_bars (PciBar * Bars[], unsigned int nBars,
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unsigned int startAddr);
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DECLARE_GLOBAL_DATA_PTR;
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static void non_prefetch_read(unsigned int addr, unsigned int cmd,
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unsigned int *data);
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static void non_prefetch_write(unsigned int addr, unsigned int cmd,
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unsigned int data);
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/*define the sub vendor and subsystem to be used */
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#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
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#define PCI_MEMORY_BUS 0x00000000
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#define PCI_MEMORY_PHY 0x48000000
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#define PCI_MEMORY_PHY 0x00000000
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#define PCI_MEMORY_SIZE 0x04000000
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#define PCI_MEM_BUS 0x40000000
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#define PCI_MEM_BUS 0x48000000
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#define PCI_MEM_PHY 0x00000000
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#define PCI_MEM_SIZE 0x04000000
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#define PCI_IO_BUS 0x40000000
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#define PCI_IO_PHY 0x50000000
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#define PCI_IO_SIZE 0x10000000
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#define PCI_IO_BUS 0x00000000
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#define PCI_IO_PHY 0x00000000
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#define PCI_IO_SIZE 0x00010000
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struct pci_controller hose;
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/* build address value for config sycle */
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static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg)
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{
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unsigned int bus = PCI_BUS(bdf);
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unsigned int dev = PCI_DEV(bdf);
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unsigned int func = PCI_FUNC(bdf);
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unsigned int addr;
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unsigned int nDevices;
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unsigned int nMBars;
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unsigned int nIOBars;
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PciBar *memBars[IXP425_PCI_MAX_BAR];
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PciBar *ioBars[IXP425_PCI_MAX_BAR];
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PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS];
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if (bus) { /* secondary bus, use type 1 config cycle */
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addr = bdf | (reg & ~3) | 1;
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} else {
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/*
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primary bus, type 0 config cycle. address bits 31:28
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specify the device 10:8 specify the function
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*/
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addr = BIT((31 - dev)) | (func << 8) | (reg & ~3);
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}
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int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val)
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return addr;
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}
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static int pci_config_status(void)
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{
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unsigned int regval;
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regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET);
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if ((regval & PCI_ISR_PFE) == 0)
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return OK;
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/* no device present, make sure that the master abort bit is reset */
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writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET);
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return ERROR;
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}
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static int pci_ixp_hose_read_config_dword(struct pci_controller *hose,
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pci_dev_t bdf, int where, unsigned int *val)
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{
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unsigned int retval;
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unsigned int addr;
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int stat;
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/*address bits 31:28 specify the device 10:8 specify the function */
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debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where);
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/*Set the address to be read */
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addr = BIT ((31 - dev)) | (where & ~3);
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non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval);
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addr = pci_config_addr(bdf, where);
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non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval);
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*val = retval;
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return (OK);
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stat = pci_config_status();
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if (stat < 0)
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*val = -1;
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debug("-> val %x, status %x\n", *val, stat);
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return stat;
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}
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int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val)
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static int pci_ixp_hose_read_config_word(struct pci_controller *hose,
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pci_dev_t bdf, int where, unsigned short *val)
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{
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unsigned int n;
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unsigned int retval;
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unsigned int addr;
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unsigned int byteEnables;
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int stat;
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debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where);
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n = where % 4;
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/*byte enables are 4 bits active low, the position of each
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bit maps to the byte that it enables */
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byteEnables =
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(~(BIT (n) | BIT ((n + 1)))) &
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(~(BIT(n) | BIT((n + 1)))) &
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IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
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byteEnables = byteEnables << PCI_NP_CBE_BESL;
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/*address bits 31:28 specify the device 10:8 specify the function */
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/*Set the address to be read */
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addr = BIT ((31 - dev)) | (where & ~3);
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non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
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addr = pci_config_addr(bdf, where);
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non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
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/*Pick out the word we are interested in */
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*val = (retval >> (8 * n));
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*val = retval >> (8 * n);
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return (OK);
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stat = pci_config_status();
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if (stat < 0)
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*val = -1;
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debug("-> val %x, status %x\n", *val, stat);
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return stat;
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}
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int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val)
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static int pci_ixp_hose_read_config_byte(struct pci_controller *hose,
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pci_dev_t bdf, int where, unsigned char *val)
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{
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unsigned int retval;
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unsigned int n;
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unsigned int byteEnables;
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unsigned int addr;
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int stat;
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debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where);
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n = where % 4;
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/*byte enables are 4 bits, active low, the position of each
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bit maps to the byte that it enables */
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byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
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byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
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byteEnables = byteEnables << PCI_NP_CBE_BESL;
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/*address bits 31:28 specify the device, 10:8 specify the function */
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/*Set the address to be read */
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addr = BIT ((31 - dev)) | (where & ~3);
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non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
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addr = pci_config_addr(bdf, where);
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non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
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/*Pick out the byte we are interested in */
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*val = (retval >> (8 * n));
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*val = retval >> (8 * n);
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return (OK);
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stat = pci_config_status();
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if (stat < 0)
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*val = -1;
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debug("-> val %x, status %x\n", *val, stat);
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return stat;
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}
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|
||||
int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val)
|
||||
static int pci_ixp_hose_write_config_byte(struct pci_controller *hose,
|
||||
pci_dev_t bdf, int where, unsigned char val)
|
||||
{
|
||||
unsigned int addr;
|
||||
unsigned int byteEnables;
|
||||
unsigned int n;
|
||||
unsigned int ldata;
|
||||
int stat;
|
||||
|
||||
debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x",
|
||||
bdf, where, val);
|
||||
n = where % 4;
|
||||
/*byte enables are 4 bits active low, the position of each
|
||||
bit maps to the byte that it enables */
|
||||
byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
|
||||
byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
|
||||
byteEnables = byteEnables << PCI_NP_CBE_BESL;
|
||||
ldata = val << (8 * n);
|
||||
/*address bits 31:28 specify the device 10:8 specify the function */
|
||||
/*Set the address to be written */
|
||||
addr = BIT ((31 - dev)) | (where & ~3);
|
||||
non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
|
||||
addr = pci_config_addr(bdf, where);
|
||||
non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
|
||||
|
||||
return (OK);
|
||||
stat = pci_config_status();
|
||||
debug("-> status %x\n", stat);
|
||||
return stat;
|
||||
}
|
||||
|
||||
int pci_write_config_word (pci_dev_t dev, int where, unsigned short val)
|
||||
static int pci_ixp_hose_write_config_word(struct pci_controller *hose,
|
||||
pci_dev_t bdf, int where, unsigned short val)
|
||||
{
|
||||
unsigned int addr;
|
||||
unsigned int byteEnables;
|
||||
unsigned int n;
|
||||
unsigned int ldata;
|
||||
int stat;
|
||||
|
||||
debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x",
|
||||
bdf, where, val);
|
||||
n = where % 4;
|
||||
/*byte enables are 4 bits active low, the position of each
|
||||
bit maps to the byte that it enables */
|
||||
byteEnables =
|
||||
(~(BIT (n) | BIT ((n + 1)))) &
|
||||
(~(BIT(n) | BIT((n + 1)))) &
|
||||
IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
|
||||
byteEnables = byteEnables << PCI_NP_CBE_BESL;
|
||||
ldata = val << (8 * n);
|
||||
/*address bits 31:28 specify the device 10:8 specify the function */
|
||||
/*Set the address to be written */
|
||||
addr = BIT (31 - dev) | (where & ~3);
|
||||
non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
|
||||
addr = pci_config_addr(bdf, where);
|
||||
non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
|
||||
|
||||
return (OK);
|
||||
stat = pci_config_status();
|
||||
debug("-> status %x\n", stat);
|
||||
return stat;
|
||||
}
|
||||
|
||||
int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val)
|
||||
static int pci_ixp_hose_write_config_dword(struct pci_controller *hose,
|
||||
pci_dev_t bdf, int where, unsigned int val)
|
||||
{
|
||||
unsigned int addr;
|
||||
int stat;
|
||||
|
||||
/*address bits 31:28 specify the device 10:8 specify the function */
|
||||
debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x",
|
||||
bdf, where, val);
|
||||
/*Set the address to be written */
|
||||
addr = BIT (31 - dev) | (where & ~3);
|
||||
non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val);
|
||||
addr = pci_config_addr(bdf, where);
|
||||
non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val);
|
||||
|
||||
return (OK);
|
||||
stat = pci_config_status();
|
||||
debug("-> status %x\n", stat);
|
||||
return stat;
|
||||
}
|
||||
|
||||
void non_prefetch_read (unsigned int addr,
|
||||
unsigned int cmd, unsigned int *data)
|
||||
static void non_prefetch_read(unsigned int addr,
|
||||
unsigned int cmd, unsigned int *data)
|
||||
{
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
|
||||
writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
|
||||
|
||||
/*set up and execute the read */
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
|
||||
writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
|
||||
|
||||
/*The result of the read is now in np_rdata */
|
||||
REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data);
|
||||
*data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void non_prefetch_write (unsigned int addr,
|
||||
unsigned int cmd, unsigned int data)
|
||||
static void non_prefetch_write(unsigned int addr,
|
||||
unsigned int cmd, unsigned int data)
|
||||
{
|
||||
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
|
||||
writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
|
||||
/*set up the write */
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
|
||||
writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
|
||||
/*Execute the write by writing to NP_WDATA */
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data);
|
||||
writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* PCI controller config registers are accessed through these functions
|
||||
* i.e. these allow us to set up our own BARs etc.
|
||||
*/
|
||||
void crp_read (unsigned int offset, unsigned int *data)
|
||||
static void crp_write(unsigned int offset, unsigned int data)
|
||||
{
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset);
|
||||
REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data);
|
||||
/*
|
||||
* The CRP address register bit 16 indicates that we want to do a
|
||||
* write
|
||||
*/
|
||||
writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET);
|
||||
writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET);
|
||||
}
|
||||
|
||||
void crp_write (unsigned int offset, unsigned int data)
|
||||
void pci_ixp_init(struct pci_controller *hose)
|
||||
{
|
||||
/*The CRP address register bit 16 indicates that we want to do a write */
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET,
|
||||
PCI_CRP_WRITE | offset);
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data);
|
||||
}
|
||||
unsigned int csr;
|
||||
|
||||
/*struct pci_controller *hose*/
|
||||
void pci_ixp_init (struct pci_controller *hose)
|
||||
{
|
||||
unsigned int regval;
|
||||
/*
|
||||
* Specify that the AHB bus is operating in big endian mode. Set up
|
||||
* byte lane swapping between little-endian PCI and the big-endian
|
||||
* AHB bus
|
||||
*/
|
||||
#ifdef __ARMEB__
|
||||
csr = PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
|
||||
#else
|
||||
csr = PCI_CSR_ABE;
|
||||
#endif
|
||||
writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
|
||||
|
||||
writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET);
|
||||
|
||||
/*
|
||||
* We configure the PCI inbound memory windows to be
|
||||
* 1:1 mapped to SDRAM
|
||||
*/
|
||||
crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000);
|
||||
crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000);
|
||||
crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000);
|
||||
crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000);
|
||||
|
||||
/*
|
||||
* Enable CSR window at 64 MiB to allow PCI masters
|
||||
* to continue prefetching past 64 MiB boundary.
|
||||
*/
|
||||
crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000);
|
||||
/*
|
||||
* Enable the IO window to be way up high, at 0xfffffc00
|
||||
*/
|
||||
crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01);
|
||||
|
||||
/*Setup PCI-AHB and AHB-PCI address mappings */
|
||||
writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET);
|
||||
|
||||
writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET);
|
||||
|
||||
writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET);
|
||||
|
||||
crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
|
||||
|
||||
crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
|
||||
udelay(1000);
|
||||
|
||||
/* clear error bits in status register */
|
||||
writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE,
|
||||
PCI_CSR_BASE + PCI_ISR_OFFSET);
|
||||
|
||||
/*
|
||||
* Set Initialize Complete in PCI Control Register: allow IXP4XX to
|
||||
* respond to PCI configuration cycles.
|
||||
*/
|
||||
csr |= PCI_CSR_IC;
|
||||
writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
|
||||
|
||||
hose->first_busno = 0;
|
||||
hose->last_busno = 0x00;
|
||||
hose->last_busno = 0;
|
||||
|
||||
/* System memory space */
|
||||
pci_set_region (hose->regions + 0,
|
||||
PCI_MEMORY_BUS,
|
||||
PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
|
||||
pci_set_region(hose->regions + 0,
|
||||
PCI_MEMORY_BUS,
|
||||
PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
|
||||
|
||||
/* PCI memory space */
|
||||
pci_set_region (hose->regions + 1,
|
||||
PCI_MEM_BUS,
|
||||
PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
|
||||
pci_set_region(hose->regions + 1,
|
||||
PCI_MEM_BUS,
|
||||
PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
|
||||
/* PCI I/O space */
|
||||
pci_set_region (hose->regions + 2,
|
||||
PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
|
||||
pci_set_region(hose->regions + 2,
|
||||
PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
|
||||
pci_register_hose (hose);
|
||||
pci_set_ops(hose,
|
||||
pci_ixp_hose_read_config_byte,
|
||||
pci_ixp_hose_read_config_word,
|
||||
pci_ixp_hose_read_config_dword,
|
||||
pci_ixp_hose_write_config_byte,
|
||||
pci_ixp_hose_write_config_word,
|
||||
pci_ixp_hose_write_config_dword);
|
||||
|
||||
/*
|
||||
==========================================================
|
||||
Init IXP PCI
|
||||
==========================================================
|
||||
*/
|
||||
REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
|
||||
regval |= 1 << 2;
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
|
||||
|
||||
configure_pins ();
|
||||
|
||||
READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
|
||||
WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13)));
|
||||
udelay (533);
|
||||
sys_pci_gpio_clock_config ();
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0);
|
||||
udelay (100);
|
||||
READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
|
||||
WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13));
|
||||
udelay (533);
|
||||
crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT);
|
||||
crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT);
|
||||
crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT);
|
||||
crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT);
|
||||
crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT);
|
||||
crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT);
|
||||
/*Setup PCI-AHB and AHB-PCI address mappings */
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET,
|
||||
IXP425_PCI_AHBMEMBASE_DEFAULT);
|
||||
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET,
|
||||
IXP425_PCI_AHBIOBASE_DEFAULT);
|
||||
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET,
|
||||
IXP425_PCI_PCIMEMBASE_DEFAULT);
|
||||
|
||||
crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
|
||||
|
||||
REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
|
||||
regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS;
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
|
||||
crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
|
||||
udelay (1000);
|
||||
|
||||
pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD);
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
|
||||
| PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
|
||||
#ifdef CONFIG_PCI_SCAN_SHOW
|
||||
printf ("Device bus dev func deviceID vendorID \n");
|
||||
#endif
|
||||
pci_bus_scan ();
|
||||
}
|
||||
|
||||
void configure_pins (void)
|
||||
{
|
||||
unsigned int regval;
|
||||
|
||||
/* Disable clock on GPIO PIN 14 */
|
||||
READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||
WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8)));
|
||||
READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||
|
||||
READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
|
||||
WRITE_GPIO_REG (IXP425_GPIO_GPOER,
|
||||
(((~(3 << 13)) & regval) | (0xf << 8)));
|
||||
READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
|
||||
|
||||
READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
|
||||
WRITE_GPIO_REG (IXP425_GPIO_GPIT2R,
|
||||
(regval &
|
||||
((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1)));
|
||||
READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
|
||||
|
||||
READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
|
||||
WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8)));
|
||||
READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
|
||||
}
|
||||
|
||||
void sys_pci_gpio_clock_config (void)
|
||||
{
|
||||
unsigned int regval;
|
||||
|
||||
READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||
regval |= 0x1 << 4;
|
||||
WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||
READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||
regval |= 0x1 << 8;
|
||||
WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
|
||||
}
|
||||
|
||||
void pci_bus_scan (void)
|
||||
{
|
||||
unsigned int bus = 0, dev, func = 0;
|
||||
unsigned short data16;
|
||||
unsigned int data32;
|
||||
unsigned char intPin;
|
||||
|
||||
/* Assign first device to ourselves */
|
||||
devices[0].bus = 0;
|
||||
devices[0].device = 0;
|
||||
devices[0].func = 0;
|
||||
|
||||
crp_read (PCI_CFG_VENDOR_ID, &data32);
|
||||
|
||||
devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK;
|
||||
devices[0].device_id = data32 >> 16;
|
||||
devices[0].error = FALSE;
|
||||
devices[0].bar[NO_BAR].size = 0; /*dummy - required */
|
||||
|
||||
nDevices = 1;
|
||||
|
||||
nMBars = 0;
|
||||
nIOBars = 0;
|
||||
|
||||
for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) {
|
||||
|
||||
/*Check whether a device is present */
|
||||
if (pci_device_exists (dev) != TRUE) {
|
||||
|
||||
/*Clear error bits in ISR, write 1 to clear */
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
|
||||
| PCI_ISR_PFE | PCI_ISR_PPE |
|
||||
PCI_ISR_AHBE);
|
||||
continue;
|
||||
}
|
||||
|
||||
/*A device is present, add an entry to the array */
|
||||
devices[nDevices].bus = bus;
|
||||
devices[nDevices].device = dev;
|
||||
devices[nDevices].func = func;
|
||||
|
||||
pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16);
|
||||
|
||||
devices[nDevices].vendor_id = data16;
|
||||
|
||||
pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16);
|
||||
devices[nDevices].device_id = data16;
|
||||
|
||||
/*The device is functioning correctly, set error to FALSE */
|
||||
devices[nDevices].error = FALSE;
|
||||
|
||||
/*Figure out what BARs are on this device */
|
||||
sys_pci_bar_info_get (nDevices, bus, dev, func);
|
||||
/*Figure out what INTX# line the card uses */
|
||||
pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin);
|
||||
|
||||
/*assign the appropriate irq line */
|
||||
if (intPin > PCI_IRQ_LINES) {
|
||||
devices[nDevices].error = TRUE;
|
||||
} else if (intPin != 0) {
|
||||
/*This device uses an interrupt line */
|
||||
/*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */
|
||||
devices[nDevices].irq = intPin;
|
||||
}
|
||||
#ifdef CONFIG_PCI_SCAN_SHOW
|
||||
printf ("%06d %03d %03d %04d %08d %08x\n", nDevices,
|
||||
devices[nDevices].vendor_id);
|
||||
#endif
|
||||
nDevices++;
|
||||
|
||||
}
|
||||
|
||||
calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE);
|
||||
sys_pci_device_bars_write ();
|
||||
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
|
||||
| PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
|
||||
}
|
||||
|
||||
void sys_pci_bar_info_get (unsigned int devnum,
|
||||
unsigned int bus,
|
||||
unsigned int dev, unsigned int func)
|
||||
{
|
||||
unsigned int data32;
|
||||
unsigned int tmp;
|
||||
unsigned int size;
|
||||
|
||||
pci_write_config_dword (devnum,
|
||||
PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY);
|
||||
pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32);
|
||||
|
||||
devices[devnum].bar[0].address = (data32 & 1);
|
||||
|
||||
if (data32 & 1) {
|
||||
/* IO space */
|
||||
tmp = data32 & ~0x3;
|
||||
size = ~(tmp - 1);
|
||||
devices[devnum].bar[0].size = size;
|
||||
|
||||
if (nIOBars < IXP425_PCI_MAX_BAR) {
|
||||
ioBars[nIOBars++] = &devices[devnum].bar[0];
|
||||
}
|
||||
} else {
|
||||
/* Mem space */
|
||||
tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
|
||||
size = ~(tmp - 1);
|
||||
devices[devnum].bar[0].size = size;
|
||||
|
||||
if (nMBars < IXP425_PCI_MAX_BAR) {
|
||||
memBars[nMBars++] = &devices[devnum].bar[0];
|
||||
} else {
|
||||
devices[devnum].error = TRUE;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
devices[devnum].bar[1].size = 0;
|
||||
}
|
||||
|
||||
void sortBars (PciBar * Bars[], unsigned int nBars)
|
||||
{
|
||||
unsigned int i, j;
|
||||
PciBar *tmp;
|
||||
|
||||
if (nBars == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Sort biggest to smallest */
|
||||
for (i = 0; i < nBars - 1; i++) {
|
||||
for (j = i + 1; j < nBars; j++) {
|
||||
if (Bars[j]->size > Bars[i]->size) {
|
||||
/* swap them */
|
||||
tmp = Bars[i];
|
||||
Bars[i] = Bars[j];
|
||||
Bars[j] = tmp;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
if (nBars == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < nBars; i++) {
|
||||
Bars[i]->address |= startAddr;
|
||||
startAddr += Bars[i]->size;
|
||||
}
|
||||
}
|
||||
|
||||
void sys_pci_device_bars_write (void)
|
||||
{
|
||||
unsigned int i;
|
||||
int addr;
|
||||
|
||||
for (i = 1; i < nDevices; i++) {
|
||||
if (devices[i].error) {
|
||||
continue;
|
||||
}
|
||||
|
||||
pci_write_config_dword (devices[i].device,
|
||||
PCI_CFG_BASE_ADDRESS_0,
|
||||
devices[i].bar[0].address);
|
||||
addr = BIT (31 - devices[i].device) |
|
||||
(0 << PCI_NP_AD_FUNCSL) |
|
||||
(PCI_CFG_BASE_ADDRESS_0 & ~3);
|
||||
pci_write_config_dword (devices[i].device,
|
||||
PCI_CFG_DEV_INT_LINE, devices[i].irq);
|
||||
|
||||
pci_write_config_word (devices[i].device,
|
||||
PCI_CFG_COMMAND, INITIAL_PCI_CMD);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int pci_device_exists (unsigned int deviceNo)
|
||||
{
|
||||
unsigned int vendorId;
|
||||
unsigned int regval;
|
||||
|
||||
pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId);
|
||||
|
||||
/* There are two ways to find out an empty device.
|
||||
* 1. check Master Abort bit after the access.
|
||||
* 2. check whether the vendor id read back is 0x0.
|
||||
*/
|
||||
REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval);
|
||||
if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) {
|
||||
return TRUE;
|
||||
}
|
||||
/*no device present, make sure that the master abort bit is reset */
|
||||
|
||||
REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE);
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int devdidvid;
|
||||
unsigned int didvid;
|
||||
unsigned int vendorId, deviceId;
|
||||
|
||||
vendorId = ids->vendor;
|
||||
deviceId = ids->device;
|
||||
didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) |
|
||||
(vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK);
|
||||
|
||||
for (i = devNo + 1; i < nDevices; i++) {
|
||||
|
||||
pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID,
|
||||
&devdidvid);
|
||||
|
||||
if (devdidvid == didvid) {
|
||||
return devices[i].device;
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
pci_register_hose(hose);
|
||||
hose->last_busno = pci_hose_scan(hose);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user