leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

spi: zynq_qspi: Fix to configure CPOL, CPHA mask

Browse Source 
priv->mode is initialized when .set_speed triggers
with mode value, so checking mode for configuring
CPOL, CPHA using priv->mode is invalid hence use
mode from .set_speed argument, and at the end
priv->mode will initialized with mode.

This patch also replaces formatting string to use
speed instead of mode in .set_speed ops.

Signed-off-by: Jagan Teki <jteki@openedev.com>
This commit is contained in:
Jagan Teki 2015-09-08 01:39:44 +05:30
parent 232a8e4ecc
commit 2775e91835
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/spi/zynq_qspi.c
View File

@ -569,7 +569,8 @@ static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
writel(confr, &regs->cr);
priv->freq = speed;
debug("zynq_spi_set_speed: regs=%p, mode=%d\n", priv->regs, priv->freq);
debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
priv->regs, priv->freq);
return 0;
}
@ -584,9 +585,9 @@ static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
confr = readl(&regs->cr);
confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
if (priv->mode & SPI_CPHA)
if (mode & SPI_CPHA)
confr |= ZYNQ_QSPI_CR_CPHA_MASK;
if (priv->mode & SPI_CPOL)
if (mode & SPI_CPOL)
confr |= ZYNQ_QSPI_CR_CPOL_MASK;
writel(confr, &regs->cr);