arm: rmobile: silk: Add support SDHI
This adds GPIO configuration and initialization function of SDHI on Silk board Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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@ -20,6 +20,7 @@
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/sh_sdhi.h>
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#include <netdev.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <i2c.h>
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@ -47,6 +48,10 @@ void s_init(void)
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#define ETHER_MSTP813 (1 << 13)
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#define ETHER_MSTP813 (1 << 13)
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#define IIC1_MSTP323 (1 << 23)
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#define IIC1_MSTP323 (1 << 23)
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#define MMC0_MSTP315 (1 << 15)
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#define MMC0_MSTP315 (1 << 15)
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#define SDHI1_MSTP312 (1 << 12)
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#define SD1CKCR 0xE6150078
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#define SD1_97500KHZ 0x7
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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@ -66,6 +71,16 @@ int board_early_init_f(void)
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/* MMC */
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/* MMC */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
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#endif
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#endif
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#ifdef CONFIG_SH_SDHI
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/* SDHI1 */
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312);
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/*
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* Set SD1 to the 97.5MHz
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*/
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writel(SD1_97500KHZ, SD1CKCR);
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#endif
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return 0;
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return 0;
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}
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}
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@ -139,7 +154,7 @@ int board_eth_init(bd_t *bis)
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int board_mmc_init(bd_t *bis)
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int board_mmc_init(bd_t *bis)
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{
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{
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int ret = 0;
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int ret = -ENODEV;
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#ifdef CONFIG_SH_MMCIF
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#ifdef CONFIG_SH_MMCIF
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/* MMC0 */
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/* MMC0 */
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@ -148,6 +163,24 @@ int board_mmc_init(bd_t *bis)
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ret = mmcif_mmc_init();
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ret = mmcif_mmc_init();
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#endif
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#endif
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#ifdef CONFIG_SH_SDHI
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gpio_request(GPIO_FN_SD1_DATA0, NULL);
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gpio_request(GPIO_FN_SD1_DATA1, NULL);
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gpio_request(GPIO_FN_SD1_DATA2, NULL);
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gpio_request(GPIO_FN_SD1_DATA3, NULL);
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gpio_request(GPIO_FN_SD1_CLK, NULL);
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gpio_request(GPIO_FN_SD1_CMD, NULL);
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gpio_request(GPIO_FN_SD1_CD, NULL);
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/* SDHI 1 */
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gpio_request(GPIO_GP_4_26, NULL);
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gpio_request(GPIO_GP_4_29, NULL);
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gpio_direction_output(GPIO_GP_4_26, 1);
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gpio_direction_output(GPIO_GP_4_29, 1);
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ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
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#endif
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return ret;
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return ret;
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}
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}
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@ -3,3 +3,4 @@ CONFIG_RMOBILE=y
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CONFIG_TARGET_SILK=y
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CONFIG_TARGET_SILK=y
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CONFIG_DM=y
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CONFIG_DM=y
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CONFIG_DM_SERIAL=y
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CONFIG_DM_SERIAL=y
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CONFIG_SH_SDHI=y
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@ -101,6 +101,9 @@
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#define CONFIG_SH_MMCIF_ADDR 0xee200000
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#define CONFIG_SH_MMCIF_ADDR 0xee200000
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#define CONFIG_SH_MMCIF_CLK 48000000
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#define CONFIG_SH_MMCIF_CLK 48000000
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/* SDHI */
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#define CONFIG_SH_SDHI_FREQ 97500000
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/* Module stop status bits */
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/* Module stop status bits */
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/* INTC-RT */
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/* INTC-RT */
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#define CONFIG_SMSTP0_ENA 0x00400000
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#define CONFIG_SMSTP0_ENA 0x00400000
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