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arm: samsung: Migrate a number of symbols to Kconfig

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- In a number of cases, use CONFIG_ARCH_EXYNOS[45] rather than
  CONFIG_EXYNOS[45]
- In other cases, test for CONFIG_ARCH_EXYNOS or CONFIG_ARCH_S5PC1XX
- Migrate specific SoC CONFIG values to Kconfig
- Use CONFIG_TARGET_x rather than CONFIG_x
- Migrate other CONFIG_EXYNOS_x symbols to Kconfig
- Reference CONFIG_EXYNOS_RELOCATE_CODE_BASE directly as EXYNOS_RELOCATE_CODE_BASE
- Rename CONFIG_S5P_PA_SYSRAM to CONFIG_SMP_PEN_ADDR to match the rest
  of U-Boot usage.

Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-06-10 22:59:33 -04:00
parent 1e03e03d03
commit 24ec3dea4b
36 changed files with 74 additions and 99 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/Kconfig
View File

@ -609,6 +609,9 @@ config ARM64_SUPPORT_AARCH32
help
This ARM64 system supports AArch32 execution state.
config S5P
def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
choice
prompt "Target select"
default TARGET_HIKEY

8
arch/arm/dts/Makefile
View File

@ -5,9 +5,9 @@ dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb
dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb
dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb
dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb
dtb-$(CONFIG_ARCH_EXYNOS4) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-universal_c210.dtb \
exynos4210-trats.dtb \
@ -19,7 +19,7 @@ dtb-$(CONFIG_TARGET_HIKEY960) += hi3660-hikey960.dtb
dtb-$(CONFIG_TARGET_POPLAR) += hi3798cv200-poplar.dtb
dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
dtb-$(CONFIG_ARCH_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
exynos5250-spring.dtb \
exynos5250-smdk5250.dtb \

5
arch/arm/include/asm/spl.h
View File

@ -6,9 +6,8 @@
#ifndef _ASM_SPL_H_
#define _ASM_SPL_H_
#if defined(CONFIG_ARCH_OMAP2PLUS) \
|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
|| defined(CONFIG_EXYNOS4210) || defined(CONFIG_ARCH_K3)
#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) || \
defined(CONFIG_ARCH_K3) || defined(CONFIG_ARCH_OMAP2PLUS)
/* Platform-specific defines */
#include <asm/arch/spl.h>

39
arch/arm/mach-exynos/Kconfig
View File

@ -54,11 +54,15 @@ endchoice
if ARCH_EXYNOS4
config EXYNOS4210
bool
choice
prompt "EXYNOS4 board select"
config TARGET_SMDKV310
bool "Exynos4210 SMDKV310 board"
select EXYNOS4210
select OF_CONTROL
select SUPPORT_SPL
@ -70,6 +74,7 @@ config TARGET_S5PC210_UNIVERSAL
config TARGET_ORIGEN
bool "Exynos4412 Origen board"
select EXYNOS4210
select SUPPORT_SPL
config TARGET_TRATS2
@ -83,6 +88,15 @@ endif
if ARCH_EXYNOS5
config EXYNOS5250
bool
config EXYNOS5420
bool
config EXYNOS5_DT
bool
config SPL_GPIO
default y
@ -97,6 +111,8 @@ choice
config TARGET_ODROID_XU3
bool "Exynos5422 Odroid board"
select EXYNOS5_DT
select EXYNOS5420
select OF_CONTROL
config TARGET_ARNDALE
@ -105,36 +121,49 @@ config TARGET_ARNDALE
select ARM_ERRATA_774769
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select EXYNOS5250
select OF_CONTROL
select SUPPORT_SPL
config TARGET_SMDK5250
bool "SMDK5250 board"
select EXYNOS5_DT
select EXYNOS5250
select OF_CONTROL
select SUPPORT_SPL
config TARGET_SNOW
bool "Snow board"
select EXYNOS5_DT
select EXYNOS5250
select OF_CONTROL
select SUPPORT_SPL
config TARGET_SPRING
bool "Spring board"
select EXYNOS5_DT
select EXYNOS5250
select OF_CONTROL
select SUPPORT_SPL
config TARGET_SMDK5420
bool "SMDK5420 board"
select EXYNOS5_DT
select EXYNOS5420
select OF_CONTROL
select SUPPORT_SPL
config TARGET_PEACH_PI
bool "Peach Pi board"
select EXYNOS5_DT
select EXYNOS5420
select OF_CONTROL
select SUPPORT_SPL
config TARGET_PEACH_PIT
bool "Peach Pit board"
select EXYNOS5_DT
select EXYNOS5420
select OF_CONTROL
select SUPPORT_SPL
@ -189,6 +218,16 @@ endif
config SYS_SOC
default "exynos"
config EXYNOS_ACE_SHA
bool "Advanced Crypto Engine SHA support"
depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && (LIB_HW_RAND || SHA_HW_ACCEL)
default y if ARCH_EXYNOS5
config EXYNOS_TMU
bool "Exynos5 thermal management unit support"
depends on ARCH_EXYNOS5
default y
source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
source "board/samsung/universal_c210/Kconfig"

4
arch/arm/mach-exynos/Makefile
View File

@ -10,8 +10,8 @@ obj-$(CONFIG_ARM64) += mmu-arm64.o
obj-$(CONFIG_EXYNOS5420) += sec_boot.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
obj-y += spl_boot.o tzpc.o
obj-y += lowlevel_init.o

2
arch/arm/mach-exynos/dmc_init_exynos4.c
View File

@ -175,7 +175,7 @@ void mem_ctrl_init(int reset)
* 0: full_sync
*/
writel(1, ASYNC_CONFIG);
#ifdef CONFIG_ORIGEN
#ifdef CONFIG_TARGET_ORIGEN
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
APB_SFR_INTERLEAVE_CONF_OFFSET);

4
arch/arm/mach-exynos/exynos4_setup.h
View File

@ -420,7 +420,7 @@ struct mem_timings {
#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828
#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830
#ifdef CONFIG_ORIGEN
#ifdef CONFIG_TARGET_ORIGEN
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001
@ -542,7 +542,7 @@ struct mem_timings {
#define CONTROL2_VAL 0x00000000
#ifdef CONFIG_ORIGEN
#ifdef CONFIG_TARGET_ORIGEN
#define TIMINGREF_VAL 0x000000BB
#define TIMINGROW_VAL 0x4046654f
#define TIMINGDATA_VAL 0x46400506

8
arch/arm/mach-exynos/lowlevel_init.c
View File

@ -49,6 +49,10 @@ enum {
};
#ifdef CONFIG_EXYNOS5420
/* Address for relocating helper code (Last 4 KB of IRAM) */
#define EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000)
/*
* Power up secondary CPUs.
*/
@ -56,7 +60,7 @@ static void secondary_cpu_start(void)
{
v7_enable_smp(EXYNOS5420_INFORM_BASE);
svc32_mode_en();
branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
branch_bx(EXYNOS_RELOCATE_CODE_BASE);
}
/*
@ -153,7 +157,7 @@ static void power_down_core(void)
static void secondary_cores_configure(void)
{
/* Clear secondary boot iRAM base */
writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C));
/* set lowpower flag and address */
writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);

2
arch/arm/mach-exynos/sec_boot.S
View File

@ -21,7 +21,7 @@ relocate_wait_code:
.ltorg
/*
* Secondary core waits here until Primary wake it up.
* Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE.
* Below code is copied to (CONFIG_IRAM_TOP - 0x1000)
* This is a workaround code which is supposed to act as a
* substitute/supplement to the iROM code.
*

4
board/samsung/arndale/arndale.c
View File

@ -112,10 +112,10 @@ int checkboard(void)
}
#endif
#ifdef CONFIG_S5P_PA_SYSRAM
#ifdef CONFIG_SMP_PEN_ADDR
void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
writel(addr, CONFIG_S5P_PA_SYSRAM);
writel(addr, CONFIG_SMP_PEN_ADDR);
/* make sure this write is really executed */
__asm__ volatile ("dsb\n");

1
configs/odroid-xu3_defconfig
View File

@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ARCH_EXYNOS5=y
# CONFIG_EXYNOS_TMU is not set
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x310000

1
configs/odroid_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_LEN=0x5004000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_ODROID=y
CONFIG_EXYNOS_ACE_SHA=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x140000

1
configs/trats2_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_TRATS2=y
CONFIG_EXYNOS_ACE_SHA=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"

1
configs/trats_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_LEN=0x5001000
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_TRATS=y
CONFIG_EXYNOS_ACE_SHA=y
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x7000
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"

2
drivers/i2c/exynos_hs_i2c.c
View File

@ -147,7 +147,7 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
unsigned int i = 0, utemp0 = 0, utemp1 = 0;
unsigned int t_ftl_cycle;
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
clkin = get_i2c_clk();
#else
clkin = get_PCLK();

4
drivers/i2c/s3c24x0_i2c.c
View File

@ -8,7 +8,7 @@
#include <errno.h>
#include <dm.h>
#include <fdtdec.h>
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
#include <log.h>
#include <asm/arch/clk.h>
#include <asm/arch/cpu.h>
@ -53,7 +53,7 @@ static void read_write_byte(struct s3c24x0_i2c *i2c)
static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
{
ulong freq, pres = 16, div;
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
freq = get_i2c_clk();
#else
freq = get_PCLK();

6
include/configs/arndale.h
View File

@ -14,13 +14,9 @@
#include "exynos5250-common.h"
#include <configs/exynos5-common.h>
/* MMC SPL */
#define CONFIG_EXYNOS_SPL
/* Miscellaneous configurable options */
#define CONFIG_S5P_PA_SYSRAM 0x02020000
#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM
#define CONFIG_SMP_PEN_ADDR 0x02020000
/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000

2
include/configs/espresso7420.h
View File

@ -10,8 +10,6 @@
#include <configs/exynos7420-common.h>
#define CONFIG_ESPRESSO7420
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* DRAM Memory Banks */

4
include/configs/exynos-common.h
View File

@ -8,10 +8,6 @@
#ifndef __EXYNOS_COMMON_H
#define __EXYNOS_COMMON_H
/* High Level Configuration Options */
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
#define CONFIG_S5P /* S5P Family */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <linux/sizes.h>
#include <linux/stringify.h>

2
include/configs/exynos4-common.h
View File

@ -8,8 +8,6 @@
#ifndef __CONFIG_EXYNOS4_COMMON_H
#define __CONFIG_EXYNOS4_COMMON_H
#define CONFIG_EXYNOS4 /* Exynos4 Family */
#include "exynos-common.h"
/* SD/MMC configuration */

10
include/configs/exynos5-common.h
View File

@ -8,15 +8,8 @@
#ifndef __CONFIG_EXYNOS5_COMMON_H
#define __CONFIG_EXYNOS5_COMMON_H
#define CONFIG_EXYNOS5 /* Exynos5 Family */
#include "exynos-common.h"
#define CONFIG_EXYNOS_SPL
/* Enable ACE acceleration for SHA1 and SHA256 */
#define CONFIG_EXYNOS_ACE_SHA
/* Power Down Modes */
#define S5P_CHECK_SLEEP 0x00000BAD
#define S5P_CHECK_DIDLE 0xBAD00000
@ -31,9 +24,6 @@
/* select serial console configuration */
#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
/* Thermal Management Unit */
#define CONFIG_EXYNOS_TMU
/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x02020030

2
include/configs/exynos5-dt-common.h
View File

@ -15,8 +15,6 @@
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#define CONFIG_EXYNOS5_DT
#define CONFIG_SYS_SPI_BASE 0x12D30000
#define FLASH_SIZE (4 << 20)
#define CONFIG_SPI_BOOTING

2
include/configs/exynos5250-common.h
View File

@ -9,8 +9,6 @@
#ifndef __CONFIG_5250_H
#define __CONFIG_5250_H
#define CONFIG_EXYNOS5250
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* USB */

7
include/configs/exynos5420-common.h
View File

@ -8,19 +8,12 @@
#ifndef __CONFIG_EXYNOS5420_H
#define __CONFIG_EXYNOS5420_H
#define CONFIG_EXYNOS5420
#define CONFIG_EXYNOS5_DT
#define CONFIG_VAR_SIZE_SPL
#define CONFIG_IRAM_TOP 0x02074000
#define CONFIG_PHY_IRAM_BASE 0x02020000
/* Address for relocating helper code (Last 4 KB of IRAM) */
#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000)
/*
* Low Power settings
*/

4
include/configs/exynos7420-common.h
View File

@ -8,10 +8,6 @@
#ifndef __CONFIG_EXYNOS7420_COMMON_H
#define __CONFIG_EXYNOS7420_COMMON_H
/* High Level Configuration Options */
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
#define CONFIG_S5P
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <linux/sizes.h>

4
include/configs/exynos78x0-common.h
View File

@ -11,10 +11,6 @@
#ifndef __CONFIG_EXYNOS78x0_COMMON_H
#define __CONFIG_EXYNOS78x0_COMMON_H
/* High Level Configuration Options */
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
#define CONFIG_S5P
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <linux/sizes.h>

3
include/configs/odroid.h
View File

@ -146,9 +146,6 @@
/* GPT */
/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
/* USB */
#define CONFIG_USB_EHCI_EXYNOS

3
include/configs/odroid_xu3.h
View File

@ -31,9 +31,6 @@
#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */
#undef CONFIG_EXYNOS_TMU
#define CONFIG_DFU_ALT_SYSTEM \
"uImage fat 0 1;" \
"zImage fat 0 1;" \

4
include/configs/origen.h
View File

@ -10,10 +10,6 @@
#include <configs/exynos4-common.h>
/* High Level Configuration Options */
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
/* ORIGEN has 4 bank of DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE

5
include/configs/s5p_goni.h
View File

@ -10,11 +10,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5P 1 /* which is in a S5P Family */
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */

8
include/configs/smdkc100.h
View File

@ -11,14 +11,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5P 1 /* which is in a S5P Family */
#define CONFIG_S5PC100 1 /* which is in a S5PC100 */
#include <asm/arch/cpu.h> /* get chip and board defs */
/* input clock of PLL: SMDKC100 has 12MHz input clock */

2
include/configs/smdkv310.h
View File

@ -13,8 +13,6 @@
#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
/* High Level Configuration Options */
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* Handling Sleep Mode*/

5
include/configs/trats.h
View File

@ -11,8 +11,6 @@
#include <configs/exynos4-common.h>
#define CONFIG_TRATS
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000
@ -128,9 +126,6 @@
/* GPT */
/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
/* Common misc for Samsung */
#define CONFIG_MISC_COMMON

3
include/configs/trats2.h
View File

@ -116,9 +116,6 @@
/* GPT */
/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
/* Common misc for Samsung */
#define CONFIG_MISC_COMMON

2
include/power/fg_battery_cell_params.h
View File

@ -7,7 +7,7 @@
#ifndef __FG_BATTERY_CELL_PARAMS_H_
#define __FG_BATTERY_CELL_PARAMS_H_
#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TRATS)
#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TARGET_TRATS)
/* Cell characteristics - Exynos4 TRATS development board */
/* Shall be written to addr 0x80h */

6
scripts/Makefile.spl
View File

@ -253,7 +253,7 @@ endif
INPUTS-y += $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).sym
ifdef CONFIG_SAMSUNG
ifneq ($(CONFIG_ARCH_EXYNOS)$(CONFIG_ARCH_S5PC1XX),)
INPUTS-y += $(obj)/$(BOARD)-spl.bin
endif
@ -367,8 +367,8 @@ $(platdata-hdr) $(u-boot-spl-platdata_c) &: $(obj)/$(SPL_BIN).dtb
@rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata)
$(call if_changed,dtoc)
ifdef CONFIG_SAMSUNG
ifdef CONFIG_VAR_SIZE_SPL
ifneq ($(CONFIG_ARCH_EXYNOS)$(CONFIG_ARCH_S5PC1XX),)
ifeq ($(CONFIG_EXYNOS5420),y)
VAR_SIZE_PARAM = --vs
else
VAR_SIZE_PARAM =