mmc: at91: add multi block read/write support.
Since the at91sam9263, the mmc hardware support multi blocks read/write. So this driver enable it. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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@ -87,6 +87,11 @@ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
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| MMCI_BF(BLKLEN, blklen)
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| MMCI_BIT(RDPROOF)
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| MMCI_BIT(WRPROOF)), &mci->mr);
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/*
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* On some new platforms BLKLEN in mci->mr is ignored.
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* Should use the BLKLEN in the block register.
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*/
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writel(MMCI_BF(BLKLEN, blklen), &mci->blkr);
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initialized = 1;
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}
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@ -183,6 +188,12 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
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/* Figure out the transfer arguments */
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cmdr = mci_encode_cmd(cmd, data, &error_flags);
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/* For multi blocks read/write, set the block register */
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if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
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|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
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writel(data->blocks | MMCI_BF(BLKLEN, mmc->read_bl_len),
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&mci->blkr);
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/* Send the command */
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writel(cmd->cmdarg, &mci->argr);
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writel(cmdr, &mci->cmdr);
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@ -38,7 +38,7 @@ typedef struct atmel_mci {
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u32 sdcr; /* 0x0c */
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u32 argr; /* 0x10 */
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u32 cmdr; /* 0x14 */
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u32 _18; /* 0x18 */
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u32 blkr; /* 0x18 */
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u32 _1c; /* 0x1c */
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u32 rspr; /* 0x20 */
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u32 rspr1; /* 0x24 */
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@ -118,6 +118,11 @@ typedef struct atmel_mci {
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#define MMCI_TRTYP_OFFSET 19
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#define MMCI_TRTYP_SIZE 2
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/* Bitfields in BLKR */
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/* MMCI_BLKLEN_OFFSET/SIZE already defined in MR */
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#define MMCI_BCNT_OFFSET 0
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#define MMCI_BCNT_SIZE 16
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/* Bitfields in RSPRx */
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#define MMCI_RSP_OFFSET 0
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#define MMCI_RSP_SIZE 32
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