Tegra30: Add AVP (arm720t) files
This provides SPL support for T30 boards - AVP early init, plus CPU (A9) init/jump to main U-Boot. Some changes were made to Tegra20 cpu.c to move common routines into tegra-common/cpu.c and reduce code duplication. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
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dc89ad1438
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@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)libtegra-common.o
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COBJS-$(CONFIG_SPL_BUILD) += spl.o
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COBJS-y += cpu.o
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SRCS := $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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335
arch/arm/cpu/arm720t/tegra-common/cpu.c
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335
arch/arm/cpu/arm720t/tegra-common/cpu.c
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@ -0,0 +1,335 @@
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/*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gp_padctrl.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/scu.h>
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#include "cpu.h"
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enum tegra_family_t {
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TEGRA_FAMILY_T2x,
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TEGRA_FAMILY_T3x,
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};
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enum tegra_family_t get_family(void)
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{
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u32 reg, chip_id;
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reg = readl(NV_PA_APB_MISC_BASE + GP_HIDREV);
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chip_id = reg >> 8;
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chip_id &= 0xff;
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debug(" tegra_get_family: chip_id = %x\n", chip_id);
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if (chip_id == 0x30)
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return TEGRA_FAMILY_T3x;
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else
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return TEGRA_FAMILY_T2x;
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}
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int get_num_cpus(void)
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{
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return get_family() == TEGRA_FAMILY_T3x ? 4 : 2;
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}
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/*
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* Timing tables for each SOC for all four oscillator options.
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*/
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struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
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/* T20: 1 GHz */
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{{ 1000, 13, 0, 12}, /* OSC 13M */
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{ 625, 12, 0, 8}, /* OSC 19.2M */
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{ 1000, 12, 0, 12}, /* OSC 12M */
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{ 1000, 26, 0, 12}, /* OSC 26M */
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},
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/* T25: 1.2 GHz */
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{{ 923, 10, 0, 12},
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{ 750, 12, 0, 8},
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{ 600, 6, 0, 12},
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{ 600, 13, 0, 12},
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},
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/* T30: 1.4 GHz */
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{{ 862, 8, 0, 8},
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{ 583, 8, 0, 4},
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{ 700, 6, 0, 8},
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{ 700, 13, 0, 8},
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},
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/* TEGRA_SOC2_SLOW: 312 MHz */
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{{ 312, 13, 0, 12}, /* OSC 13M */
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{ 260, 16, 0, 8}, /* OSC 19.2M */
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{ 312, 12, 0, 12}, /* OSC 12M */
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{ 312, 26, 0, 12}, /* OSC 26M */
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},
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};
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void adjust_pllp_out_freqs(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
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u32 reg;
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/* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
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reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
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reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
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| (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
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writel(reg, &pll->pll_out[0]);
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reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
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reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
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| (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
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writel(reg, &pll->pll_out[1]);
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}
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int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
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u32 divp, u32 cpcon)
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{
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u32 reg;
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/* If PLLX is already enabled, just return */
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if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
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debug("pllx_set_rate: PLLX already enabled, returning\n");
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return 0;
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}
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debug(" pllx_set_rate entry\n");
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/* Set BYPASS, m, n and p to PLLX_BASE */
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reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
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reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
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writel(reg, &pll->pll_base);
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/* Set cpcon to PLLX_MISC */
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reg = (cpcon << PLL_CPCON_SHIFT);
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/* Set dccon to PLLX_MISC if freq > 600MHz */
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if (divn > 600)
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reg |= (1 << PLL_DCCON_SHIFT);
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writel(reg, &pll->pll_misc);
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/* Enable PLLX */
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reg = readl(&pll->pll_base);
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reg |= PLL_ENABLE_MASK;
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/* Disable BYPASS */
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reg &= ~PLL_BYPASS_MASK;
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writel(reg, &pll->pll_base);
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/* Set lock_enable to PLLX_MISC */
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reg = readl(&pll->pll_misc);
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reg |= PLL_LOCK_ENABLE_MASK;
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writel(reg, &pll->pll_misc);
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return 0;
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}
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void init_pllx(void)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
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int chip_type;
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enum clock_osc_freq osc;
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struct clk_pll_table *sel;
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debug("init_pllx entry\n");
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/* get chip type */
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chip_type = tegra_get_chip_type();
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debug(" init_pllx: chip_type = %d\n", chip_type);
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/* get osc freq */
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osc = clock_get_osc_freq();
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debug(" init_pllx: osc = %d\n", osc);
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/* set pllx */
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sel = &tegra_pll_x_table[chip_type][osc];
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pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
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/* adjust PLLP_out1-4 on T30 */
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if (chip_type == TEGRA_SOC_T30) {
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debug(" init_pllx: adjusting PLLP out freqs\n");
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adjust_pllp_out_freqs();
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}
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}
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void enable_cpu_clock(int enable)
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{
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struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 clk;
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/*
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* NOTE:
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* Regardless of whether the request is to enable or disable the CPU
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* clock, every processor in the CPU complex except the master (CPU 0)
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* will have it's clock stopped because the AVP only talks to the
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* master.
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*/
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if (enable) {
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/* Initialize PLLX */
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init_pllx();
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/* Wait until all clocks are stable */
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udelay(PLL_STABILIZATION_DELAY);
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writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
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writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
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}
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/*
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* Read the register containing the individual CPU clock enables and
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* always stop the clocks to CPUs > 0.
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*/
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clk = readl(&clkrst->crc_clk_cpu_cmplx);
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clk |= 1 << CPU1_CLK_STP_SHIFT;
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#if defined(CONFIG_TEGRA30)
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clk |= 1 << CPU2_CLK_STP_SHIFT;
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clk |= 1 << CPU3_CLK_STP_SHIFT;
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#endif
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/* Stop/Unstop the CPU clock */
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clk &= ~CPU0_CLK_STP_MASK;
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clk |= !enable << CPU0_CLK_STP_SHIFT;
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writel(clk, &clkrst->crc_clk_cpu_cmplx);
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clock_enable(PERIPH_ID_CPU);
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}
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static int is_cpu_powered(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
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}
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static void remove_cpu_io_clamps(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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/* Remove the clamps on the CPU I/O signals */
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reg = readl(&pmc->pmc_remove_clamping);
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reg |= CPU_CLMP;
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writel(reg, &pmc->pmc_remove_clamping);
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/* Give I/O signals time to stabilize */
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udelay(IO_STABILIZATION_DELAY);
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}
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void powerup_cpu(void)
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{
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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int timeout = IO_STABILIZATION_DELAY;
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if (!is_cpu_powered()) {
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/* Toggle the CPU power state (OFF -> ON) */
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reg = readl(&pmc->pmc_pwrgate_toggle);
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reg &= PARTID_CP;
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reg |= START_CP;
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writel(reg, &pmc->pmc_pwrgate_toggle);
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/* Wait for the power to come up */
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while (!is_cpu_powered()) {
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if (timeout-- == 0)
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printf("CPU failed to power up!\n");
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else
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udelay(10);
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}
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/*
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* Remove the I/O clamps from CPU power partition.
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* Recommended only on a Warm boot, if the CPU partition gets
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* power gated. Shouldn't cause any harm when called after a
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* cold boot according to HW, probably just redundant.
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*/
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remove_cpu_io_clamps();
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}
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}
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void reset_A9_cpu(int reset)
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{
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/*
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* NOTE: Regardless of whether the request is to hold the CPU in reset
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* or take it out of reset, every processor in the CPU complex
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* except the master (CPU 0) will be held in reset because the
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* AVP only talks to the master. The AVP does not know that there
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* are multiple processors in the CPU complex.
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*/
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int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
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int num_cpus = get_num_cpus();
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int cpu;
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debug("reset_a9_cpu entry\n");
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/* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
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for (cpu = 1; cpu < num_cpus; cpu++)
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reset_cmplx_set_enable(cpu, mask, 1);
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reset_cmplx_set_enable(0, mask, reset);
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/* Enable/Disable master CPU reset */
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reset_set_enable(PERIPH_ID_CPU, reset);
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}
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void clock_enable_coresight(int enable)
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{
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u32 rst, src;
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debug("clock_enable_coresight entry\n");
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clock_set_enable(PERIPH_ID_CORESIGHT, enable);
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reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
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if (enable) {
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/*
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* Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
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* 1.5, giving an effective frequency of 144MHz.
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* Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
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* (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
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*
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* Clock divider request for 204MHz would setup CSITE clock as
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* 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
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*/
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if (tegra_get_chip_type() == TEGRA_SOC_T30)
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src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
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else
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src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
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clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
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/* Unlock the CPU CoreSight interfaces */
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rst = CORESIGHT_UNLOCK;
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writel(rst, CSITE_CPU_DBG0_LAR);
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writel(rst, CSITE_CPU_DBG1_LAR);
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#if defined(CONFIG_TEGRA30)
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writel(rst, CSITE_CPU_DBG2_LAR);
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writel(rst, CSITE_CPU_DBG3_LAR);
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#endif
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}
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}
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void halt_avp(void)
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{
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for (;;) {
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writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
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| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
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FLOW_CTLR_HALT_COP_EVENTS);
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}
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}
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@ -26,7 +26,11 @@
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#define PLL_STABILIZATION_DELAY (300)
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#define IO_STABILIZATION_DELAY (1000)
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#if defined(CONFIG_TEGRA30)
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#define NVBL_PLLP_KHZ (408000)
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#else /* Tegra20 */
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#define NVBL_PLLP_KHZ (216000)
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#endif
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#define PLLX_ENABLED (1 << 30)
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#define CCLK_BURST_POLICY 0x20008888
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@ -44,50 +48,11 @@
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#define CORESIGHT_UNLOCK 0xC5ACCE55;
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/* AP20-Specific Base Addresses */
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/* AP20 Base physical address of SDRAM. */
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#define AP20_BASE_PA_SDRAM 0x00000000
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/* AP20 Base physical address of internal SRAM. */
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#define AP20_BASE_PA_SRAM 0x40000000
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/* AP20 Size of internal SRAM (256KB). */
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#define AP20_BASE_PA_SRAM_SIZE 0x00040000
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/* AP20 Base physical address of flash. */
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#define AP20_BASE_PA_NOR_FLASH 0xD0000000
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/* AP20 Base physical address of boot information table. */
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#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
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/*
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* Super-temporary stacks for EXTREMELY early startup. The values chosen for
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* these addresses must be valid on ALL SOCs because this value is used before
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* we are able to differentiate between the SOC types.
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*
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* NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
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* stack is placed below the AVP stack. Once the CPU stack has been moved,
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* the AVP is free to use the IRAM the CPU stack previously occupied if
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* it should need to do so.
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*
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* NOTE: In multi-processor CPU complex configurations, each processor will have
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* its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
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* limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
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* stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
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* CPU.
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*/
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/* Common AVP early boot stack limit */
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#define AVP_EARLY_BOOT_STACK_LIMIT \
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(AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
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/* Common AVP early boot stack size */
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#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
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/* Common CPU early boot stack limit */
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#define CPU_EARLY_BOOT_STACK_LIMIT \
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(AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
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/* Common CPU early boot stack size */
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#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
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#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
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#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
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#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
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#define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
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#define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
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#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
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#define FLOW_MODE_STOP 2
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@ -95,6 +60,23 @@
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#define HALT_COP_EVENT_IRQ_1 (1 << 11)
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#define HALT_COP_EVENT_FIQ_1 (1 << 9)
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void start_cpu(u32 reset_vector);
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int ap20_cpu_is_cortexa9(void);
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#define FLOW_MODE_NONE 0
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#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
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struct clk_pll_table {
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u16 n;
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u16 m;
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u8 p;
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u8 cpcon;
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};
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void clock_enable_coresight(int enable);
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void enable_cpu_clock(int enable);
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void halt_avp(void) __attribute__ ((noreturn));
|
||||
void init_pllx(void);
|
||||
void powerup_cpu(void);
|
||||
void reset_A9_cpu(int reset);
|
||||
void start_cpu(u32 reset_vector);
|
||||
int tegra_get_chip_type(void);
|
||||
void adjust_pllp_out_freqs(void);
|
||||
|
@ -23,7 +23,6 @@
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include "cpu.h"
|
||||
#include <spl.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
@ -32,7 +31,7 @@
|
||||
#include <asm/arch/tegra.h>
|
||||
#include <asm/arch-tegra/board.h>
|
||||
#include <asm/arch/spl.h>
|
||||
|
||||
#include "cpu.h"
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
|
@ -1,160 +1,25 @@
|
||||
/*
|
||||
* (C) Copyright 2010-2011
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/tegra.h>
|
||||
#include <asm/arch-tegra/clk_rst.h>
|
||||
#include <asm/arch-tegra/pmc.h>
|
||||
#include <asm/arch-tegra/scu.h>
|
||||
#include "../tegra-common/cpu.h"
|
||||
|
||||
/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
|
||||
int ap20_cpu_is_cortexa9(void)
|
||||
{
|
||||
u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
|
||||
return id == (PG_UP_TAG_0_PID_CPU & 0xff);
|
||||
}
|
||||
|
||||
void init_pllx(void)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
|
||||
u32 reg;
|
||||
|
||||
/* If PLLX is already enabled, just return */
|
||||
if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
|
||||
return;
|
||||
|
||||
/* Set PLLX_MISC */
|
||||
writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
|
||||
|
||||
/* Use 12MHz clock here */
|
||||
reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
|
||||
reg |= 1000 << PLL_DIVN_SHIFT;
|
||||
writel(reg, &pll->pll_base);
|
||||
|
||||
reg |= PLL_ENABLE_MASK;
|
||||
writel(reg, &pll->pll_base);
|
||||
|
||||
reg &= ~PLL_BYPASS_MASK;
|
||||
writel(reg, &pll->pll_base);
|
||||
}
|
||||
|
||||
static void enable_cpu_clock(int enable)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
u32 clk;
|
||||
|
||||
/*
|
||||
* NOTE:
|
||||
* Regardless of whether the request is to enable or disable the CPU
|
||||
* clock, every processor in the CPU complex except the master (CPU 0)
|
||||
* will have it's clock stopped because the AVP only talks to the
|
||||
* master. The AVP does not know (nor does it need to know) that there
|
||||
* are multiple processors in the CPU complex.
|
||||
*/
|
||||
|
||||
if (enable) {
|
||||
/* Initialize PLLX */
|
||||
init_pllx();
|
||||
|
||||
/* Wait until all clocks are stable */
|
||||
udelay(PLL_STABILIZATION_DELAY);
|
||||
|
||||
writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
|
||||
writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read the register containing the individual CPU clock enables and
|
||||
* always stop the clock to CPU 1.
|
||||
*/
|
||||
clk = readl(&clkrst->crc_clk_cpu_cmplx);
|
||||
clk |= 1 << CPU1_CLK_STP_SHIFT;
|
||||
|
||||
/* Stop/Unstop the CPU clock */
|
||||
clk &= ~CPU0_CLK_STP_MASK;
|
||||
clk |= !enable << CPU0_CLK_STP_SHIFT;
|
||||
writel(clk, &clkrst->crc_clk_cpu_cmplx);
|
||||
|
||||
clock_enable(PERIPH_ID_CPU);
|
||||
}
|
||||
|
||||
static int is_cpu_powered(void)
|
||||
{
|
||||
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
|
||||
|
||||
return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
|
||||
}
|
||||
|
||||
static void remove_cpu_io_clamps(void)
|
||||
{
|
||||
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
|
||||
u32 reg;
|
||||
|
||||
/* Remove the clamps on the CPU I/O signals */
|
||||
reg = readl(&pmc->pmc_remove_clamping);
|
||||
reg |= CPU_CLMP;
|
||||
writel(reg, &pmc->pmc_remove_clamping);
|
||||
|
||||
/* Give I/O signals time to stabilize */
|
||||
udelay(IO_STABILIZATION_DELAY);
|
||||
}
|
||||
|
||||
static void powerup_cpu(void)
|
||||
{
|
||||
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
|
||||
u32 reg;
|
||||
int timeout = IO_STABILIZATION_DELAY;
|
||||
|
||||
if (!is_cpu_powered()) {
|
||||
/* Toggle the CPU power state (OFF -> ON) */
|
||||
reg = readl(&pmc->pmc_pwrgate_toggle);
|
||||
reg &= PARTID_CP;
|
||||
reg |= START_CP;
|
||||
writel(reg, &pmc->pmc_pwrgate_toggle);
|
||||
|
||||
/* Wait for the power to come up */
|
||||
while (!is_cpu_powered()) {
|
||||
if (timeout-- == 0)
|
||||
printf("CPU failed to power up!\n");
|
||||
else
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove the I/O clamps from CPU power partition.
|
||||
* Recommended only on a Warm boot, if the CPU partition gets
|
||||
* power gated. Shouldn't cause any harm when called after a
|
||||
* cold boot according to HW, probably just redundant.
|
||||
*/
|
||||
remove_cpu_io_clamps();
|
||||
}
|
||||
}
|
||||
|
||||
static void enable_cpu_power_rail(void)
|
||||
{
|
||||
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
|
||||
@ -173,49 +38,6 @@ static void enable_cpu_power_rail(void)
|
||||
udelay(3750);
|
||||
}
|
||||
|
||||
static void reset_A9_cpu(int reset)
|
||||
{
|
||||
/*
|
||||
* NOTE: Regardless of whether the request is to hold the CPU in reset
|
||||
* or take it out of reset, every processor in the CPU complex
|
||||
* except the master (CPU 0) will be held in reset because the
|
||||
* AVP only talks to the master. The AVP does not know that there
|
||||
* are multiple processors in the CPU complex.
|
||||
*/
|
||||
|
||||
/* Hold CPU 1 in reset, and CPU 0 if asked */
|
||||
reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
|
||||
reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
|
||||
reset);
|
||||
|
||||
/* Enable/Disable master CPU reset */
|
||||
reset_set_enable(PERIPH_ID_CPU, reset);
|
||||
}
|
||||
|
||||
static void clock_enable_coresight(int enable)
|
||||
{
|
||||
u32 rst, src;
|
||||
|
||||
clock_set_enable(PERIPH_ID_CORESIGHT, enable);
|
||||
reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
|
||||
|
||||
if (enable) {
|
||||
/*
|
||||
* Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
|
||||
* 1.5, giving an effective frequency of 144MHz.
|
||||
* Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
|
||||
* (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
|
||||
*/
|
||||
src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
|
||||
clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
|
||||
|
||||
/* Unlock the CPU CoreSight interfaces */
|
||||
rst = 0xC5ACCE55;
|
||||
writel(rst, CSITE_CPU_DBG0_LAR);
|
||||
writel(rst, CSITE_CPU_DBG1_LAR);
|
||||
}
|
||||
}
|
||||
|
||||
void start_cpu(u32 reset_vector)
|
||||
{
|
||||
/* Enable VDD_CPU */
|
||||
@ -246,13 +68,3 @@ void start_cpu(u32 reset_vector)
|
||||
/* Take the CPU out of reset */
|
||||
reset_A9_cpu(0);
|
||||
}
|
||||
|
||||
|
||||
void halt_avp(void)
|
||||
{
|
||||
for (;;) {
|
||||
writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
|
||||
| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
|
||||
FLOW_CTLR_HALT_COP_EVENTS);
|
||||
}
|
||||
}
|
||||
|
41
arch/arm/cpu/arm720t/tegra30/Makefile
Normal file
41
arch/arm/cpu/arm720t/tegra30/Makefile
Normal file
@ -0,0 +1,41 @@
|
||||
#
|
||||
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
#
|
||||
# (C) Copyright 2000-2008
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms and conditions of the GNU General Public License,
|
||||
# version 2, as published by the Free Software Foundation.
|
||||
#
|
||||
# This program is distributed in the hope it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
# more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
COBJS-y += cpu.o
|
||||
|
||||
SRCS := $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
|
||||
all: $(obj).depend $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
19
arch/arm/cpu/arm720t/tegra30/config.mk
Normal file
19
arch/arm/cpu/arm720t/tegra30/config.mk
Normal file
@ -0,0 +1,19 @@
|
||||
#
|
||||
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms and conditions of the GNU General Public License,
|
||||
# version 2, as published by the Free Software Foundation.
|
||||
#
|
||||
# This program is distributed in the hope it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
# more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
USE_PRIVATE_LIBGCC = yes
|
176
arch/arm/cpu/arm720t/tegra30/cpu.c
Normal file
176
arch/arm/cpu/arm720t/tegra30/cpu.c
Normal file
@ -0,0 +1,176 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/flow.h>
|
||||
#include <asm/arch/tegra.h>
|
||||
#include <asm/arch-tegra/clk_rst.h>
|
||||
#include <asm/arch-tegra/pmc.h>
|
||||
#include <asm/arch-tegra/tegra_i2c.h>
|
||||
#include "../tegra-common/cpu.h"
|
||||
|
||||
/* Tegra30-specific CPU init code */
|
||||
void tegra_i2c_ll_write_addr(uint addr, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(addr, ®->cmd_addr0);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
void tegra_i2c_ll_write_data(uint data, uint config)
|
||||
{
|
||||
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
|
||||
|
||||
writel(data, ®->cmd_data1);
|
||||
writel(config, ®->cnfg);
|
||||
}
|
||||
|
||||
#define TPS65911_I2C_ADDR 0x5A
|
||||
#define TPS65911_VDDCTRL_OP_REG 0x28
|
||||
#define TPS65911_VDDCTRL_SR_REG 0x27
|
||||
#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG)
|
||||
#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
|
||||
#define I2C_SEND_2_BYTES 0x0A02
|
||||
|
||||
static void enable_cpu_power_rail(void)
|
||||
{
|
||||
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
|
||||
u32 reg;
|
||||
|
||||
debug("enable_cpu_power_rail entry\n");
|
||||
reg = readl(&pmc->pmc_cntrl);
|
||||
reg |= CPUPWRREQ_OE;
|
||||
writel(reg, &pmc->pmc_cntrl);
|
||||
|
||||
/*
|
||||
* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
|
||||
* First set VDD to 1.4V, then enable the VDD regulator.
|
||||
*/
|
||||
tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
|
||||
tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
|
||||
udelay(1000);
|
||||
tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
|
||||
udelay(10 * 1000);
|
||||
}
|
||||
|
||||
/**
|
||||
* The T30 requires some special clock initialization, including setting up
|
||||
* the dvc i2c, turning on mselect and selecting the G CPU cluster
|
||||
*/
|
||||
void t30_init_clocks(void)
|
||||
{
|
||||
struct clk_rst_ctlr *clkrst =
|
||||
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
||||
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
|
||||
u32 val;
|
||||
|
||||
debug("t30_init_clocks entry\n");
|
||||
/* Set active CPU cluster to G */
|
||||
clrbits_le32(flow->cluster_control, 1 << 0);
|
||||
|
||||
/*
|
||||
* Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
|
||||
* at 108 MHz. This is glitch free as only the source is changed, no
|
||||
* special precaution needed.
|
||||
*/
|
||||
val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
|
||||
(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
|
||||
(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
|
||||
(SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
|
||||
(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
|
||||
writel(val, &clkrst->crc_sclk_brst_pol);
|
||||
|
||||
writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
|
||||
|
||||
val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
|
||||
(1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
|
||||
(0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
|
||||
(0 << CLK_SYS_RATE_APB_RATE_SHIFT);
|
||||
writel(val, &clkrst->crc_clk_sys_rate);
|
||||
|
||||
/* Put i2c, mselect in reset and enable clocks */
|
||||
reset_set_enable(PERIPH_ID_DVC_I2C, 1);
|
||||
clock_set_enable(PERIPH_ID_DVC_I2C, 1);
|
||||
reset_set_enable(PERIPH_ID_MSELECT, 1);
|
||||
clock_set_enable(PERIPH_ID_MSELECT, 1);
|
||||
|
||||
/* Switch MSELECT clock to PLLP (00) */
|
||||
clock_ll_set_source(PERIPH_ID_MSELECT, 0);
|
||||
|
||||
/*
|
||||
* Our high-level clock routines are not available prior to
|
||||
* relocation. We use the low-level functions which require a
|
||||
* hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
|
||||
*/
|
||||
clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
|
||||
|
||||
/*
|
||||
* Give clocks time to stabilize, then take i2c and mselect out of
|
||||
* reset
|
||||
*/
|
||||
udelay(1000);
|
||||
reset_set_enable(PERIPH_ID_DVC_I2C, 0);
|
||||
reset_set_enable(PERIPH_ID_MSELECT, 0);
|
||||
}
|
||||
|
||||
static void set_cpu_running(int run)
|
||||
{
|
||||
struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
|
||||
|
||||
debug("set_cpu_running entry, run = %d\n", run);
|
||||
writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
|
||||
}
|
||||
|
||||
void start_cpu(u32 reset_vector)
|
||||
{
|
||||
debug("start_cpu entry, reset_vector = %x\n", reset_vector);
|
||||
t30_init_clocks();
|
||||
|
||||
/* Enable VDD_CPU */
|
||||
enable_cpu_power_rail();
|
||||
|
||||
set_cpu_running(0);
|
||||
|
||||
/* Hold the CPUs in reset */
|
||||
reset_A9_cpu(1);
|
||||
|
||||
/* Disable the CPU clock */
|
||||
enable_cpu_clock(0);
|
||||
|
||||
/* Enable CoreSight */
|
||||
clock_enable_coresight(1);
|
||||
|
||||
/*
|
||||
* Set the entry point for CPU execution from reset,
|
||||
* if it's a non-zero value.
|
||||
*/
|
||||
if (reset_vector)
|
||||
writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
|
||||
|
||||
/* Enable the CPU clock */
|
||||
enable_cpu_clock(1);
|
||||
|
||||
/* If the CPU doesn't already have power, power it up */
|
||||
powerup_cpu();
|
||||
|
||||
/* Take the CPU out of reset */
|
||||
reset_A9_cpu(0);
|
||||
|
||||
set_cpu_running(1);
|
||||
}
|
Loading…
Reference in New Issue
Block a user