sh: Add support PCI of SuperH and SH7780
This patch add support PCI of SuperH base code and SH7780 specific code. Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Yusuke Goda
Nobuhiro Iwamatsu
parent
b55523efff
commit
1a2334a4eb
@ -29,7 +29,8 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(CPU).a
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START = start.o
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OBJS = cpu.o interrupts.o watchdog.o time.o cache.o
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OBJS = cpu.o interrupts.o watchdog.o time.o cache.o \
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pci-sh4.o pci-sh7780.o
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all: .depend $(START) $(LIB)
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81
cpu/sh4/pci-sh4.c
Normal file
81
cpu/sh4/pci-sh4.c
Normal file
@ -0,0 +1,81 @@
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/*
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* SH4 PCI Controller (PCIC) for U-Boot.
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* (C) Dustin McIntire (dustin@sensoria.com)
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* (C) 2007 Nobuhiro Iwamatsu
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* (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
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*
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* u-boot/cpu/sh4/pci-sh4.c
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_PCI) && \
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defined(CONFIG_SH4_PCI)
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <pci.h>
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int pci_sh4_init(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->region_count = 0;
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hose->last_busno = 0xff;
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/* PCI memory space */
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pci_set_region(hose->regions + 0,
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CONFIG_PCI_MEM_BUS,
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CONFIG_PCI_MEM_PHYS,
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CONFIG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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hose->region_count++;
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/* PCI IO space */
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pci_set_region(hose->regions + 1,
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CONFIG_PCI_IO_BUS,
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CONFIG_PCI_IO_PHYS,
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CONFIG_PCI_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count++;
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udelay(1000);
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pci_set_ops(hose,
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pci_hose_read_config_byte_via_dword,
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pci_hose_read_config_word_via_dword,
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pci_sh4_read_config_dword,
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pci_hose_write_config_byte_via_dword,
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pci_hose_write_config_word_via_dword,
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pci_sh4_write_config_dword);
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pci_register_hose(hose);
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udelay(1000);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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hose->last_busno = pci_hose_scan(hose);
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return 0;
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SH4_PCI) */
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111
cpu/sh4/pci-sh7780.c
Normal file
111
cpu/sh4/pci-sh7780.c
Normal file
@ -0,0 +1,111 @@
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/*
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* SH7780 PCI Controller (PCIC) for U-Boot.
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* (C) Dustin McIntire (dustin@sensoria.com)
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* (C) 2007 Nobuhiro Iwamatsu
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* (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_PCI) && defined(CONFIG_SH4_PCI) \
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&& defined(CONFIG_CPU_SH7780)
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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#define SH7780_VENDOR_ID 0x1912
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#define SH7780_DEVICE_ID 0x0002
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#define SH7780_PCICR_PREFIX 0xA5000000
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#define SH7780_PCICR_PFCS 0x00000800
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#define SH7780_PCICR_FTO 0x00000400
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#define SH7780_PCICR_PFE 0x00000200
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#define SH7780_PCICR_TBS 0x00000100
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#define SH7780_PCICR_ARBM 0x00000040
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#define SH7780_PCICR_IOCS 0x00000004
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#define SH7780_PCICR_PRST 0x00000002
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#define SH7780_PCICR_CFIN 0x00000001
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#define p4_in(addr) *((vu_long *)addr)
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#define p4_out(data,addr) *(vu_long *)(addr) = (data)
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#define p4_inw(addr) *((vu_short *)addr)
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#define p4_outw(data,addr) *(vu_short *)(addr) = (data)
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int pci_sh4_read_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 *value)
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{
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u32 par_data = 0x80000000 | dev;
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p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
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*value = p4_in(SH7780_PCIPDR);
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return 0;
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}
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int pci_sh4_write_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 value)
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{
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u32 par_data = 0x80000000 | dev;
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p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
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p4_out(value, SH7780_PCIPDR);
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return 0;
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}
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int pci_sh7780_init(struct pci_controller *hose)
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{
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p4_out(0x01, SH7780_PCIECR);
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if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
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&& p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID){
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printf("PCI: Unknown PCI host bridge.\n");
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return;
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}
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printf("PCI: SH7780 PCI host bridge found.\n");
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/* Toggle PCI reset pin */
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p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR);
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udelay(100000);
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p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
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p4_outw(0x0047, SH7780_PCICMD);
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p4_out(0x07F00001, SH7780_PCILSR0);
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p4_out(0x08000000, SH7780_PCILAR0);
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p4_out(0x00000000, SH7780_PCILSR1);
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p4_out(0, SH7780_PCILAR1);
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p4_out(0x08000000, SH7780_PCIMBAR0);
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p4_out(0x00000000, SH7780_PCIMBAR1);
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p4_out(0xFD000000, SH7780_PCIMBR0);
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p4_out(0x00FC0000, SH7780_PCIMBMR0);
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/* if use Operand Cache then enable PCICSCR Soonp bits. */
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p4_out(0x08000000, SH7780_PCICSAR0);
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p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */
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p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM
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| SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE),
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SH7780_PCICR);
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pci_sh4_init(hose);
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return 0;
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_CPU_SH7780) */
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@ -118,63 +118,63 @@
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#define DBK_2 0xFE800404
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/* PCI Controller */
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#define PCIECR 0xFE000008
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#define PCIVID 0xFE040000
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#define PCIDID 0xFE040002
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#define PCICMD 0xFE040004
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#define PCISTATUS 0xFE040006
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#define PCIRID 0xFE040008
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#define PCIPIF 0xFE040009
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#define PCISUB 0xFE04000A
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#define PCIBCC 0xFE04000B
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#define PCICLS 0xFE04000C
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#define PCILTM 0xFE04000D
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#define PCIHDR 0xFE04000E
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#define PCIBIST 0xFE04000F
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#define PCIIBAR 0xFE040010
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#define PCIMBAR0 0xFE040014
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#define PCIMBAR1 0xFE040018
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#define PCISVID 0xFE04002C
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#define PCISID 0xFE04002E
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#define PCICP 0xFE040034
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#define PCIINTLINE 0xFE04003C
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#define PCIINTPIN 0xFE04003D
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#define PCIMINGNT 0xFE04003E
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#define PCIMAXLAT 0xFE04003F
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#define PCICID 0xFE040040
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#define PCINIP 0xFE040041
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#define PCIPMC 0xFE040042
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#define PCIPMCSR 0xFE040044
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#define PCIPMCSRBSE 0xFE040046
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#define PCI_CDD 0xFE040047
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#define PCICR 0xFE040100
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#define PCILSR0 0xFE040104
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#define PCILSR1 0xFE040108
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#define PCILAR0 0xFE04010C
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#define PCILAR1 0xFE040110
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#define PCIIR 0xFE040114
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#define PCIIMR 0xFE040118
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#define PCIAIR 0xFE04011C
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#define PCICIR 0xFE040120
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#define PCIAINT 0xFE040130
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#define PCIAINTM 0xFE040134
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#define PCIBMIR 0xFE040138
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#define PCIPAR 0xFE0401C0
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#define PCIPINT 0xFE0401CC
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#define PCIPINTM 0xFE0401D0
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#define PCIMBR0 0xFE0401E0
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#define PCIMBMR0 0xFE0401E4
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#define PCIMBR1 0xFE0401E8
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#define PCIMBMR1 0xFE0401EC
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#define PCIMBR2 0xFE0401F0
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#define PCIMBMR2 0xFE0401F4
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#define PCIIOBR 0xFE0401F8
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#define PCIIOBMR 0xFE0401FC
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#define PCICSCR0 0xFE040210
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#define PCICSCR1 0xFE040214
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#define PCICSAR0 0xFE040218
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#define PCICSAR1 0xFE04021C
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#define PCIPDR 0xFE040220
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#define SH7780_PCIECR 0xFE000008
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#define SH7780_PCIVID 0xFE040000
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#define SH7780_PCIDID 0xFE040002
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#define SH7780_PCICMD 0xFE040004
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#define SH7780_PCISTATUS 0xFE040006
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#define SH7780_PCIRID 0xFE040008
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#define SH7780_PCIPIF 0xFE040009
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#define SH7780_PCISUB 0xFE04000A
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#define SH7780_PCIBCC 0xFE04000B
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#define SH7780_PCICLS 0xFE04000C
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#define SH7780_PCILTM 0xFE04000D
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#define SH7780_PCIHDR 0xFE04000E
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#define SH7780_PCIBIST 0xFE04000F
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#define SH7780_PCIIBAR 0xFE040010
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#define SH7780_PCIMBAR0 0xFE040014
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#define SH7780_PCIMBAR1 0xFE040018
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#define SH7780_PCISVID 0xFE04002C
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#define SH7780_PCISID 0xFE04002E
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#define SH7780_PCICP 0xFE040034
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#define SH7780_PCIINTLINE 0xFE04003C
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#define SH7780_PCIINTPIN 0xFE04003D
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#define SH7780_PCIMINGNT 0xFE04003E
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#define SH7780_PCIMAXLAT 0xFE04003F
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#define SH7780_PCICID 0xFE040040
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#define SH7780_PCINIP 0xFE040041
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#define SH7780_PCIPMC 0xFE040042
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#define SH7780_PCIPMCSR 0xFE040044
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#define SH7780_PCIPMCSRBSE 0xFE040046
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#define SH7780_PCI_CDD 0xFE040047
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#define SH7780_PCICR 0xFE040100
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#define SH7780_PCILSR0 0xFE040104
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#define SH7780_PCILSR1 0xFE040108
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#define SH7780_PCILAR0 0xFE04010C
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#define SH7780_PCILAR1 0xFE040110
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#define SH7780_PCIIR 0xFE040114
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#define SH7780_PCIIMR 0xFE040118
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#define SH7780_PCIAIR 0xFE04011C
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#define SH7780_PCICIR 0xFE040120
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#define SH7780_PCIAINT 0xFE040130
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#define SH7780_PCIAINTM 0xFE040134
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#define SH7780_PCIBMIR 0xFE040138
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#define SH7780_PCIPAR 0xFE0401C0
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#define SH7780_PCIPINT 0xFE0401CC
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#define SH7780_PCIPINTM 0xFE0401D0
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#define SH7780_PCIMBR0 0xFE0401E0
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#define SH7780_PCIMBMR0 0xFE0401E4
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#define SH7780_PCIMBR1 0xFE0401E8
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#define SH7780_PCIMBMR1 0xFE0401EC
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#define SH7780_PCIMBR2 0xFE0401F0
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#define SH7780_PCIMBMR2 0xFE0401F4
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#define SH7780_PCIIOBR 0xFE0401F8
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#define SH7780_PCIIOBMR 0xFE0401FC
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#define SH7780_PCICSCR0 0xFE040210
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#define SH7780_PCICSCR1 0xFE040214
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#define SH7780_PCICSAR0 0xFE040218
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#define SH7780_PCICSAR1 0xFE04021C
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#define SH7780_PCIPDR 0xFE040220
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/* DMAC */
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#define DMAC_SAR0 0xFC808020
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46
include/asm-sh/pci.h
Normal file
46
include/asm-sh/pci.h
Normal file
@ -0,0 +1,46 @@
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/*
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* SH4 PCI Controller (PCIC) for U-Boot.
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* (C) Dustin McIntire (dustin@sensoria.com)
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* (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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* (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
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*
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* u-boot/include/asm-sh/pci.h
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_PCI_H_
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#define _ASM_PCI_H_
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#include <pci.h>
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#if defined(CONFIG_CPU_SH7780)
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int pci_sh7780_init(struct pci_controller *hose);
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#else
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#error "Not support PCI."
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#endif
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/* PCI dword read for sh4 */
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int pci_sh4_read_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 *value);
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/* PCI dword write for sh4 */
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int pci_sh4_write_config_dword(struct pci_controller *hose,
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pci_dev_t dev, int offset, u32 value);
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#endif /* _ASM_PCI_H_ */
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2007
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* Copyright (C) 2007,2008
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* This program is free software; you can redistribute it and/or
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@ -95,6 +95,14 @@ static int sh_marubun_init(void)
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}
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#endif /* (CONFIG_CMD_IDE) */
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#if defined(CONFIG_PCI)
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static int sh_pci_init(void)
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{
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pci_init();
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return 0;
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}
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#endif /* CONFIG_PCI */
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static int sh_mem_env_init(void)
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{
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mem_malloc_init();
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@ -140,6 +148,9 @@ init_fnc_t *init_sequence[] =
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sh_mem_env_init,
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#if defined(CONFIG_CMD_NAND)
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sh_nand_init, /* Flash memory (NAND) init */
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#endif
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#if defined(CONFIG_PCI)
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sh_pci_init, /* PCI Init */
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#endif
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devices_init,
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console_init_r,
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