Get MPC8641HPCN flash images working.
Enable the CFI driver. Remove bogus LAWBAR7 cruft. Use correct TEXT_BASE, Fixup load script. Enable SPD EEPROM during DDR setup. Use generic RFC 1918 IP addresses by default.
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5c9efb36a6
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@ -25,8 +25,7 @@
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# default CCSRBAR is at 0xff700000
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# assume U-Boot is less than 0.5MB
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#
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#TEXT_BASE = 0xfff01000
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TEXT_BASE = 0x00400000
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TEXT_BASE = 0xfff01000
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PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
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@ -80,23 +80,6 @@
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#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
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/*
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* Rapid IO at 0xc000_0000 for 512 M
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*/
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/*
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#ifdef CFG_INIT_RAM_LOCK
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#define LAWBAR7 ((CFG_RIO_MEM_BASE>>12) & 0xffffff)
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#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#endif
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*/
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/*
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* Stack at 0xfc00_0000 for 32M on LBC
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*/
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#if !defined(CFG_INIT_RAM_LOCK)
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#define LAWBAR7 ((CFG_INIT_RAM_ADDR>>12) & 0xffffff)
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#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
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#endif
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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@ -28,7 +28,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/
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__DYNAMIC = 0; */
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SECTIONS
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{
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/* .resetvec 0xFFF00100 :
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.resetvec 0xFFF00100 :
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{
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*(.resetvec)
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} = 0xffff
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@ -38,7 +38,7 @@ SECTIONS
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cpu/mpc86xx/start.o (.bootpg)
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board/mpc8641hpcn/init.o (.bootpg)
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} = 0xffff
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*/
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/* Read-only sections, merged into text segment: */
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. = + 1024;
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.interp : { *(.interp) }
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@ -51,6 +51,7 @@
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
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#undef CONFIG_DDR_DLL /* possible DLL fix needed */
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#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
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#define CONFIG_DDR_ECC /* only for ECC DDR module */
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@ -102,11 +103,9 @@
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#else
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/*
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* Manually set up DDR parameters
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* Manually set up DDR1 parameters
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*/
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/* DDR I */
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#if 1
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#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
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#define CFG_DDR_CS0_BNDS 0x0000000F
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@ -125,15 +124,14 @@
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#define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
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#define CFG_DDR_CONTROL2 0x04400000
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//Not used in fixed_sdram function
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/* Not used in fixed_sdram function */
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#define CFG_DDR_MODE 0x00000022
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#define CFG_DDR_CS1_BNDS 0x00000000
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#define CFG_DDR_CS2_BNDS 0x00000FFF //Not done
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#define CFG_DDR_CS3_BNDS 0x00000FFF //Not done
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#define CFG_DDR_CS4_BNDS 0x00000FFF //Not done
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#define CFG_DDR_CS5_BNDS 0x00000FFF //Not done
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#endif
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#define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
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#define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */
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#define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
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#define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
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#endif
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@ -190,6 +188,7 @@
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_CFI
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#define CFG_FLASH_EMPTY_INFO
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@ -199,14 +198,14 @@
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#undef CFG_RAMBOOT
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#endif
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#if !defined(CFG_RAMBOOT)
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
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#if !defined(CONFIG_SPD_EEPROM) && !defined(CFG_RAMBOOT)
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#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
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#endif
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#undef CONFIG_CLOCKS_IN_MHZ
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#define CONFIG_L1_INIT_RAM
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#undef CFG_INIT_RAM_LOCK
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#define CFG_INIT_RAM_LOCK 1
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#ifndef CFG_INIT_RAM_LOCK
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#define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
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#else
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@ -540,22 +539,21 @@
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#define CONFIG_HAS_ETH2 1
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#define CONFIG_HAS_ETH3 1
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#define CONFIG_IPADDR 10.82.193.138
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#define CONFIG_IPADDR 192.168.1.100
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#define CONFIG_HOSTNAME unknown
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#define CONFIG_ROOTPATH /opt/nfsroot
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#define CONFIG_BOOTFILE uImage
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#define CONFIG_SERVERIP 192.168.1.1
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#define CONFIG_GATEWAYIP 10.82.193.104
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#define CONFIG_GATEWAYIP 192.168.1.1
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#define CONFIG_NETMASK 255.255.255.0
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
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//#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_BAUDRATE 115200
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