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ARM: rmobile: Fix SD divider settings on Gen3

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On RCar M3 and on RCar H3 newer than and not including ES1.0, the SD clock
must be divided by 4 rather than 2 because a hardware workaround present
only in the H3 ES1.0 has been removed from these chips. U-Boot currently
only supports M3 and H3 ES 2.0 and newer, so configure the SD pre-divider
to 4 to prevent SD instability.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut 2017-09-05 15:11:14 +02:00 committed by Tom Rini
parent ec6bc928bb
commit 183f5fd3ca
2 changed files with 8 additions and 8 deletions
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8
board/renesas/salvator-x/salvator-x.c
View File

@ -74,10 +74,10 @@ int board_early_init_f(void)
/* SDHI0, 3 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
writel(0, SD0CKCR);
writel(0, SD1CKCR);
writel(0, SD2CKCR);
writel(0, SD3CKCR);
writel(1, SD0CKCR);
writel(1, SD1CKCR);
writel(1, SD2CKCR);
writel(1, SD3CKCR);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */

8
board/renesas/ulcb/ulcb.c
View File

@ -72,10 +72,10 @@ int board_early_init_f(void)
/* SDHI0 */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314);
writel(0, SD0CKCR);
writel(0, SD1CKCR);
writel(0, SD2CKCR);
writel(0, SD3CKCR);
writel(1, SD0CKCR);
writel(1, SD1CKCR);
writel(1, SD2CKCR);
writel(1, SD3CKCR);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */