fsl-diu: Using I/O accessor to CCSR space
Using PPC I/O accessor to DIU I/O space instead of directly read/write. It will prevent the dozen of compiler order issue and PPC hardware order issue for accessing I/O space. Using the toolchain(tc-fsl-x86lnx-e500-dp-4.3.74-2.i386.rpm) can show up the order issue of DIU driver. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -1,5 +1,5 @@
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/*
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* Copyright 2007 Freescale Semiconductor, Inc.
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* Copyright 2007, 2010 Freescale Semiconductor, Inc.
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* York Sun <yorksun@freescale.com>
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*
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* FSL DIU Framebuffer driver
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@ -26,6 +26,7 @@
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#include <common.h>
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#include <i2c.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include "fsl_diu_fb.h"
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@ -267,9 +268,9 @@ int fsl_diu_init(int xres,
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memset(info->screen_base, 0, info->smem_len);
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dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
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dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
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dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
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out_be32(&dr.diu_reg->desc[0], &dummy_ad);
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out_be32(&dr.diu_reg->desc[1], &dummy_ad);
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out_be32(&dr.diu_reg->desc[2], &dummy_ad);
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debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
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debug("dummy desc[0] = 0x%x\n", hw->desc[0]);
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@ -331,26 +332,26 @@ int fsl_diu_init(int xres,
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/* Program DIU registers */
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hw->gamma = (unsigned int) gamma.paddr;
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hw->cursor= (unsigned int) cursor.paddr;
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hw->bgnd = 0x007F7F7F; /* BGND */
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hw->bgnd_wb = 0; /* BGND_WB */
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hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */
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hw->wb_size = 0; /* WB SIZE */
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hw->wb_mem_addr = 0; /* WB MEM ADDR */
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hw->hsyn_para = var->left_margin << 22 | /* BP_H */
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out_be32(&hw->gamma, gamma.paddr);
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out_be32(&hw->cursor, cursor.paddr);
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out_be32(&hw->bgnd, 0x007F7F7F);
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out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
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out_be32(&hw->disp_size, var->yres << 16 | var->xres); /* DISP SIZE */
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out_be32(&hw->wb_size, 0); /* WB SIZE */
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out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
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out_be32(&hw->hsyn_para, var->left_margin << 22 | /* BP_H */
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var->hsync_len << 11 | /* PW_H */
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var->right_margin; /* FP_H */
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hw->vsyn_para = var->upper_margin << 22 | /* BP_V */
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var->right_margin); /* FP_H */
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out_be32(&hw->vsyn_para, var->upper_margin << 22 | /* BP_V */
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var->vsync_len << 11 | /* PW_V */
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var->lower_margin; /* FP_V */
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hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */
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hw->thresholds = 0x00037800; /* The Thresholds */
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hw->int_status = 0; /* INTERRUPT STATUS */
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hw->int_mask = 0; /* INT MASK */
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hw->plut = 0x01F5F666;
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var->lower_margin); /* FP_V */
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out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
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out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */
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out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
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out_be32(&hw->int_mask, 0); /* INT MASK */
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out_be32(&hw->plut, 0x01F5F666);
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/* Pixel Clock configuration */
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debug("DIU pixclock in ps - %d\n", var->pixclock);
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diu_set_pixel_clock(var->pixclock);
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@ -390,8 +391,8 @@ static int fsl_diu_enable_panel(struct fb_info *info)
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struct diu_ad *ad = &fsl_diu_fb_ad;
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debug("Entered: enable_panel\n");
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if (hw->desc[0] != (unsigned int)ad)
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hw->desc[0] = (unsigned int)ad;
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if (in_be32(&hw->desc[0]) != (u32)ad)
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out_be32(&hw->desc[0], ad);
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debug("desc[0] = 0x%x\n", hw->desc[0]);
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return 0;
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}
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@ -401,8 +402,8 @@ static int fsl_diu_disable_panel(struct fb_info *info)
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struct diu *hw = dr.diu_reg;
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debug("Entered: disable_panel\n");
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if (hw->desc[0] != (unsigned int)&dummy_ad)
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hw->desc[0] = (unsigned int)&dummy_ad;
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if (in_be32(&hw->desc[0]) != (u32)&dummy_ad)
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out_be32(&hw->desc[0], &dummy_ad);
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return 0;
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}
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@ -443,7 +444,7 @@ static void enable_lcdc(void)
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debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
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if (!fb_enabled) {
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hw->diu_mode = dr.mode;
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out_be32(&hw->diu_mode, dr.mode);
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fb_enabled++;
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}
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debug("diu_mode = %d\n", hw->diu_mode);
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@ -455,7 +456,7 @@ static void disable_lcdc(void)
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debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
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if (fb_enabled) {
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hw->diu_mode = 0;
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out_be32(&hw->diu_mode, 0);
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fb_enabled = 0;
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}
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}
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