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arm: set cntfrq_el0 if CONFIG_COUNTER_FREQUENCY is valid

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Since COUNTER_FREQUENCY is obselete, so set cntfrq_el0 if
CONFIG_COUNTER_FREQUENCY is valid

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
This commit is contained in:
Peng Fan 2022-04-13 17:47:22 +08:00 committed by Tom Rini
parent c5b9bf5518
commit 151a030063
9 changed files with 13 additions and 13 deletions
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2
arch/arm/cpu/armv7/ls102xa/psci.S
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@ -36,7 +36,7 @@
.align 5
#define ONE_MS (COUNTER_FREQUENCY / 1000)
#define ONE_MS (CONFIG_COUNTER_FREQUENCY / 1000)
#define RESET_WAIT (30 * ONE_MS)
.globl psci_version

2
arch/arm/cpu/armv7/ls102xa/timer.c
View File

@ -65,7 +65,7 @@ int timer_init(void)
/* Enable System Counter */
writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
freq = COUNTER_FREQUENCY;
freq = CONFIG_COUNTER_FREQUENCY;
asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
/* Set PL1 Physical Timer Ctrl */

4
arch/arm/cpu/armv7/nonsec_virt.S
View File

@ -189,11 +189,11 @@ ENTRY(_nonsec_init)
* we do this here instead.
* But first check if we have the generic timer.
*/
#ifdef COUNTER_FREQUENCY
#if CONFIG_COUNTER_FREQUENCY
mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
ldreq r1, =COUNTER_FREQUENCY
ldreq r1, =CONFIG_COUNTER_FREQUENCY
mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
#endif

2
arch/arm/cpu/armv7/sunxi/psci.c
View File

@ -57,7 +57,7 @@ static u32 __secure cp15_read_cntp_ctl(void)
return val;
}
#define ONE_MS (COUNTER_FREQUENCY / 1000)
#define ONE_MS (CONFIG_COUNTER_FREQUENCY / 1000)
static void __secure __mdelay(u32 ms)
{

4
arch/arm/cpu/armv8/start.S
View File

@ -138,9 +138,9 @@ pie_fixup_done:
0:
msr daifclr, #0x4 /* Unmask SError interrupts */
#ifdef COUNTER_FREQUENCY
#if CONFIG_COUNTER_FREQUENCY
branch_if_not_highest_el x0, 4f
ldr x0, =COUNTER_FREQUENCY
ldr x0, =CONFIG_COUNTER_FREQUENCY
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
#endif

2
arch/arm/mach-rockchip/rk3036-board-spl.c
View File

@ -20,7 +20,7 @@
void rockchip_stimer_init(void)
{
asm volatile("mcr p15, 0, %0, c14, c0, 0"
: : "r"(COUNTER_FREQUENCY));
: : "r"(CONFIG_COUNTER_FREQUENCY));
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);

2
arch/arm/mach-rockchip/spl.c
View File

@ -88,7 +88,7 @@ __weak void rockchip_stimer_init(void)
return;
#ifndef CONFIG_ARM64
asm volatile("mcr p15, 0, %0, c14, c0, 0"
: : "r"(COUNTER_FREQUENCY));
: : "r"(CONFIG_COUNTER_FREQUENCY));
#endif
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE);

2
arch/arm/mach-rockchip/tpl.c
View File

@ -39,7 +39,7 @@ __weak void rockchip_stimer_init(void)
#ifndef CONFIG_ARM64
asm volatile("mcr p15, 0, %0, c14, c0, 0"
: : "r"(COUNTER_FREQUENCY));
: : "r"(CONFIG_COUNTER_FREQUENCY));
#endif
writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);

6
board/sunxi/board.c
View File

@ -202,14 +202,14 @@ int board_init(void)
* we avoid the risk of writing to it.
*/
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
if (freq != COUNTER_FREQUENCY) {
if (freq != CONFIG_COUNTER_FREQUENCY) {
debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
freq, COUNTER_FREQUENCY);
freq, CONFIG_COUNTER_FREQUENCY);
#ifdef CONFIG_NON_SECURE
printf("arch timer frequency is wrong, but cannot adjust it\n");
#else
asm volatile("mcr p15, 0, %0, c14, c0, 0"
: : "r"(COUNTER_FREQUENCY));
: : "r"(CONFIG_COUNTER_FREQUENCY));
#endif
}
}