leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ppc: Move brg_clk to arch_global_data

Browse Source 
Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2012-12-13 20:48:44 +00:00 committed by Tom Rini
parent 6cb49c13f6
commit 1206c18403
13 changed files with 26 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/powerpc/cpu/mpc8260/commproc.c
View File

@ -101,7 +101,7 @@ m8260_cpm_hostalloc(uint size, uint align)
* Baud rate clocks are zero-based in the driver code (as that maps
* to port numbers). Documentation uses 1-based numbering.
*/
#define BRG_INT_CLK gd->brg_clk
#define BRG_INT_CLK gd->arch.brg_clk
#define BRG_UART_CLK (BRG_INT_CLK / 16)
/* This function is used by UARTs, or anything else that uses a 16x

2
arch/powerpc/cpu/mpc8260/i2c.c
View File

@ -259,7 +259,7 @@ void i2c_init(int speed, int slaveadd)
* divide BRGCLK by 1)
*/
debug("[I2C] Setting rate...\n");
i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED);
i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED);
/* Set I2C controller in master mode */
i2c->i2c_i2com = 0x01;

4
arch/powerpc/cpu/mpc8260/speed.c
View File

@ -145,7 +145,7 @@ int get_clocks (void)
gd->cpm_clk = gd->vco_out / 2;
gd->bus_clk = clkin;
gd->scc_clk = gd->vco_out / 4;
gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
if (cp->b2c_mult > 0) {
gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
@ -231,7 +231,7 @@ int prt_8260_clks (void)
plldf, pllmf, pcidf);
printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
gd->vco_out, gd->scc_clk, gd->brg_clk);
gd->vco_out, gd->scc_clk, gd->arch.brg_clk);
printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
gd->cpu_clk, gd->cpm_clk, gd->bus_clk);

5
arch/powerpc/cpu/mpc83xx/speed.c
View File

@ -496,7 +496,7 @@ int get_clocks(void)
#endif
#if defined(CONFIG_QE)
gd->qe_clk = qe_clk;
gd->brg_clk = brg_clk;
gd->arch.brg_clk = brg_clk;
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
@ -540,7 +540,8 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
#if defined(CONFIG_QE)
printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk));
printf(" BRG: %-4s MHz\n",
strmhz(buf, gd->arch.brg_clk));
#endif
printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk));

2
arch/powerpc/cpu/mpc85xx/commproc.c
View File

@ -110,7 +110,7 @@ m8560_cpm_hostalloc(uint size, uint align)
* Baud rate clocks are zero-based in the driver code (as that maps
* to port numbers). Documentation uses 1-based numbering.
*/
#define BRG_INT_CLK gd->brg_clk
#define BRG_INT_CLK gd->arch.brg_clk
#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
/* This function is used by UARTS, or anything else that uses a 16x

4
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -395,7 +395,7 @@ int get_clocks (void)
#ifdef CONFIG_QE
gd->qe_clk = sys_info.freqQE;
gd->brg_clk = gd->qe_clk / 2;
gd->arch.brg_clk = gd->qe_clk / 2;
#endif
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
@ -438,7 +438,7 @@ int get_clocks (void)
gd->vco_out = 2*sys_info.freqSystemBus;
gd->cpm_clk = gd->vco_out / 2;
gd->scc_clk = gd->vco_out / 4;
gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
#endif
if(gd->cpu_clk != 0) return (0);

2
arch/powerpc/cpu/mpc8xx/fdt.c
View File

@ -37,7 +37,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
gd->brg_clk, 1);
gd->arch.brg_clk, 1);
/* Fixup ethernet MAC addresses */
fdt_fixup_ethernet(blob);

2
arch/powerpc/cpu/mpc8xx/speed.c
View File

@ -192,7 +192,7 @@ void get_brgclk(uint sccr)
divider = 64;
break;
}
gd->brg_clk = gd->cpu_clk/divider;
gd->arch.brg_clk = gd->cpu_clk/divider;
}
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)

14
arch/powerpc/include/asm/global_data.h
View File

@ -29,6 +29,15 @@
/* Architecture-specific global data */
struct arch_global_data {
#if defined(CONFIG_8xx)
unsigned long brg_clk;
#endif
#if defined(CONFIG_CPM2)
unsigned long brg_clk;
#endif
#if defined(CONFIG_QE)
u32 brg_clk;
#endif
};
/*
@ -45,15 +54,11 @@ typedef struct global_data {
unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#if defined(CONFIG_8xx)
unsigned long brg_clk;
#endif
#if defined(CONFIG_CPM2)
/* There are many clocks on the MPC8260 - see page 9-5 */
unsigned long vco_out;
unsigned long cpm_clk;
unsigned long scc_clk;
unsigned long brg_clk;
#ifdef CONFIG_PCI
unsigned long pci_clk;
#endif
@ -106,7 +111,6 @@ typedef struct global_data {
#endif
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */

2
arch/powerpc/lib/board.c
View File

@ -581,7 +581,7 @@ void board_init_f(ulong bootflag)
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
#if defined(CONFIG_CPM2)
bd->bi_cpmfreq = gd->cpm_clk;
bd->bi_brgfreq = gd->brg_clk;
bd->bi_brgfreq = gd->arch.brg_clk;
bd->bi_sccfreq = gd->scc_clk;
bd->bi_vco = gd->vco_out;
#endif /* CONFIG_CPM2 */

2
common/cmd_immap.c
View File

@ -453,7 +453,7 @@ static void prbrg (int n, uint val)
#if defined(CONFIG_8xx)
ulong clock = gd->cpu_clk;
#elif defined(CONFIG_8260)
ulong clock = gd->brg_clk;
ulong clock = gd->arch.brg_clk;
#endif
printf ("BRG%d:", n);

4
drivers/qe/fdt.c
View File

@ -77,13 +77,13 @@ void ft_qe_setup(void *blob)
do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
"bus-frequency", gd->qe_clk, 1);
do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
"brg-frequency", gd->brg_clk, 1);
"brg-frequency", gd->arch.brg_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe",
"clock-frequency", gd->qe_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe",
"bus-frequency", gd->qe_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe",
"brg-frequency", gd->brg_clk, 1);
"brg-frequency", gd->arch.brg_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe-gtm",
"clock-frequency", gd->qe_clk / 2, 1);
fdt_fixup_qe_firmware(blob);

2
drivers/qe/qe.c
View File

@ -220,7 +220,7 @@ void qe_assign_page(uint snum, uint para_ram_base)
from CLKn pin, we have te change the function.
*/
#define BRG_CLK (gd->brg_clk)
#define BRG_CLK (gd->arch.brg_clk)
int qe_set_brg(uint brg, uint rate)
{