Add mxc_ocotp driver
Add an mxc_ocotp driver for i.MX6. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
This commit is contained in:
Benoît Thébaudeau
Stefano Babic
parent
f6bfd29b11
commit
112fd2ec6c
@ -37,6 +37,20 @@ enum pll_clocks {
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struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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#ifdef CONFIG_MXC_OCOTP
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void enable_ocotp_clk(unsigned char enable)
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{
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u32 reg;
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reg = __raw_readl(&imx_ccm->CCGR2);
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if (enable)
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reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
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else
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reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
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__raw_writel(reg, &imx_ccm->CCGR2);
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}
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#endif
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void enable_usboh3_clk(unsigned char enable)
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{
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u32 reg;
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@ -61,6 +61,7 @@ enum mxc_clock {
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u32 imx_get_uartclk(void);
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u32 imx_get_fecclk(void);
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unsigned int mxc_get_clock(enum mxc_clock clk);
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void enable_ocotp_clk(unsigned char enable);
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void enable_usboh3_clk(unsigned char enable);
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int enable_sata_clock(void);
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
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50
doc/README.mxc_ocotp
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50
doc/README.mxc_ocotp
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@ -0,0 +1,50 @@
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Driver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP)
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on MXC
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This IP can be found on the following SoCs:
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- i.MX6.
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Note that this IP is different from albeit similar to the IPs of the same name
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that can be found on the following SoCs:
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- i.MX23,
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- i.MX28,
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- i.MX50.
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The section numbers in this file refer to the i.MX6 Reference Manual.
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A fuse word contains 32 fuse bit slots, as explained in 46.2.1.
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A bank contains 8 fuse word slots, as explained in 46.2.1 and shown by the
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memory map in 46.4.
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Some fuse bit or word slots may not have the corresponding fuses actually
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implemented in the fusebox.
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See the README files of the SoCs using this driver in order to know the
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conventions used by U-Boot to store some specific data in the fuses, e.g. MAC
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addresses.
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Fuse operations:
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Read
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Read operations are implemented as read accesses to the shadow registers,
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using "Bankx Wordy" from the memory map in 46.4. This is explained in
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detail by the first two paragraphs in 46.2.1.2.
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Sense
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Sense operations are implemented as the direct fusebox read explained by
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the steps in 46.2.1.2.
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Program
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Program operations are implemented as explained by the steps in 46.2.1.3.
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Following this operation, the shadow registers are not reloaded by the
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hardware.
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Override
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Override operations are implemented as write accesses to the shadow
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registers, as explained by the first paragraph in 46.2.1.3.
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Configuration:
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CONFIG_MXC_OCOTP
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Define this to enable the mxc_ocotp driver.
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@ -31,6 +31,7 @@ COBJS-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
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COBJS-$(CONFIG_FSL_IIM) += fsl_iim.o
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COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
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COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
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COBJS-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
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COBJS-$(CONFIG_NS87308) += ns87308.o
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COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
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COBJS-$(CONFIG_STATUS_LED) += status_led.o
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216
drivers/misc/mxc_ocotp.c
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216
drivers/misc/mxc_ocotp.c
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@ -0,0 +1,216 @@
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/*
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* (C) Copyright 2013 ADVANSEE
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* Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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*
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* Based on Dirk Behme's
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* https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
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* which is based on Freescale's
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* http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
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* which is:
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <fuse.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#define BO_CTRL_WR_UNLOCK 16
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#define BM_CTRL_WR_UNLOCK 0xffff0000
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#define BV_CTRL_WR_UNLOCK_KEY 0x3e77
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#define BM_CTRL_ERROR 0x00000200
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#define BM_CTRL_BUSY 0x00000100
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#define BO_CTRL_ADDR 0
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#define BM_CTRL_ADDR 0x0000007f
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#define BO_TIMING_STROBE_READ 16
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#define BM_TIMING_STROBE_READ 0x003f0000
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#define BV_TIMING_STROBE_READ_NS 37
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#define BO_TIMING_RELAX 12
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#define BM_TIMING_RELAX 0x0000f000
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#define BV_TIMING_RELAX_NS 17
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#define BO_TIMING_STROBE_PROG 0
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#define BM_TIMING_STROBE_PROG 0x00000fff
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#define BV_TIMING_STROBE_PROG_US 10
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#define BM_READ_CTRL_READ_FUSE 0x00000001
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#define BF(value, field) (((value) << BO_##field) & BM_##field)
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#define WRITE_POSTAMBLE_US 2
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static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
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{
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while (readl(®s->ctrl) & BM_CTRL_BUSY)
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udelay(delay_us);
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}
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static void clear_error(struct ocotp_regs *regs)
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{
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writel(BM_CTRL_ERROR, ®s->ctrl_clr);
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}
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static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
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int assert, const char *caller)
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{
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*regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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if (bank >= ARRAY_SIZE((*regs)->bank) ||
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word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
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!assert) {
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printf("mxc_ocotp %s(): Invalid argument\n", caller);
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return -EINVAL;
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}
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enable_ocotp_clk(1);
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wait_busy(*regs, 1);
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clear_error(*regs);
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return 0;
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}
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static int finish_access(struct ocotp_regs *regs, const char *caller)
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{
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u32 err;
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err = !!(readl(®s->ctrl) & BM_CTRL_ERROR);
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clear_error(regs);
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enable_ocotp_clk(0);
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if (err) {
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printf("mxc_ocotp %s(): Access protect error\n", caller);
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return -EIO;
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}
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return 0;
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}
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static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
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const char *caller)
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{
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return prepare_access(regs, bank, word, val != NULL, caller);
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}
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int fuse_read(u32 bank, u32 word, u32 *val)
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{
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struct ocotp_regs *regs;
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int ret;
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ret = prepare_read(®s, bank, word, val, __func__);
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if (ret)
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return ret;
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*val = readl(®s->bank[bank].fuse_regs[word << 2]);
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return finish_access(regs, __func__);
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}
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static void set_timing(struct ocotp_regs *regs)
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{
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u32 ipg_clk;
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u32 relax, strobe_read, strobe_prog;
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u32 timing;
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ipg_clk = mxc_get_clock(MXC_IPG_CLK);
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relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
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strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
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1000000000) + 2 * (relax + 1) - 1;
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strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
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2 * (relax + 1) - 1;
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timing = BF(strobe_read, TIMING_STROBE_READ) |
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BF(relax, TIMING_RELAX) |
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BF(strobe_prog, TIMING_STROBE_PROG);
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clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
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BM_TIMING_STROBE_PROG, timing);
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}
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static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
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int write)
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{
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u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
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u32 addr = bank << 3 | word;
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set_timing(regs);
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clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
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BF(wr_unlock, CTRL_WR_UNLOCK) |
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BF(addr, CTRL_ADDR));
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}
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int fuse_sense(u32 bank, u32 word, u32 *val)
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{
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struct ocotp_regs *regs;
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int ret;
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ret = prepare_read(®s, bank, word, val, __func__);
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if (ret)
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return ret;
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setup_direct_access(regs, bank, word, false);
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writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl);
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wait_busy(regs, 1);
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*val = readl(®s->read_fuse_data);
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return finish_access(regs, __func__);
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}
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static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
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const char *caller)
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{
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return prepare_access(regs, bank, word, true, caller);
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}
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int fuse_prog(u32 bank, u32 word, u32 val)
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{
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struct ocotp_regs *regs;
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int ret;
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ret = prepare_write(®s, bank, word, __func__);
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if (ret)
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return ret;
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setup_direct_access(regs, bank, word, true);
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writel(val, ®s->data);
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wait_busy(regs, BV_TIMING_STROBE_PROG_US);
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udelay(WRITE_POSTAMBLE_US);
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return finish_access(regs, __func__);
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}
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int fuse_override(u32 bank, u32 word, u32 val)
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{
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struct ocotp_regs *regs;
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int ret;
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ret = prepare_write(®s, bank, word, __func__);
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if (ret)
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return ret;
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writel(val, ®s->bank[bank].fuse_regs[word << 2]);
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return finish_access(regs, __func__);
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}
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