Patch by Yuli Barcohen, 19 Apr 2004:
- Rename DUET_ADS to MPC885ADS - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY - Clean up FADS family port to use the new defines
This commit is contained in:
wdenk
parent
d7a04603ae
commit
1114257c9d
@ -2,6 +2,12 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Patch by Yuli Barcohen, 19 Apr 2004:
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- Rename DUET_ADS to MPC885ADS
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- Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
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- Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
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- Clean up FADS family port to use the new defines
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* Fix PCI support on CPC45 board
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* Patch by Scott McNutt, 25 Apr 2004:
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2
MAKEALL
2
MAKEALL
@ -34,7 +34,7 @@ LIST_5xxx=" \
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LIST_8xx=" \
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AdderII ADS860 AMX860 c2mon \
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CCM cogent_mpc8xx DUET_ADS ESTEEM192E \
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CCM cogent_mpc8xx MPC885ADS ESTEEM192E \
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ETX094 ELPT860 FADS823 FADS850SAR \
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FADS860T FLAGADM FPS850L GEN860T \
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GEN860T_SC GENIETV GTH hermes \
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2
Makefile
2
Makefile
@ -266,10 +266,10 @@ AdderII_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx adderII
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ADS860_config \
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DUET_ADS_config \
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FADS823_config \
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FADS850SAR_config \
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MPC86xADS_config \
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MPC885ADS_config \
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FADS860T_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8xx fads
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@ -24,8 +24,8 @@
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#
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#
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# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and DUET
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# (MPC87x/88x) ADS boards
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# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and
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# MPC885ADS boards
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#
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TEXT_BASE = 0xFE000000
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@ -26,12 +26,13 @@
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#include <config.h>
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#include <common.h>
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#include <mpc8xx.h>
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#include <pcmcia.h>
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#define _NOT_USED_ 0xFFFFFFFF
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/* ========================================================================= */
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#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */
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#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
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#if defined(CONFIG_DRAM_50MHZ)
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/* 50MHz tables */
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@ -290,7 +291,7 @@ static void _dramdisable(void)
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/* maybe we should turn off upma here or something */
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}
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#endif /* !CONFIG_DUET_ADS */
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#endif /* !CONFIG_MPC885ADS */
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/* ========================================================================= */
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@ -604,7 +605,7 @@ long int initdram (int board_type)
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uint sdramsz = 0; /* size of sdram in Mbytes */
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uint base = 0; /* base of dram in bytes */
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uint m = 0; /* size of dram in Mbytes */
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#ifndef CONFIG_DUET_ADS
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#ifndef CONFIG_MPC885ADS
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uint k, s;
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#endif
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@ -614,7 +615,7 @@ long int initdram (int board_type)
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printf ("(%u MB SDRAM) ", sdramsz);
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}
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#endif
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#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */
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#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
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k = (*((uint *) BCSR2) >> 23) & 0x0f;
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switch (k & 0x3) {
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@ -665,7 +666,7 @@ long int initdram (int board_type)
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_dramdisable ();
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m = 0;
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}
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#endif /* !CONFIG_DUET_ADS */
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#endif /* !CONFIG_MPC885ADS */
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m += sdramsz; /* add sdram size to total */
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return (m << 20);
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@ -734,8 +735,8 @@ int checkboard (void)
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#if defined(CONFIG_MPC86xADS)
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puts ("MPC86xADS");
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#elif defined(CONFIG_DUET_ADS)
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puts ("DUET ADS");
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#elif defined(CONFIG_MPC885ADS)
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puts ("MPC885ADS");
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r = 0; /* I've got NR (No Revision) board */
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#elif defined(CONFIG_FADS)
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puts ("FADS");
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@ -759,7 +760,7 @@ int checkboard (void)
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case 0x03:
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puts ("B \n");
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break;
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#elif defined(CONFIG_DUET_ADS)
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#elif defined(CONFIG_MPC885ADS)
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case 0x00:
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puts ("NR\n");
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break;
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@ -790,7 +791,7 @@ volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
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int pcmcia_init(void)
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{
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volatile pcmconf8xx_t *pcmp;
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uint v, slota, slotb;
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uint v, slota = 0, slotb = 0;
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/*
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** Enable the PCMCIA for a Flash card.
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@ -805,10 +806,10 @@ int pcmcia_init(void)
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/* Set all slots to zero by default. */
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pcmp->pcmc_pgcra = 0;
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pcmp->pcmc_pgcrb = 0;
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#ifdef PCMCIA_SLOT_A
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#ifdef CONFIG_PCMCIA_SLOT_A
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pcmp->pcmc_pgcra = 0x40;
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#endif
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#ifdef PCMCIA_SLOT_B
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#ifdef CONFIG_PCMCIA_SLOT_B
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pcmp->pcmc_pgcrb = 0x40;
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#endif
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@ -817,17 +818,17 @@ int pcmcia_init(void)
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/* Check if any PCMCIA card is plugged in. */
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#ifdef CONFIG_PCMCIA_SLOT_A
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slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
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#endif
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#ifdef CONFIG_PCMCIA_SLOT_B
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slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
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#endif
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if (!(slota || slotb)) {
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printf("No card present\n");
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#ifdef PCMCIA_SLOT_A
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pcmp->pcmc_pgcra = 0;
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#endif
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#ifdef PCMCIA_SLOT_B
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pcmp->pcmc_pgcrb = 0;
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#endif
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return -1;
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}
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else
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@ -908,9 +909,10 @@ int pcmcia_init(void)
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udelay(20);
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#ifdef PCMCIA_SLOT_A
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#ifdef CONFIG_PCMCIA_SLOT_A
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pcmp->pcmc_pgcra = 0;
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#elif PCMCIA_SLOT_B
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#endif
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#ifdef CONFIG_PCMCIA_SLOT_B
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pcmp->pcmc_pgcrb = 0;
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#endif
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@ -48,9 +48,6 @@
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* | ... | v
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*
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*****************************************************************************/
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/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
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/* in general, we always know this for FADS+new ADS anyway */
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#define CONFIG_8xx_GCLK_FREQ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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@ -66,6 +63,7 @@
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"bootm"
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
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/*
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* New MPC86xADS and Duet provide two Ethernet connectivity options:
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@ -90,11 +88,12 @@
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#endif
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#ifndef CONFIG_COMMANDS
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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| CFG_CMD_DHCP \
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| CFG_CMD_IMMAP \
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| CFG_CMD_MII \
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| CFG_CMD_PING \
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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| CFG_CMD_DHCP \
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| CFG_CMD_IMMAP \
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| CFG_CMD_MII \
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| CFG_CMD_PCMCIA \
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| CFG_CMD_PING \
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)
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#endif /* !CONFIG_COMMANDS */
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@ -146,7 +145,7 @@
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#if defined(CONFIG_MPC86xADS) || defined(CONFIG_DUET_ADS) /* New ADS or Duet */
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#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
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#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
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#elif defined(CONFIG_FADS) /* Old/new FADS */
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#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
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@ -186,7 +185,12 @@
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
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#ifdef CONFIG_BZIP2
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#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
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#else
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#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
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#endif /* CONFIG_BZIP2 */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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@ -248,7 +252,16 @@
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 14-22
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*-----------------------------------------------------------------------
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* set the PLL, the low-power modes and the reset control
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*/
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#ifndef CFG_PLPRCR
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#define CFG_PLPRCR PLPRCR_TEXPS
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#endif
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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@ -407,6 +420,20 @@
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#define BCSR4_DATA_VOICE ((uint)0x00080000)
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#endif /* CONFIG_MPC850 */
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/* BSCR5 exists on MPC86xADS and Duet ADS only */
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#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
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#define BCSR5 (CFG_PHYDEV_ADDR + 0x300)
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#define BCSR5_MII2_EN 0x40
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#define BCSR5_MII2_RST 0x20
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#define BCSR5_T1_RST 0x10
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#define BCSR5_ATM155_RST 0x08
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#define BCSR5_ATM25_RST 0x04
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#define BCSR5_MII1_EN 0x02
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#define BCSR5_MII1_RST 0x01
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/* We don't use the 8259.
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*/
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#define NR_8259_INTS 0
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@ -419,10 +446,6 @@
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*/
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#if !defined(CONFIG_MPC823) && !defined(CONFIG_MPC850)
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#define PCMCIA_SLOT_A 1
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#endif
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
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@ -388,7 +388,7 @@ static void fec_pin_init(int fecidx)
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fecp->fec_mii_speed <<= 1;
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#endif
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#if defined(CONFIG_DUET) && defined(WANT_MII)
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#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
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/* use MDC for MII */
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immr->im_ioport.iop_pdpar |= 0x0080;
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immr->im_ioport.iop_pddir &= ~0x0080;
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@ -397,7 +397,7 @@ static void fec_pin_init(int fecidx)
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if (fecidx == 0) {
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#if defined(CONFIG_ETHER_ON_FEC1)
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#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
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#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
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#if !defined(CONFIG_RMII)
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@ -489,7 +489,7 @@ static void fec_pin_init(int fecidx)
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#if defined(CONFIG_ETHER_ON_FEC2)
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#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */
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#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
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#if !defined(CONFIG_RMII)
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@ -516,7 +516,7 @@ static void fec_pin_init(int fecidx)
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immr->im_cpm.cp_cptr &= ~0x00000028;
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#endif /* CONFIG_RMII */
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#endif /* CONFIG_DUET */
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#endif /* CONFIG_MPC885_FAMILY */
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#endif /* CONFIG_ETHER_ON_FEC2 */
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@ -533,7 +533,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
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if (efis->ether_index == 0) {
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#if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
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#if defined(CONFIG_DUET_ADS)
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#if defined(CONFIG_MPC885ADS)
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*(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
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#else
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/* configure FADS for fast (FEC) ethernet, half-duplex */
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@ -553,7 +553,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
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*bcsr4 |= BCSR4_FETHRST;
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udelay (10);
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}
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#endif /* CONFIG_DUET_ADS */
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#endif /* CONFIG_MPC885ADS */
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#endif /* CONFIG_FADS */
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}
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@ -948,7 +948,7 @@ void mii_init (void)
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*/
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fecp->fec_ievent = 0xffc0;
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/* Setup the pin configuration of the FEC(s)
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/* Setup the pin configuration of the FEC(s)
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*/
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fec_pin_init(ether_fcc_info[i].ether_index);
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@ -90,7 +90,7 @@ unsigned long measure_gclk(void)
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ulong timer2_val;
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ulong msr_val;
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#ifdef CONFIG_MPC866_et_al
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#ifdef CFG_8XX_XIN
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/* dont use OSCM, only use EXTCLK/512 */
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immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
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#else
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@ -162,7 +162,7 @@ unsigned long measure_gclk(void)
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timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
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immr->im_sit.sit_piscr &= ~PISCR_PTE;
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#if defined(CONFIG_MPC866_et_al)
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#if defined(CFG_8XX_XIN)
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/* not using OSCM, using XIN, so scale appropriately */
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return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
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#else
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@ -183,22 +183,39 @@ int get_clocks (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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#ifndef CONFIG_8xx_GCLK_FREQ
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gd->cpu_clk = measure_gclk();
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#else /* CONFIG_8xx_GCLK_FREQ */
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uint immr = get_immr (0); /* Return full IMMR contents */
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volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
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uint sccr = immap->im_clkrst.car_sccr;
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/*
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* If for some reason measuring the gclk frequency won't
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* work, we return the hardwired value.
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* (For example, the cogent CMA286-60 CPU module has no
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* separate oscillator for PITRTCLK)
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*/
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#if defined(CONFIG_8xx_GCLK_FREQ)
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gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
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#elif defined(CONFIG_8xx_OSCLK)
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#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
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uint pll = immap->im_clkrst.car_plprcr;
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uint clk;
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if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
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clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
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(PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
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(1<<PLPRCR_val(S));
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} else {
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clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
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}
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if (pll & PLPRCR_CSRC) { /* Low frequency division factor is used */
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gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
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} else { /* High frequency division factor is used */
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gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
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}
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#else
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gd->cpu_clk = measure_gclk();
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#endif /* CONFIG_8xx_GCLK_FREQ */
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if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) {
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if ((sccr & SCCR_EBDF11) == 0) {
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/* No Bus Divider active */
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gd->bus_clk = gd->cpu_clk;
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} else {
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@ -209,7 +226,7 @@ int get_clocks (void)
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return (0);
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}
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#else /* CONFIG_MPC866_et_al */
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#else /* CONFIG_MPC866_FAMILY */
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static long init_pll_866 (long clk);
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@ -345,7 +362,7 @@ static long init_pll_866 (long clk)
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return (n);
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}
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#endif /* CONFIG_MPC866_et_al */
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#endif /* CONFIG_MPC866_FAMILY */
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#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
||||
/*
|
||||
|
||||
@ -475,7 +475,7 @@ typedef struct comm_proc {
|
||||
#define lcd_cmap fl_un.fl_un_cmap
|
||||
char res18[0xE00];
|
||||
|
||||
/* The DUET family has a second FEC here */
|
||||
/* The MPC885 family has a second FEC here */
|
||||
fec_t cp_fec2;
|
||||
#define cp_fec1 cp_fec /* consistency macro */
|
||||
|
||||
|
||||
@ -48,17 +48,17 @@ typedef volatile unsigned char vu_char;
|
||||
defined(CONFIG_MPC859DSL) || \
|
||||
defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \
|
||||
defined(CONFIG_MPC866P)
|
||||
# define CONFIG_MPC866_et_al 1
|
||||
# define CONFIG_MPC866_FAMILY 1
|
||||
#elif defined(CONFIG_MPC870) \
|
||||
|| defined(CONFIG_MPC875) \
|
||||
|| defined(CONFIG_MPC880) \
|
||||
|| defined(CONFIG_MPC885)
|
||||
# define CONFIG_DUET 1
|
||||
# define CONFIG_MPC885_FAMILY 1
|
||||
#endif
|
||||
#if defined(CONFIG_MPC860) \
|
||||
|| defined(CONFIG_MPC860T) \
|
||||
|| defined(CONFIG_MPC866_et_al) \
|
||||
|| defined(CONFIG_DUET)
|
||||
|| defined(CONFIG_MPC866_FAMILY) \
|
||||
|| defined(CONFIG_MPC885_FAMILY)
|
||||
# define CONFIG_MPC86x 1
|
||||
#endif
|
||||
#elif defined(CONFIG_5xx)
|
||||
|
||||
@ -743,7 +743,8 @@ typedef struct scc_enet {
|
||||
#endif /* CONFIG_SCC1_ETHERNET */
|
||||
|
||||
/*
|
||||
* This ENET stuff is for the MPC860TFADS/MPC86xADS/DUET with ethernet on FEC.
|
||||
* This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
|
||||
* with ethernet on FEC.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_FEC_ENET
|
||||
|
||||
@ -26,15 +26,17 @@
|
||||
|
||||
#define CONFIG_BAUDRATE 38400 /* Console baudrate */
|
||||
|
||||
/* CFG_8XX_FACT * CFG_8XX_XIN = 50 MHz */
|
||||
#if 0
|
||||
#define CFG_8XX_XIN 32768 /* 32.768 kHz input frequency */
|
||||
#define CFG_8XX_FACT 0x5F6 /* Multiply by 1526 */
|
||||
#define CFG_8XX_FACT 1526 /* 32.768 kHz crystal on XTAL/EXTAL */
|
||||
#else
|
||||
#define CFG_8XX_XIN 4000000 /* 4 MHz input frequency */
|
||||
#define CFG_8XX_FACT 12 /* Multiply by 12 */
|
||||
#define CFG_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */
|
||||
#endif
|
||||
|
||||
#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
|
||||
#define CONFIG_DRAM_50MHZ 1
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||
| CFG_CMD_DHCP \
|
||||
| CFG_CMD_IMMAP \
|
||||
@ -42,13 +44,9 @@
|
||||
| CFG_CMD_PING \
|
||||
)
|
||||
|
||||
#define CONFIG_DRAM_50MHZ 1
|
||||
|
||||
#include "fads.h"
|
||||
|
||||
#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
|
||||
#define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@ -27,21 +27,19 @@
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
|
||||
#if 0 /* old FADS */
|
||||
# define CFG_8XX_FACT 12 /* Multiply by 12 */
|
||||
# define CFG_8XX_XIN 4000000 /* 4 MHz in */
|
||||
# define CFG_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */
|
||||
#else /* new FADS */
|
||||
# define CFG_8XX_FACT 10 /* Multiply by 10 */
|
||||
# define CFG_8XX_XIN 5000000 /* 5 MHz in */
|
||||
# define CFG_8XX_FACT 10 /* 5 MHz oscillator on EXTCLK */
|
||||
#endif
|
||||
|
||||
#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
|
||||
#define CONFIG_DRAM_50MHZ 1
|
||||
#define CONFIG_SDRAM_50MHZ 1
|
||||
|
||||
#include "fads.h"
|
||||
|
||||
#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
|
||||
#ifdef USE_REAL_FLASH_VALUES
|
||||
/*
|
||||
* These values fit our FADS860T ...
|
||||
@ -53,6 +51,6 @@
|
||||
#define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */
|
||||
#endif
|
||||
|
||||
#define CFG_DAUGHTERBOARD /* FADS has processor-specfic daughterboard */
|
||||
#define CFG_DAUGHTERBOARD /* FADS has processor-specific daughterboard */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@ -33,19 +33,14 @@
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
# define CFG_8XX_FACT 5 /* Multiply by 5 */
|
||||
# define CFG_8XX_XIN 10000000 /* 10 MHz in */
|
||||
#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */
|
||||
|
||||
#define CONFIG_DRAM_50MHZ 1
|
||||
#define CONFIG_SDRAM_50MHZ 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 14-22
|
||||
*-----------------------------------------------------------------------
|
||||
* set the PLL, the low-power modes and the reset control
|
||||
*/
|
||||
#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
|
||||
|
||||
#include "fads.h"
|
||||
|
||||
#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
|
||||
#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
#define __CONFIG_H
|
||||
|
||||
/* Board type */
|
||||
#define CONFIG_DUET_ADS 1 /* Duet (MPC87x/88x) ADS */
|
||||
#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */
|
||||
#define CONFIG_FADS 1 /* We are FADS compatible (more or less) */
|
||||
|
||||
#define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */
|
||||
@ -21,33 +21,25 @@
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
#define CFG_8XX_FACT 5 /* Multiply by 5 */
|
||||
#define CFG_8XX_XIN 10000000 /* 10 MHz in */
|
||||
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
|
||||
|
||||
#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
|
||||
|
||||
#define CONFIG_SDRAM_50MHZ 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 14-22
|
||||
*-----------------------------------------------------------------------
|
||||
* set the PLL, the low-power modes and the reset control
|
||||
*/
|
||||
#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS)
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||
| CFG_CMD_DHCP \
|
||||
| CFG_CMD_IMMAP \
|
||||
| CFG_CMD_MII \
|
||||
| CFG_CMD_PING \
|
||||
)
|
||||
|
||||
#include "fads.h"
|
||||
|
||||
#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
|
||||
#undef CFG_SCCR
|
||||
#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11)
|
||||
|
||||
#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */
|
||||
#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V)
|
||||
|
||||
#define BCSR5 (CFG_PHYDEV_ADDR + 0x300)
|
||||
|
||||
#define BCSR5_MII2_EN 0x40
|
||||
#define BCSR5_MII2_RST 0x20
|
||||
#define BCSR5_T1_RST 0x10
|
||||
#define BCSR5_ATM155_RST 0x08
|
||||
#define BCSR5_ATM25_RST 0x04
|
||||
#define BCSR5_MII1_EN 0x02
|
||||
#define BCSR5_MII1_RST 0x01
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user