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net: phy: ti: Add binding for the CLK_OUT pin muxing

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The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.

Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Janine Hagemann 2018-08-28 08:25:39 +02:00 committed by Joe Hershberger
parent be71a74c59
commit 0f347a0096
3 changed files with 45 additions and 0 deletions
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3
doc/device-tree-bindings/net/ti,dp83867.txt
View File

@ -12,6 +12,8 @@ Required properties:
compensate for the board being designed with the lanes swapped.
- enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
TX/RX lanes.
- ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h
for applicable values
Default child nodes are standard Ethernet PHY device
nodes as described in doc/devicetree/bindings/net/ethernet.txt
@ -24,6 +26,7 @@ Example:
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
enet-phy-lane-no-swap;
ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
};
Datasheet can be found:

27
drivers/net/phy/ti.c
View File

@ -93,6 +93,9 @@
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \
GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
/* CFG4 bits */
#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
@ -110,6 +113,7 @@ struct dp83867_private {
int io_impedance;
bool rxctrl_strap_quirk;
int port_mirroring;
int clk_output_sel;
};
/**
@ -208,6 +212,18 @@ static int dp83867_of_init(struct phy_device *phydev)
{
struct dp83867_private *dp83867 = phydev->priv;
ofnode node;
u16 val;
/* Optional configuration */
/*
* Keep the default value if ti,clk-output-sel is not set
* or to high
*/
dp83867->clk_output_sel =
ofnode_read_u32_default(node, "ti,clk-output-sel",
DP83867_CLK_O_SEL_REF_CLK);
node = phy_get_ofnode(phydev);
if (!ofnode_valid(node))
@ -239,6 +255,17 @@ static int dp83867_of_init(struct phy_device *phydev)
dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
/* Clock output selection if muxing property is set */
if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
DP83867_DEVADDR, phydev->addr);
val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
val |= (dp83867->clk_output_sel <<
DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
DP83867_DEVADDR, phydev->addr, val);
}
return 0;
}
#else

15
include/dt-bindings/net/ti-dp83867.h
View File

@ -31,4 +31,19 @@
#define DP83867_RGMIIDCTL_3_75_NS 0xe
#define DP83867_RGMIIDCTL_4_00_NS 0xf
/* IO_MUX_CFG - Clock output selection */
#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
#define DP83867_CLK_O_SEL_REF_CLK 0xC
#endif