mmc: xenon_sdhci: remove wait_dat0 SDHCI OP
Generic SDHCI driver received support for checking the busy status by
polling the DAT[0] level instead of waiting for the worst MMC switch time.
Unfortunately, it appears that this does not work for Xenon controllers
despite being a part of the standard SDHCI registers and the Armada 3720
datasheet itself telling that BIT(20) is useful for detecting the DAT[0]
busy signal.
I have tried increasing the timeout value, but I have newer managed to
catch DAT_LEVEL bits change from 0 at all.
This issue appears to hit most if not all SoC-s supported by Xenon driver,
at least A3720, A8040 and CN9130 have non working eMMC currently.
So, until a better solution is found drop the wait_dat0 OP for Xenon.
I was able to only test it on A3720, but it should work for others as well.
Fixes: 40e6f52454
("drivers: mmc: Add wait_dat0 support for sdhci driver")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
parent
84191f7384
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0f3466f52f
@ -439,6 +439,8 @@ static const struct sdhci_ops xenon_sdhci_ops = {
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.set_ios_post = xenon_sdhci_set_ios_post
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};
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static struct dm_mmc_ops xenon_mmc_ops;
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static int xenon_sdhci_probe(struct udevice *dev)
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{
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struct xenon_sdhci_plat *plat = dev_get_plat(dev);
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@ -452,6 +454,9 @@ static int xenon_sdhci_probe(struct udevice *dev)
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host->mmc->dev = dev;
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upriv->mmc = host->mmc;
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xenon_mmc_ops = sdhci_ops;
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xenon_mmc_ops.wait_dat0 = NULL;
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/* Set quirks */
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host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;
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@ -568,7 +573,7 @@ U_BOOT_DRIVER(xenon_sdhci_drv) = {
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.id = UCLASS_MMC,
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.of_match = xenon_sdhci_ids,
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.of_to_plat = xenon_sdhci_of_to_plat,
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.ops = &sdhci_ops,
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.ops = &xenon_mmc_ops,
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.bind = xenon_sdhci_bind,
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.probe = xenon_sdhci_probe,
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.remove = xenon_sdhci_remove,
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