net: sunxi_emac: Add CLK support
Add CLk support for sunxi_emac to enable AHB_EMAC clock via CLK framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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@ -6,6 +6,7 @@
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <linux/err.h>
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#include <malloc.h>
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@ -157,6 +158,7 @@ struct sunxi_sramc_regs {
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struct emac_eth_dev {
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struct emac_regs *regs;
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struct clk clk;
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struct mii_dev *bus;
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struct phy_device *phydev;
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int link_printed;
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@ -500,14 +502,12 @@ static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
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return 0;
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}
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static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
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static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_sramc_regs *sram =
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(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
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struct emac_regs *regs = priv->regs;
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int pin;
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int pin, ret;
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/* Map SRAM to EMAC */
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setbits_le32(&sram->ctrl1, 0x5 << 2);
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@ -517,10 +517,16 @@ static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
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/* Set up clock gating */
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setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
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ret = clk_enable(&priv->clk);
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if (ret) {
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dev_err(dev, "failed to enable emac clock\n");
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return ret;
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}
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/* Set MII clock */
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clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
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return 0;
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}
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static int sunxi_emac_eth_start(struct udevice *dev)
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@ -557,9 +563,19 @@ static int sunxi_emac_eth_probe(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct emac_eth_dev *priv = dev_get_priv(dev);
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int ret;
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priv->regs = (struct emac_regs *)pdata->iobase;
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sunxi_emac_board_setup(priv);
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret) {
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dev_err(dev, "failed to get emac clock\n");
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return ret;
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}
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ret = sunxi_emac_board_setup(priv);
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if (ret)
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return ret;
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return sunxi_emac_init_phy(priv, dev);
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}
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