ram: rk3399: update the function of sdram_init
Clean up the sdram_init to keep sync with rockchip source code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
YouMin Chen
Kever Yang
parent
410d7863bc
commit
0cacc27569
@ -78,6 +78,11 @@ struct sdram_rk3399_ops {
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struct rk3399_sdram_params *sdram);
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int (*set_rate_index)(struct dram_info *dram,
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struct rk3399_sdram_params *params);
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void (*modify_param)(const struct chan_info *chan,
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struct rk3399_sdram_params *params);
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struct rk3399_sdram_params *
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(*get_phy_index_params)(u32 phy_fn,
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struct rk3399_sdram_params *params);
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};
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#if defined(CONFIG_TPL_BUILD) || \
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@ -794,46 +799,107 @@ static void set_ds_odt(const struct chan_info *chan,
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phy_io_config(chan, params, mr5);
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}
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static void pctl_start(struct dram_info *dram, u8 channel)
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static void pctl_start(struct dram_info *dram,
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struct rk3399_sdram_params *params,
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u32 channel_mask)
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{
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const struct chan_info *chan = &dram->chan[channel];
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u32 *denali_ctl = chan->pctl->denali_ctl;
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u32 *denali_phy = chan->publ->denali_phy;
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u32 *ddrc0_con = get_ddrc0_con(dram, channel);
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const struct chan_info *chan_0 = &dram->chan[0];
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const struct chan_info *chan_1 = &dram->chan[1];
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u32 *denali_ctl_0 = chan_0->pctl->denali_ctl;
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u32 *denali_phy_0 = chan_0->publ->denali_phy;
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u32 *ddrc0_con_0 = get_ddrc0_con(dram, 0);
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u32 *denali_ctl_1 = chan_1->pctl->denali_ctl;
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u32 *denali_phy_1 = chan_1->publ->denali_phy;
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u32 *ddrc1_con_0 = get_ddrc0_con(dram, 1);
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u32 count = 0;
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u32 byte, tmp;
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writel(0x01000000, &ddrc0_con);
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/* PHY_DLL_RST_EN */
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if (channel_mask & 1) {
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writel(0x01000000, &ddrc0_con_0);
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clrsetbits_le32(&denali_phy_0[957], 0x3 << 24, 0x2 << 24);
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}
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clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
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while (!(readl(&denali_ctl[203]) & (1 << 3))) {
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if (count > 1000) {
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printf("%s: Failed to init pctl for channel %d\n",
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__func__, channel);
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while (1)
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;
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if (channel_mask & 1) {
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count = 0;
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while (!(readl(&denali_ctl_0[203]) & (1 << 3))) {
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if (count > 1000) {
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printf("%s: Failed to init pctl channel 0\n",
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__func__);
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while (1)
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;
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}
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udelay(1);
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count++;
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}
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udelay(1);
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count++;
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writel(0x01000100, &ddrc0_con_0);
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for (byte = 0; byte < 4; byte++) {
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tmp = 0x820;
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writel((tmp << 16) | tmp,
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&denali_phy_0[53 + (128 * byte)]);
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writel((tmp << 16) | tmp,
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&denali_phy_0[54 + (128 * byte)]);
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writel((tmp << 16) | tmp,
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&denali_phy_0[55 + (128 * byte)]);
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writel((tmp << 16) | tmp,
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&denali_phy_0[56 + (128 * byte)]);
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writel((tmp << 16) | tmp,
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&denali_phy_0[57 + (128 * byte)]);
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clrsetbits_le32(&denali_phy_0[58 + (128 * byte)],
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0xffff, tmp);
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}
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clrsetbits_le32(&denali_ctl_0[68], PWRUP_SREFRESH_EXIT,
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dram->pwrup_srefresh_exit[0]);
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}
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writel(0x01000100, &ddrc0_con);
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for (byte = 0; byte < 4; byte++) {
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tmp = 0x820;
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writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);
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writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);
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writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);
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writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);
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writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);
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clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);
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if (channel_mask & 2) {
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writel(0x01000000, &ddrc1_con_0);
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clrsetbits_le32(&denali_phy_1[957], 0x3 << 24, 0x2 << 24);
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}
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if (channel_mask & 2) {
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count = 0;
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while (!(readl(&denali_ctl_1[203]) & (1 << 3))) {
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if (count > 1000) {
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printf("%s: Failed to init pctl channel 1\n",
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__func__);
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while (1)
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;
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}
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udelay(1);
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count++;
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}
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clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
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dram->pwrup_srefresh_exit[channel]);
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writel(0x01000100, &ddrc1_con_0);
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for (byte = 0; byte < 4; byte++) {
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tmp = 0x820;
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writel((tmp << 16) | tmp,
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&denali_phy_1[53 + (128 * byte)]);
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writel((tmp << 16) | tmp,
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&denali_phy_1[54 + (128 * byte)]);
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writel((tmp << 16) | tmp,
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&denali_phy_1[55 + (128 * byte)]);
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writel((tmp << 16) | tmp,
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&denali_phy_1[56 + (128 * byte)]);
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writel((tmp << 16) | tmp,
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&denali_phy_1[57 + (128 * byte)]);
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clrsetbits_le32(&denali_phy_1[58 + (128 * byte)],
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0xffff, tmp);
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}
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clrsetbits_le32(&denali_ctl_1[68], PWRUP_SREFRESH_EXIT,
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dram->pwrup_srefresh_exit[1]);
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/*
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* restore channel 1 RESET original setting
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* to avoid 240ohm too weak to prevent ESD test
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*/
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if (params->base.dramtype == LPDDR4)
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clrsetbits_le32(&denali_phy_1[937], 0xff,
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params->phy_regs.denali_phy[937] &
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0xFF);
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}
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}
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static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
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@ -845,7 +911,10 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
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const u32 *params_ctl = params->pctl_regs.denali_ctl;
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const u32 *params_phy = params->phy_regs.denali_phy;
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u32 tmp, tmp1, tmp2;
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struct rk3399_sdram_params *params_cfg;
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u32 byte;
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dram->ops->modify_param(chan, params);
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/*
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* work around controller bug:
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* Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
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@ -926,33 +995,52 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
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sdram_copy_to_reg(&denali_phy[768], ¶ms_phy[768],
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(805 - 768 + 1) * 4);
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set_ds_odt(chan, params, true, 0);
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if (params->base.dramtype == LPDDR4)
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params_cfg = dram->ops->get_phy_index_params(1, params);
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else
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params_cfg = dram->ops->get_phy_index_params(0, params);
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/*
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* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
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* dqs_tsel_wr_end[7:4] add Half cycle
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*/
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tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
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clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
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tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
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clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
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tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
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clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
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tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
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clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
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clrsetbits_le32(¶ms_cfg->phy_regs.denali_phy[896], 0x3 << 8,
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0 << 8);
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writel(params_cfg->phy_regs.denali_phy[896], &denali_phy[896]);
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/*
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* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
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* dq_tsel_wr_end[7:4] add Half cycle
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*/
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tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
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clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
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tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
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clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
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tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
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clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
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tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
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clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
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writel(params->phy_regs.denali_phy[83] + (0x10 << 16),
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&denali_phy[83]);
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writel(params->phy_regs.denali_phy[84] + (0x10 << 8),
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&denali_phy[84]);
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writel(params->phy_regs.denali_phy[211] + (0x10 << 16),
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&denali_phy[211]);
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writel(params->phy_regs.denali_phy[212] + (0x10 << 8),
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&denali_phy[212]);
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writel(params->phy_regs.denali_phy[339] + (0x10 << 16),
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&denali_phy[339]);
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writel(params->phy_regs.denali_phy[340] + (0x10 << 8),
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&denali_phy[340]);
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writel(params->phy_regs.denali_phy[467] + (0x10 << 16),
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&denali_phy[467]);
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writel(params->phy_regs.denali_phy[468] + (0x10 << 8),
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&denali_phy[468]);
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if (params->base.dramtype == LPDDR4) {
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/*
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* to improve write dqs and dq phase from 1.5ns to 3.5ns
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* at 50MHz. this's the measure result from oscilloscope
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* of dqs and dq write signal.
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*/
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for (byte = 0; byte < 4; byte++) {
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tmp = 0x680;
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clrsetbits_le32(&denali_phy[1 + (128 * byte)],
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0xfff << 8, tmp << 8);
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}
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/*
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* to workaround 366ball two channel's RESET connect to
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* one RESET signal of die
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*/
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if (channel == 1)
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clrsetbits_le32(&denali_phy[937], 0xff,
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PHY_DRV_ODT_240 |
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(PHY_DRV_ODT_240 << 0x4));
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}
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return 0;
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}
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@ -1611,6 +1699,33 @@ static int switch_to_phy_index1(struct dram_info *dram,
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return 0;
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}
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struct rk3399_sdram_params
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*get_phy_index_params(u32 phy_fn,
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struct rk3399_sdram_params *params)
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{
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if (phy_fn == 0)
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return params;
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else
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return NULL;
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}
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void modify_param(const struct chan_info *chan,
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struct rk3399_sdram_params *params)
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{
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struct rk3399_sdram_params *params_cfg;
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u32 *denali_pi_params;
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denali_pi_params = params->pi_regs.denali_pi;
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/* modify PHY F0/F1/F2 params */
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params_cfg = get_phy_index_params(0, params);
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set_ds_odt(chan, params_cfg, false, 0);
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clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24);
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clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24);
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clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24);
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clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1);
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}
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#else
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struct rk3399_sdram_params dfs_cfgs_lpddr4[] = {
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@ -1618,6 +1733,20 @@ struct rk3399_sdram_params dfs_cfgs_lpddr4[] = {
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#include "sdram-rk3399-lpddr4-800.inc"
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};
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static struct rk3399_sdram_params
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*lpddr4_get_phy_index_params(u32 phy_fn,
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struct rk3399_sdram_params *params)
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{
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if (phy_fn == 0)
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return params;
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else if (phy_fn == 1)
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return &dfs_cfgs_lpddr4[1];
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else if (phy_fn == 2)
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return &dfs_cfgs_lpddr4[0];
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else
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return NULL;
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}
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static void *get_denali_pi(const struct chan_info *chan,
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struct rk3399_sdram_params *params, bool reg)
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{
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@ -2017,6 +2146,56 @@ static void set_lpddr4_MR14(const struct chan_info *chan,
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}
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}
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void lpddr4_modify_param(const struct chan_info *chan,
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struct rk3399_sdram_params *params)
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{
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struct rk3399_sdram_params *params_cfg;
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u32 *denali_ctl_params;
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u32 *denali_pi_params;
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u32 *denali_phy_params;
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denali_ctl_params = params->pctl_regs.denali_ctl;
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denali_pi_params = params->pi_regs.denali_pi;
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denali_phy_params = params->phy_regs.denali_phy;
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set_lpddr4_dq_odt(chan, params, 2, true, false, 0);
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set_lpddr4_ca_odt(chan, params, 2, true, false, 0);
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set_lpddr4_MR3(chan, params, 2, false, 0);
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set_lpddr4_MR12(chan, params, 2, false, 0);
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set_lpddr4_MR14(chan, params, 2, false, 0);
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params_cfg = lpddr4_get_phy_index_params(0, params);
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set_ds_odt(chan, params_cfg, false, 0);
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/* read two cycle preamble */
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clrsetbits_le32(&denali_ctl_params[200], 0x3 << 24, 0x3 << 24);
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clrsetbits_le32(&denali_phy_params[7], 0x3 << 24, 0x3 << 24);
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clrsetbits_le32(&denali_phy_params[135], 0x3 << 24, 0x3 << 24);
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clrsetbits_le32(&denali_phy_params[263], 0x3 << 24, 0x3 << 24);
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clrsetbits_le32(&denali_phy_params[391], 0x3 << 24, 0x3 << 24);
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/* boot frequency two cycle preamble */
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clrsetbits_le32(&denali_phy_params[2], 0x3 << 16, 0x3 << 16);
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clrsetbits_le32(&denali_phy_params[130], 0x3 << 16, 0x3 << 16);
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clrsetbits_le32(&denali_phy_params[258], 0x3 << 16, 0x3 << 16);
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clrsetbits_le32(&denali_phy_params[386], 0x3 << 16, 0x3 << 16);
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clrsetbits_le32(&denali_pi_params[45], 0x3 << 8, 0x3 << 8);
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clrsetbits_le32(&denali_pi_params[58], 0x1, 0x1);
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/*
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* bypass mode need PHY_SLICE_PWR_RDC_DISABLE_x = 1,
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* boot frequency mode use bypass mode
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*/
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setbits_le32(&denali_phy_params[10], 1 << 16);
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setbits_le32(&denali_phy_params[138], 1 << 16);
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setbits_le32(&denali_phy_params[266], 1 << 16);
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setbits_le32(&denali_phy_params[394], 1 << 16);
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clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24);
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clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24);
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clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24);
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clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1);
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}
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static void lpddr4_copy_phy(struct dram_info *dram,
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struct rk3399_sdram_params *params, u32 phy_fn,
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struct rk3399_sdram_params *params_cfg,
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@ -2259,44 +2438,46 @@ static void lpddr4_copy_phy(struct dram_info *dram,
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/* phy_939 phy_pad_cs_drive */
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clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
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read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
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set_ds_odt(&dram->chan[channel], params_cfg, true, mr5);
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if (params_cfg->base.dramtype == LPDDR4) {
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read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
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set_ds_odt(&dram->chan[channel], params_cfg, true, mr5);
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ctl_fn = lpddr4_get_ctl_fn(params_cfg, phy_fn);
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set_lpddr4_dq_odt(&dram->chan[channel], params_cfg,
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ctl_fn, true, true, mr5);
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set_lpddr4_ca_odt(&dram->chan[channel], params_cfg,
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ctl_fn, true, true, mr5);
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set_lpddr4_MR3(&dram->chan[channel], params_cfg,
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ctl_fn, true, mr5);
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set_lpddr4_MR12(&dram->chan[channel], params_cfg,
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ctl_fn, true, mr5);
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set_lpddr4_MR14(&dram->chan[channel], params_cfg,
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ctl_fn, true, mr5);
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ctl_fn = lpddr4_get_ctl_fn(params_cfg, phy_fn);
|
||||
set_lpddr4_dq_odt(&dram->chan[channel], params_cfg,
|
||||
ctl_fn, true, true, mr5);
|
||||
set_lpddr4_ca_odt(&dram->chan[channel], params_cfg,
|
||||
ctl_fn, true, true, mr5);
|
||||
set_lpddr4_MR3(&dram->chan[channel], params_cfg,
|
||||
ctl_fn, true, mr5);
|
||||
set_lpddr4_MR12(&dram->chan[channel], params_cfg,
|
||||
ctl_fn, true, mr5);
|
||||
set_lpddr4_MR14(&dram->chan[channel], params_cfg,
|
||||
ctl_fn, true, mr5);
|
||||
|
||||
/*
|
||||
* if phy_sw_master_mode_x not bypass mode,
|
||||
* clear phy_slice_pwr_rdc_disable.
|
||||
* note: need use timings, not ddr_publ_regs
|
||||
*/
|
||||
if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
|
||||
clrbits_le32(&denali_phy[10], 1 << 16);
|
||||
clrbits_le32(&denali_phy[138], 1 << 16);
|
||||
clrbits_le32(&denali_phy[266], 1 << 16);
|
||||
clrbits_le32(&denali_phy[394], 1 << 16);
|
||||
}
|
||||
/*
|
||||
* if phy_sw_master_mode_x not bypass mode,
|
||||
* clear phy_slice_pwr_rdc_disable.
|
||||
* note: need use timings, not ddr_publ_regs
|
||||
*/
|
||||
if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
|
||||
clrbits_le32(&denali_phy[10], 1 << 16);
|
||||
clrbits_le32(&denali_phy[138], 1 << 16);
|
||||
clrbits_le32(&denali_phy[266], 1 << 16);
|
||||
clrbits_le32(&denali_phy[394], 1 << 16);
|
||||
}
|
||||
|
||||
/*
|
||||
* when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
|
||||
* smaller than 8
|
||||
* NOTE: need use timings, not ddr_publ_regs
|
||||
*/
|
||||
if ((denali_phy_params[84] >> 16) & 1) {
|
||||
if (((readl(&denali_ctl[217 + ctl_fn]) >>
|
||||
16) & 0x1f) < 8)
|
||||
clrsetbits_le32(&denali_ctl[217 + ctl_fn],
|
||||
0x1f << 16,
|
||||
8 << 16);
|
||||
/*
|
||||
* when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
|
||||
* smaller than 8
|
||||
* NOTE: need use timings, not ddr_publ_regs
|
||||
*/
|
||||
if ((denali_phy_params[84] >> 16) & 1) {
|
||||
if (((readl(&denali_ctl[217 + ctl_fn]) >>
|
||||
16) & 0x1f) < 8)
|
||||
clrsetbits_le32(&denali_ctl[217 + ctl_fn],
|
||||
0x1f << 16,
|
||||
8 << 16);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -2480,39 +2661,13 @@ static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
|
||||
params->ch[channel].cap_info.ddrconfig = 0;
|
||||
}
|
||||
|
||||
static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)
|
||||
{
|
||||
int channel;
|
||||
int ret;
|
||||
|
||||
for (channel = 0; channel < 2; channel++) {
|
||||
const struct chan_info *chan = &dram->chan[channel];
|
||||
struct rk3399_cru *cru = dram->cru;
|
||||
struct rk3399_ddr_publ_regs *publ = chan->publ;
|
||||
|
||||
phy_pctrl_reset(cru, channel);
|
||||
phy_dll_bypass_set(publ, params->base.ddr_freq);
|
||||
|
||||
ret = pctl_cfg(dram, chan, channel, params);
|
||||
if (ret < 0) {
|
||||
printf("%s: pctl config failed\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* start to trigger initialization */
|
||||
pctl_start(dram, channel);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sdram_init(struct dram_info *dram,
|
||||
struct rk3399_sdram_params *params)
|
||||
{
|
||||
unsigned char dramtype = params->base.dramtype;
|
||||
unsigned int ddr_freq = params->base.ddr_freq;
|
||||
int channel, ch, rank;
|
||||
int ret;
|
||||
u32 ret;
|
||||
|
||||
debug("Starting SDRAM initialization...\n");
|
||||
|
||||
@ -2523,15 +2678,24 @@ static int sdram_init(struct dram_info *dram,
|
||||
return -E2BIG;
|
||||
}
|
||||
|
||||
/* detect rank */
|
||||
for (ch = 0; ch < 2; ch++) {
|
||||
params->ch[ch].cap_info.rank = 2;
|
||||
for (rank = 2; rank != 0; rank--) {
|
||||
ret = pctl_init(dram, params);
|
||||
if (ret < 0) {
|
||||
printf("%s: pctl init failed\n", __func__);
|
||||
return ret;
|
||||
for (channel = 0; channel < 2; channel++) {
|
||||
const struct chan_info *chan =
|
||||
&dram->chan[channel];
|
||||
struct rk3399_cru *cru = dram->cru;
|
||||
struct rk3399_ddr_publ_regs *publ = chan->publ;
|
||||
|
||||
phy_pctrl_reset(cru, channel);
|
||||
phy_dll_bypass_set(publ, ddr_freq);
|
||||
pctl_cfg(dram, chan, channel, params);
|
||||
}
|
||||
|
||||
/* start to trigger initialization */
|
||||
pctl_start(dram, params, 3);
|
||||
|
||||
/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
|
||||
if (dramtype == LPDDR3)
|
||||
udelay(10);
|
||||
@ -2553,7 +2717,8 @@ static int sdram_init(struct dram_info *dram,
|
||||
params->base.num_channels = 0;
|
||||
for (channel = 0; channel < 2; channel++) {
|
||||
const struct chan_info *chan = &dram->chan[channel];
|
||||
struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info;
|
||||
struct sdram_cap_info *cap_info =
|
||||
¶ms->ch[channel].cap_info;
|
||||
u8 training_flag = PI_FULL_TRAINING;
|
||||
|
||||
if (cap_info->rank == 0) {
|
||||
@ -2583,8 +2748,12 @@ static int sdram_init(struct dram_info *dram,
|
||||
|
||||
sdram_print_ddr_info(cap_info, ¶ms->base);
|
||||
set_memory_map(chan, channel, params);
|
||||
cap_info->ddrconfig = calculate_ddrconfig(params, channel);
|
||||
|
||||
cap_info->ddrconfig =
|
||||
calculate_ddrconfig(params, channel);
|
||||
if (-1 == cap_info->ddrconfig) {
|
||||
printf("no ddrconfig find, Cap not support!\n");
|
||||
continue;
|
||||
}
|
||||
set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
|
||||
set_cap_relate_config(chan, params, channel);
|
||||
}
|
||||
@ -2648,9 +2817,13 @@ static const struct sdram_rk3399_ops rk3399_ops = {
|
||||
#if !defined(CONFIG_RAM_RK3399_LPDDR4)
|
||||
.data_training_first = data_training_first,
|
||||
.set_rate_index = switch_to_phy_index1,
|
||||
.modify_param = modify_param,
|
||||
.get_phy_index_params = get_phy_index_params,
|
||||
#else
|
||||
.data_training_first = lpddr4_mr_detect,
|
||||
.set_rate_index = lpddr4_set_rate,
|
||||
.modify_param = lpddr4_modify_param,
|
||||
.get_phy_index_params = lpddr4_get_phy_index_params,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user