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Merge branch 'master' of git://git.denx.de/u-boot-spi

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This commit is contained in:
Tom Rini 2016-12-16 18:32:43 -05:00
commit 0b4bc1b3ab
7 changed files with 94 additions and 175 deletions
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2
arch/arm/dts/am437x-idk-evm.dts
View File

@ -341,7 +341,7 @@
spi-max-frequency = <48000000>; spi-max-frequency = <48000000>;
m25p80@0 { m25p80@0 {
compatible = "mx66l51235l"; compatible = "mx66l51235l", "spi-flash";
spi-max-frequency = <48000000>; spi-max-frequency = <48000000>;
reg = <0>; reg = <0>;
spi-cpol; spi-cpol;

3
drivers/mtd/spi/sf_internal.h
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@ -49,7 +49,6 @@ enum spi_nor_option_flags {
#define CMD_WRITE_DISABLE 0x04 #define CMD_WRITE_DISABLE 0x04
#define CMD_WRITE_ENABLE 0x06 #define CMD_WRITE_ENABLE 0x06
#define CMD_QUAD_PAGE_PROGRAM 0x32 #define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_WRITE_EVCR 0x61
/* Read commands */ /* Read commands */
#define CMD_READ_ARRAY_SLOW 0x03 #define CMD_READ_ARRAY_SLOW 0x03
@ -63,7 +62,6 @@ enum spi_nor_option_flags {
#define CMD_READ_STATUS1 0x35 #define CMD_READ_STATUS1 0x35
#define CMD_READ_CONFIG 0x35 #define CMD_READ_CONFIG 0x35
#define CMD_FLAG_STATUS 0x70 #define CMD_FLAG_STATUS 0x70
#define CMD_READ_EVCR 0x65
/* Bank addr access commands */ /* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR #ifdef CONFIG_SPI_FLASH_BAR
@ -78,7 +76,6 @@ enum spi_nor_option_flags {
#define STATUS_QEB_WINSPAN BIT(1) #define STATUS_QEB_WINSPAN BIT(1)
#define STATUS_QEB_MXIC BIT(6) #define STATUS_QEB_MXIC BIT(6)
#define STATUS_PEC BIT(7) #define STATUS_PEC BIT(7)
#define STATUS_QEB_MICRON BIT(7)
#define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP0 BIT(2) /* Block protect 0 */
#define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP1 BIT(3) /* Block protect 1 */
#define SR_BP2 BIT(4) /* Block protect 2 */ #define SR_BP2 BIT(4) /* Block protect 2 */

68
drivers/mtd/spi/spi_flash.c
View File

@ -112,37 +112,6 @@ static int write_cr(struct spi_flash *flash, u8 wc)
} }
#endif #endif
#ifdef CONFIG_SPI_FLASH_STMICRO
static int read_evcr(struct spi_flash *flash, u8 *evcr)
{
int ret;
const u8 cmd = CMD_READ_EVCR;
ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1);
if (ret < 0) {
debug("SF: error reading EVCR\n");
return ret;
}
return 0;
}
static int write_evcr(struct spi_flash *flash, u8 evcr)
{
u8 cmd;
int ret;
cmd = CMD_WRITE_EVCR;
ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1);
if (ret < 0) {
debug("SF: error while writing EVCR register\n");
return ret;
}
return 0;
}
#endif
#ifdef CONFIG_SPI_FLASH_BAR #ifdef CONFIG_SPI_FLASH_BAR
static int write_bar(struct spi_flash *flash, u32 offset) static int write_bar(struct spi_flash *flash, u32 offset)
{ {
@ -894,34 +863,6 @@ static int spansion_quad_enable(struct spi_flash *flash)
} }
#endif #endif
#ifdef CONFIG_SPI_FLASH_STMICRO
static int micron_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
int ret;
ret = read_evcr(flash, &qeb_status);
if (ret < 0)
return ret;
if (!(qeb_status & STATUS_QEB_MICRON))
return 0;
ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON);
if (ret < 0)
return ret;
/* read EVCR and check it */
ret = read_evcr(flash, &qeb_status);
if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) {
printf("SF: Micron EVCR Quad bit not clear\n");
return -EINVAL;
}
return ret;
}
#endif
static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash) static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
{ {
int tmp; int tmp;
@ -962,7 +903,8 @@ static int set_quad_mode(struct spi_flash *flash,
#endif #endif
#ifdef CONFIG_SPI_FLASH_STMICRO #ifdef CONFIG_SPI_FLASH_STMICRO
case SPI_FLASH_CFI_MFR_STMICRO: case SPI_FLASH_CFI_MFR_STMICRO:
return micron_quad_enable(flash); debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info));
return 0;
#endif #endif
default: default:
printf("SF: Need set QEB func for %02x flash\n", printf("SF: Need set QEB func for %02x flash\n",
@ -985,7 +927,7 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
return 0; return 0;
} }
if (flash->size != size) { if (flash->size > size) {
debug("%s: Memory map must cover entire device\n", __func__); debug("%s: Memory map must cover entire device\n", __func__);
return -1; return -1;
} }
@ -1000,7 +942,7 @@ int spi_flash_scan(struct spi_flash *flash)
{ {
struct spi_slave *spi = flash->spi; struct spi_slave *spi = flash->spi;
const struct spi_flash_info *info = NULL; const struct spi_flash_info *info = NULL;
int ret = -1; int ret;
info = spi_flash_read_id(flash); info = spi_flash_read_id(flash);
if (IS_ERR_OR_NULL(info)) if (IS_ERR_OR_NULL(info))
@ -1166,5 +1108,5 @@ int spi_flash_scan(struct spi_flash *flash)
} }
#endif #endif
return ret; return 0;
} }

6
drivers/spi/cadence_qspi.c
View File

@ -170,14 +170,12 @@ static int cadence_spi_probe(struct udevice *bus)
static int cadence_spi_set_mode(struct udevice *bus, uint mode) static int cadence_spi_set_mode(struct udevice *bus, uint mode)
{ {
struct cadence_spi_priv *priv = dev_get_priv(bus); struct cadence_spi_priv *priv = dev_get_priv(bus);
unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
/* Disable QSPI */ /* Disable QSPI */
cadence_qspi_apb_controller_disable(priv->regbase); cadence_qspi_apb_controller_disable(priv->regbase);
/* Set SPI mode */ /* Set SPI mode */
cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha); cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
/* Enable QSPI */ /* Enable QSPI */
cadence_qspi_apb_controller_enable(priv->regbase); cadence_qspi_apb_controller_enable(priv->regbase);
@ -298,6 +296,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
plat->regbase = (void *)data[0]; plat->regbase = (void *)data[0];
plat->ahbbase = (void *)data[2]; plat->ahbbase = (void *)data[2];
plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
/* All other paramters are embedded in the child node */ /* All other paramters are embedded in the child node */
subnode = fdt_first_subnode(blob, node); subnode = fdt_first_subnode(blob, node);
@ -317,7 +316,6 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255); plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz, __func__, plat->regbase, plat->ahbbase, plat->max_hz,

3
drivers/spi/cadence_qspi.h
View File

@ -63,8 +63,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
void cadence_qspi_apb_chipselect(void *reg_base, void cadence_qspi_apb_chipselect(void *reg_base,
unsigned int chip_select, unsigned int decoder_enable); unsigned int chip_select, unsigned int decoder_enable);
void cadence_qspi_apb_set_clk_mode(void *reg_base_addr, void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
unsigned int clk_pol, unsigned int clk_pha);
void cadence_qspi_apb_config_baudrate_div(void *reg_base, void cadence_qspi_apb_config_baudrate_div(void *reg_base,
unsigned int ref_clk_hz, unsigned int sclk_hz); unsigned int ref_clk_hz, unsigned int sclk_hz);
void cadence_qspi_apb_delay(void *reg_base, void cadence_qspi_apb_delay(void *reg_base,

183
drivers/spi/cadence_qspi_apb.c
View File

@ -32,37 +32,37 @@
#include <spi.h> #include <spi.h>
#include "cadence_qspi.h" #include "cadence_qspi.h"
#define CQSPI_REG_POLL_US (1) /* 1us */ #define CQSPI_REG_POLL_US 1 /* 1us */
#define CQSPI_REG_RETRY (10000) #define CQSPI_REG_RETRY 10000
#define CQSPI_POLL_IDLE_RETRY (3) #define CQSPI_POLL_IDLE_RETRY 3
#define CQSPI_FIFO_WIDTH (4) #define CQSPI_FIFO_WIDTH 4
#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) #define CQSPI_REG_SRAM_THRESHOLD_WORDS 50
/* Transfer mode */ /* Transfer mode */
#define CQSPI_INST_TYPE_SINGLE (0) #define CQSPI_INST_TYPE_SINGLE 0
#define CQSPI_INST_TYPE_DUAL (1) #define CQSPI_INST_TYPE_DUAL 1
#define CQSPI_INST_TYPE_QUAD (2) #define CQSPI_INST_TYPE_QUAD 2
#define CQSPI_STIG_DATA_LEN_MAX (8) #define CQSPI_STIG_DATA_LEN_MAX 8
#define CQSPI_DUMMY_CLKS_PER_BYTE (8)
#define CQSPI_DUMMY_BYTES_MAX (4)
#define CQSPI_DUMMY_CLKS_PER_BYTE 8
#define CQSPI_DUMMY_BYTES_MAX 4
#define CQSPI_REG_SRAM_FILL_THRESHOLD \ #define CQSPI_REG_SRAM_FILL_THRESHOLD \
((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
/**************************************************************************** /****************************************************************************
* Controller's configuration and status register (offset from QSPI_BASE) * Controller's configuration and status register (offset from QSPI_BASE)
****************************************************************************/ ****************************************************************************/
#define CQSPI_REG_CONFIG 0x00 #define CQSPI_REG_CONFIG 0x00
#define CQSPI_REG_CONFIG_CLK_POL_LSB 1 #define CQSPI_REG_CONFIG_ENABLE BIT(0)
#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2 #define CQSPI_REG_CONFIG_CLK_POL BIT(1)
#define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) #define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
#define CQSPI_REG_CONFIG_DIRECT_MASK BIT(7) #define CQSPI_REG_CONFIG_DIRECT BIT(7)
#define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) #define CQSPI_REG_CONFIG_DECODE BIT(9)
#define CQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18) #define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
#define CQSPI_REG_CONFIG_BAUD_LSB 19 #define CQSPI_REG_CONFIG_BAUD_LSB 19
#define CQSPI_REG_CONFIG_IDLE_LSB 31 #define CQSPI_REG_CONFIG_IDLE_LSB 31
@ -94,10 +94,10 @@
#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
#define CQSPI_READLCAPTURE 0x10 #define CQSPI_REG_RD_DATA_CAPTURE 0x10
#define CQSPI_READLCAPTURE_BYPASS_LSB 0 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
#define CQSPI_READLCAPTURE_DELAY_LSB 1 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
#define CQSPI_READLCAPTURE_DELAY_MASK 0xF #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
#define CQSPI_REG_SIZE 0x14 #define CQSPI_REG_SIZE 0x14
#define CQSPI_REG_SIZE_ADDRESS_LSB 0 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
@ -123,18 +123,18 @@
#define CQSPI_REG_IRQMASK 0x44 #define CQSPI_REG_IRQMASK 0x44
#define CQSPI_REG_INDIRECTRD 0x60 #define CQSPI_REG_INDIRECTRD 0x60
#define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) #define CQSPI_REG_INDIRECTRD_START BIT(0)
#define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) #define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK BIT(2) #define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
#define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) #define CQSPI_REG_INDIRECTRD_DONE BIT(5)
#define CQSPI_REG_INDIRECTRDWATERMARK 0x64 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
#define CQSPI_REG_INDIRECTRDBYTES 0x6C #define CQSPI_REG_INDIRECTRDBYTES 0x6C
#define CQSPI_REG_CMDCTRL 0x90 #define CQSPI_REG_CMDCTRL 0x90
#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) #define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) #define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
@ -150,10 +150,10 @@
#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
#define CQSPI_REG_INDIRECTWR 0x70 #define CQSPI_REG_INDIRECTWR 0x70
#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) #define CQSPI_REG_INDIRECTWR_START BIT(0)
#define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) #define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK BIT(2) #define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
#define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) #define CQSPI_REG_INDIRECTWR_DONE BIT(5)
#define CQSPI_REG_INDIRECTWRWATERMARK 0x74 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
@ -169,9 +169,6 @@
((readl(base + CQSPI_REG_CONFIG) >> \ ((readl(base + CQSPI_REG_CONFIG) >> \
CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
@ -197,18 +194,16 @@ void cadence_qspi_apb_controller_enable(void *reg_base)
{ {
unsigned int reg; unsigned int reg;
reg = readl(reg_base + CQSPI_REG_CONFIG); reg = readl(reg_base + CQSPI_REG_CONFIG);
reg |= CQSPI_REG_CONFIG_ENABLE_MASK; reg |= CQSPI_REG_CONFIG_ENABLE;
writel(reg, reg_base + CQSPI_REG_CONFIG); writel(reg, reg_base + CQSPI_REG_CONFIG);
return;
} }
void cadence_qspi_apb_controller_disable(void *reg_base) void cadence_qspi_apb_controller_disable(void *reg_base)
{ {
unsigned int reg; unsigned int reg;
reg = readl(reg_base + CQSPI_REG_CONFIG); reg = readl(reg_base + CQSPI_REG_CONFIG);
reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; reg &= ~CQSPI_REG_CONFIG_ENABLE;
writel(reg, reg_base + CQSPI_REG_CONFIG); writel(reg, reg_base + CQSPI_REG_CONFIG);
return;
} }
/* Return 1 if idle, otherwise return 0 (busy). */ /* Return 1 if idle, otherwise return 0 (busy). */
@ -244,23 +239,22 @@ void cadence_qspi_apb_readdata_capture(void *reg_base,
unsigned int reg; unsigned int reg;
cadence_qspi_apb_controller_disable(reg_base); cadence_qspi_apb_controller_disable(reg_base);
reg = readl(reg_base + CQSPI_READLCAPTURE); reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
if (bypass) if (bypass)
reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB); reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
else else
reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB); reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
<< CQSPI_READLCAPTURE_DELAY_LSB); << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK) reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
<< CQSPI_READLCAPTURE_DELAY_LSB); << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
writel(reg, reg_base + CQSPI_READLCAPTURE); writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
cadence_qspi_apb_controller_enable(reg_base); cadence_qspi_apb_controller_enable(reg_base);
return;
} }
void cadence_qspi_apb_config_baudrate_div(void *reg_base, void cadence_qspi_apb_config_baudrate_div(void *reg_base,
@ -273,54 +267,42 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base,
reg = readl(reg_base + CQSPI_REG_CONFIG); reg = readl(reg_base + CQSPI_REG_CONFIG);
reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
div = ref_clk_hz / sclk_hz; /*
* The baud_div field in the config reg is 4 bits, and the ref clock is
if (div > 32) * divided by 2 * (baud_div + 1). Round up the divider to ensure the
div = 32; * SPI clock rate is less than or equal to the requested clock rate.
*/
/* Check if even number. */ div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
if ((div & 1)) {
div = (div / 2);
} else {
if (ref_clk_hz % sclk_hz)
/* ensure generated SCLK doesn't exceed user
specified sclk_hz */
div = (div / 2);
else
div = (div / 2) - 1;
}
debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
ref_clk_hz, sclk_hz, div);
/* ensure the baud rate doesn't exceed the max value */ /* ensure the baud rate doesn't exceed the max value */
if (div > CQSPI_REG_CONFIG_BAUD_MASK) if (div > CQSPI_REG_CONFIG_BAUD_MASK)
div = CQSPI_REG_CONFIG_BAUD_MASK; div = CQSPI_REG_CONFIG_BAUD_MASK;
debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB); reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
writel(reg, reg_base + CQSPI_REG_CONFIG); writel(reg, reg_base + CQSPI_REG_CONFIG);
cadence_qspi_apb_controller_enable(reg_base); cadence_qspi_apb_controller_enable(reg_base);
return;
} }
void cadence_qspi_apb_set_clk_mode(void *reg_base, void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
unsigned int clk_pol, unsigned int clk_pha)
{ {
unsigned int reg; unsigned int reg;
cadence_qspi_apb_controller_disable(reg_base); cadence_qspi_apb_controller_disable(reg_base);
reg = readl(reg_base + CQSPI_REG_CONFIG); reg = readl(reg_base + CQSPI_REG_CONFIG);
reg &= ~(1 << reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
(CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); if (mode & SPI_CPOL)
reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); reg |= CQSPI_REG_CONFIG_CLK_POL;
if (mode & SPI_CPHA)
reg |= CQSPI_REG_CONFIG_CLK_PHA;
writel(reg, reg_base + CQSPI_REG_CONFIG); writel(reg, reg_base + CQSPI_REG_CONFIG);
cadence_qspi_apb_controller_enable(reg_base); cadence_qspi_apb_controller_enable(reg_base);
return;
} }
void cadence_qspi_apb_chipselect(void *reg_base, void cadence_qspi_apb_chipselect(void *reg_base,
@ -336,9 +318,9 @@ void cadence_qspi_apb_chipselect(void *reg_base,
reg = readl(reg_base + CQSPI_REG_CONFIG); reg = readl(reg_base + CQSPI_REG_CONFIG);
/* docoder */ /* docoder */
if (decoder_enable) { if (decoder_enable) {
reg |= CQSPI_REG_CONFIG_DECODE_MASK; reg |= CQSPI_REG_CONFIG_DECODE;
} else { } else {
reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; reg &= ~CQSPI_REG_CONFIG_DECODE;
/* Convert CS if without decoder. /* Convert CS if without decoder.
* CS0 to 4b'1110 * CS0 to 4b'1110
* CS1 to 4b'1101 * CS1 to 4b'1101
@ -355,7 +337,6 @@ void cadence_qspi_apb_chipselect(void *reg_base,
writel(reg, reg_base + CQSPI_REG_CONFIG); writel(reg, reg_base + CQSPI_REG_CONFIG);
cadence_qspi_apb_controller_enable(reg_base); cadence_qspi_apb_controller_enable(reg_base);
return;
} }
void cadence_qspi_apb_delay(void *reg_base, void cadence_qspi_apb_delay(void *reg_base,
@ -371,16 +352,20 @@ void cadence_qspi_apb_delay(void *reg_base,
cadence_qspi_apb_controller_disable(reg_base); cadence_qspi_apb_controller_disable(reg_base);
/* Convert to ns. */ /* Convert to ns. */
ref_clk_ns = (1000000000) / ref_clk; ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
/* Convert to ns. */ /* Convert to ns. */
sclk_ns = (1000000000) / sclk_hz; sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
/* Plus 1 to round up 1 clock cycle. */ /* The controller adds additional delay to that programmed in the reg */
tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1; if (tshsl_ns >= sclk_ns + ref_clk_ns)
tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1; tshsl_ns -= sclk_ns + ref_clk_ns;
tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1; if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1; tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
<< CQSPI_REG_DELAY_TSHSL_LSB); << CQSPI_REG_DELAY_TSHSL_LSB);
@ -393,7 +378,6 @@ void cadence_qspi_apb_delay(void *reg_base,
writel(reg, reg_base + CQSPI_REG_DELAY); writel(reg, reg_base + CQSPI_REG_DELAY);
cadence_qspi_apb_controller_enable(reg_base); cadence_qspi_apb_controller_enable(reg_base);
return;
} }
void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
@ -421,7 +405,6 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
writel(0, plat->regbase + CQSPI_REG_IRQMASK); writel(0, plat->regbase + CQSPI_REG_IRQMASK);
cadence_qspi_apb_controller_enable(plat->regbase); cadence_qspi_apb_controller_enable(plat->regbase);
return;
} }
static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
@ -432,12 +415,12 @@ static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
/* Write the CMDCTRL without start execution. */ /* Write the CMDCTRL without start execution. */
writel(reg, reg_base + CQSPI_REG_CMDCTRL); writel(reg, reg_base + CQSPI_REG_CMDCTRL);
/* Start execute */ /* Start execute */
reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; reg |= CQSPI_REG_CMDCTRL_EXECUTE;
writel(reg, reg_base + CQSPI_REG_CMDCTRL); writel(reg, reg_base + CQSPI_REG_CMDCTRL);
while (retry--) { while (retry--) {
reg = readl(reg_base + CQSPI_REG_CMDCTRL); reg = readl(reg_base + CQSPI_REG_CMDCTRL);
if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0) if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
break; break;
udelay(1); udelay(1);
} }
@ -655,7 +638,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES); writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
/* Start the indirect read transfer */ /* Start the indirect read transfer */
writel(CQSPI_REG_INDIRECTRD_START_MASK, writel(CQSPI_REG_INDIRECTRD_START,
plat->regbase + CQSPI_REG_INDIRECTRD); plat->regbase + CQSPI_REG_INDIRECTRD);
while (remaining > 0) { while (remaining > 0) {
@ -684,21 +667,21 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
/* Check indirect done status */ /* Check indirect done status */
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD, ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0); CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
if (ret) { if (ret) {
printf("Indirect read completion error (%i)\n", ret); printf("Indirect read completion error (%i)\n", ret);
goto failrd; goto failrd;
} }
/* Clear indirect completion status */ /* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTRD_DONE_MASK, writel(CQSPI_REG_INDIRECTRD_DONE,
plat->regbase + CQSPI_REG_INDIRECTRD); plat->regbase + CQSPI_REG_INDIRECTRD);
return 0; return 0;
failrd: failrd:
/* Cancel the indirect read */ /* Cancel the indirect read */
writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, writel(CQSPI_REG_INDIRECTRD_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTRD); plat->regbase + CQSPI_REG_INDIRECTRD);
return ret; return ret;
} }
@ -746,7 +729,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
/* Start the indirect write transfer */ /* Start the indirect write transfer */
writel(CQSPI_REG_INDIRECTWR_START_MASK, writel(CQSPI_REG_INDIRECTWR_START,
plat->regbase + CQSPI_REG_INDIRECTWR); plat->regbase + CQSPI_REG_INDIRECTWR);
while (remaining > 0) { while (remaining > 0) {
@ -771,20 +754,20 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
/* Check indirect done status */ /* Check indirect done status */
ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR, ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0); CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
if (ret) { if (ret) {
printf("Indirect write completion error (%i)\n", ret); printf("Indirect write completion error (%i)\n", ret);
goto failwr; goto failwr;
} }
/* Clear indirect completion status */ /* Clear indirect completion status */
writel(CQSPI_REG_INDIRECTWR_DONE_MASK, writel(CQSPI_REG_INDIRECTWR_DONE,
plat->regbase + CQSPI_REG_INDIRECTWR); plat->regbase + CQSPI_REG_INDIRECTWR);
return 0; return 0;
failwr: failwr:
/* Cancel the indirect write */ /* Cancel the indirect write */
writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, writel(CQSPI_REG_INDIRECTWR_CANCEL,
plat->regbase + CQSPI_REG_INDIRECTWR); plat->regbase + CQSPI_REG_INDIRECTWR);
return ret; return ret;
} }
@ -795,9 +778,9 @@ void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
/* enter XiP mode immediately and enable direct mode */ /* enter XiP mode immediately and enable direct mode */
reg = readl(reg_base + CQSPI_REG_CONFIG); reg = readl(reg_base + CQSPI_REG_CONFIG);
reg |= CQSPI_REG_CONFIG_ENABLE_MASK; reg |= CQSPI_REG_CONFIG_ENABLE;
reg |= CQSPI_REG_CONFIG_DIRECT_MASK; reg |= CQSPI_REG_CONFIG_DIRECT;
reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK; reg |= CQSPI_REG_CONFIG_XIP_IMM;
writel(reg, reg_base + CQSPI_REG_CONFIG); writel(reg, reg_base + CQSPI_REG_CONFIG);
/* keep the XiP mode */ /* keep the XiP mode */

4
drivers/spi/spi-uclass.c
View File

@ -418,7 +418,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
mode |= SPI_TX_QUAD; mode |= SPI_TX_QUAD;
break; break;
default: default:
error("spi-tx-bus-width %d not supported\n", value); warn_non_spl("spi-tx-bus-width %d not supported\n", value);
break; break;
} }
@ -433,7 +433,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node,
mode |= SPI_RX_QUAD; mode |= SPI_RX_QUAD;
break; break;
default: default:
error("spi-rx-bus-width %d not supported\n", value); warn_non_spl("spi-rx-bus-width %d not supported\n", value);
break; break;
} }