colibri_imx6: get rid of obsolete nospl configurations
Now with SPL long since being in place even for recovery using SDP finally get rid of those nospl configurations. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler
Stefano Babic
parent
15c41a8d9e
commit
0b2bd9feda
@ -1,58 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2014-2016, Toradex AG
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*/
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
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DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
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DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
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/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
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/* DDR3 DATA BUS SIZE: 64BIT */
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/* DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000 */
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/* DDR3 DATA BUS SIZE: 32BIT */
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DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000
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/* Write commands to DDR */
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/* Load Mode Registers */
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/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
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/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
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DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
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/* ZQ calibration */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
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DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
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DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
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@ -1,58 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2014-2016, Toradex AG
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*/
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x2C305503
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D8D63
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
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DATA 4, MX6_MMDC_P0_MDOR, 0x00301023
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DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
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DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556D
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/* CS0 End: 7MSB of ((0x10000000 + 512M) -1) >> 25 */
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
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/* DDR3 DATA BUS SIZE: 64BIT */
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DATA 4, MX6_MMDC_P0_MDCTL, 0x821A0000
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/* DDR3 DATA BUS SIZE: 32BIT */
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/* DATA 4, MX6_MMDC_P0_MDCTL, 0x82190000 */
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/* Write commands to DDR */
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/* Load Mode Registers */
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/* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
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/* DATA 4, MX6_MMDC_P0_MDSCR, 0x04408032 */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
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DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
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/* ZQ calibration */
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
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DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
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DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000000
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000000
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42360232
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x021F022A
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421E0224
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02110218
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x41434344
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4345423E
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x39383339
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3E363930
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00340039
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00120019
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
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@ -5,4 +5,3 @@ S: Maintained
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F: board/toradex/colibri_imx6/
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F: include/configs/colibri_imx6.h
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F: configs/colibri_imx6_defconfig
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F: configs/colibri_imx6_nospl_defconfig
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@ -1,41 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2014-2016, Toradex AG
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*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* set the default clock gate to save power */
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DATA 4, CCM_CCGR0, 0x00C03F3F
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DATA 4, CCM_CCGR1, 0x0030FC03
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DATA 4, CCM_CCGR2, 0x0FFFC000
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DATA 4, CCM_CCGR3, 0x3FF00000
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DATA 4, CCM_CCGR4, 0x00FFF300
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DATA 4, CCM_CCGR5, 0x0F0000C3
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DATA 4, CCM_CCGR6, 0x000003FF
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
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DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
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/*
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* Setup CCM_CCOSR register as follows:
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*
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* cko1_en = 1 --> CKO1 enabled
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* cko1_div = 111 --> divide by 8
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* cko1_sel = 1011 --> ahb_clk_root
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*
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* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
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*/
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DATA 4, CCM_CCOSR, 0x000000fb
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@ -1,37 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2014 Toradex AG
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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#define __ASSEMBLY__
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#include <config.h>
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#include "asm/arch/mx6-ddr.h"
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#include "asm/arch/iomux.h"
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#include "asm/arch/crm_regs.h"
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#include "ddr-setup.cfg"
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#if CONFIG_DDR_MB == 256
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#include "800mhz_2x64mx16.cfg"
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#elif CONFIG_DDR_MB == 512
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#include "800mhz_4x64mx16.cfg"
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#else
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#error "unknown DDR size"
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#endif
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#include "clocks.cfg"
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@ -1,97 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2014-2016, Toradex AG
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*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/*
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* DDR3 settings
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* MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
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* memory bus width: 64 bits x16/x32/x64
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* MX6DL ddr is limited to 800 MHz(400 MHz clock)
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* memory bus width: 64 bits x16/x32/x64
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* MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
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* memory bus width: 32 bits x16/x32
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*/
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DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
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DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
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DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
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DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
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DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
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/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
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DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
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DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
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DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
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DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
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DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
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DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
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DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
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DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
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DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
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DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
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DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
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DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
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/* (differential input) */
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DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
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/* (differential input) */
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DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
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/* disable ddr pullups */
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DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
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/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
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DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
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/* Read data DQ Byte0-3 delay */
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
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/*
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* MDMISC mirroring interleaved (row/bank/col)
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*/
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/* TODO: check what the RALAT field does */
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
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/*
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* MDSCR con_req
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*/
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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@ -1,63 +0,0 @@
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CONFIG_ARM=y
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CONFIG_SYS_THUMB_BUILD=y
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CONFIG_ARCH_MX6=y
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CONFIG_SYS_TEXT_BASE=0x17800000
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CONFIG_TARGET_COLIBRI_IMX6=y
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CONFIG_CMD_HDMIDETECT=y
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CONFIG_ENV_VARS_UBOOT_CONFIG=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256"
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CONFIG_BOOTDELAY=1
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# CONFIG_CONSOLE_MUX is not set
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CONFIG_SUPPORT_RAW_INITRD=y
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CONFIG_MISC_INIT_R=y
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CONFIG_VERSION_VARIABLE=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_BOUNCE_BUFFER=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="Colibri iMX6 # "
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_XIMG is not set
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CONFIG_CMD_ASKENV=y
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CONFIG_CRC32_VERIFY=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_SYS_ALT_MEMTEST=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_BMP=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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CONFIG_DFU_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_MII=y
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CONFIG_USB=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_KEYBOARD=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_MANUFACTURER="Toradex"
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CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
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CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
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CONFIG_CI_UDC=y
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CONFIG_USB_GADGET_DOWNLOAD=y
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CONFIG_USB_HOST_ETHER=y
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CONFIG_VIDEO=y
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CONFIG_FAT_WRITE=y
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CONFIG_OF_LIBFDT=y
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# CONFIG_EFI_LOADER is not set
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