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clk: rockchip: rk3399: Set 50MHz ddr clock

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Add support for setting 50MHz ddr clock.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki 2019-07-16 17:27:35 +05:30 committed by Kever Yang
parent ab0ce36a16
commit 0956568637
1 changed files with 4 additions and 0 deletions
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4
drivers/clk/rockchip/clk_rk3399.c
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@ -827,6 +827,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
switch (set_rate) {
case 50 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
break;
case 200 * MHz:
dpll_cfg = (struct pll_div)
{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};