leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

igep003x: Add support for IGEP SMARC AM335x

Browse Source 
The IGEP SMARC AM335x is an industrial processor module with
following highlights:

  o AM3352 TI processor (Up to AM3359)
  o Cortex-A8 ARM CPU
  o SMARC form factor module
  o Up to 512 MB DDR3 SDRAM / 512 MB FLASH
  o WiFi a/b/g/n and Bluetooth v4.0 on-board
  o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board
  o JTAG debug connector available
  o Designed for industrial range purposes

Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
This commit is contained in:
Pau Pajuelo 2017-04-01 17:18:40 +02:00 committed by Tom Rini
parent 3607e0f86f
commit 09533e5de7
5 changed files with 133 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-omap2/am33xx/Kconfig
View File

@ -46,6 +46,7 @@ config TARGET_AM335X_BALTOS
config TARGET_AM335X_IGEP003X config TARGET_AM335X_IGEP003X
bool "Support am335x_igep003x" bool "Support am335x_igep003x"
select BOARD_LATE_INIT
select DM select DM
select DM_SERIAL select DM_SERIAL
select DM_GPIO select DM_GPIO

126
board/isee/igep003x/board.c
View File

@ -1,7 +1,7 @@
/* /*
* Board functions for IGEP COM AQUILA based boards * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
* *
* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
@ -26,21 +26,72 @@
#include <fdt_support.h> #include <fdt_support.h>
#include <mtd_node.h> #include <mtd_node.h>
#include <jffs2/load_kernel.h> #include <jffs2/load_kernel.h>
#include <environment.h>
#include "board.h" #include "board.h"
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
* and control IGEP0034 green and red LEDs.
* U-boot configures these pins as input pullup to detect board revision:
* IGEP0034-LITE = 0b00
* IGEP0034 (FULL) = 0b01
* IGEP0033 = 0b1X
*/
#define GPIO_GREEN_REVISION 27
#define GPIO_RED_REVISION 26
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/*
* Routine: get_board_revision
* Description: Returns the board revision
*/
static int get_board_revision(void)
{
int revision;
gpio_request(GPIO_GREEN_REVISION, "green_revision");
gpio_direction_input(GPIO_GREEN_REVISION);
revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
gpio_free(GPIO_GREEN_REVISION);
gpio_request(GPIO_RED_REVISION, "red_revision");
gpio_direction_input(GPIO_RED_REVISION);
revision = revision + gpio_get_value(GPIO_RED_REVISION);
gpio_free(GPIO_RED_REVISION);
return revision;
}
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
static const struct ddr_data ddr3_data = { /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
static const struct ddr_data ddr3_igep0034_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct ddr_data ddr3_igep0034_lite_data = {
.datardsratio0 = K4B2G1646EBIH9_RD_DQS, .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
.datawdsratio0 = K4B2G1646EBIH9_WR_DQS, .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE, .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA, .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
}; };
static const struct cmd_control ddr3_cmd_ctrl_data = { static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
.cmd0csratio = K4B2G1646EBIH9_RATIO, .cmd0csratio = K4B2G1646EBIH9_RATIO,
.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
@ -51,7 +102,17 @@ static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
}; };
static struct emif_regs ddr3_emif_reg_data = { static struct emif_regs ddr3_igep0034_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG, .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF, .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1, .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
@ -61,6 +122,22 @@ static struct emif_regs ddr3_emif_reg_data = {
.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY, .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
}; };
const struct ctrl_ioregs ioregs_igep0034 = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
const struct ctrl_ioregs ioregs_igep0034_lite = {
.cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
};
#define OSC (V_OSCK/1000000) #define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = { const struct dpll_params dpll_ddr = {
400, OSC-1, 1, -1, -1, -1, -1}; 400, OSC-1, 1, -1, -1, -1, -1};
@ -80,18 +157,14 @@ void set_mux_conf_regs(void)
enable_board_pin_mux(); enable_board_pin_mux();
} }
const struct ctrl_ioregs ioregs = {
.cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
.dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
};
void sdram_init(void) void sdram_init(void)
{ {
config_ddr(400, &ioregs, &ddr3_data, if (get_board_revision() == 1)
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
&ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
else
config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
&ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
} }
#endif #endif
@ -107,6 +180,26 @@ int board_init(void)
return 0; return 0;
} }
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
switch (get_board_revision()) {
case 0:
setenv("board_name", "igep0034-lite");
break;
case 1:
setenv("board_name", "igep0034");
break;
default:
setenv("board_name", "igep0033");
break;
}
#endif
return 0;
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP #ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd) int ft_board_setup(void *blob, bd_t *bd)
{ {
@ -180,6 +273,9 @@ int board_eth_init(bd_t *bis)
writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN), writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
&cdev->miisel); &cdev->miisel);
if (get_board_revision() == 1)
cpsw_slaves[0].phy_addr = 1;
rv = cpsw_register(&cpsw_data); rv = cpsw_register(&cpsw_data);
if (rv < 0) if (rv < 0)
printf("Error %d registering CPSW switch\n", rv); printf("Error %d registering CPSW switch\n", rv);

10
board/isee/igep003x/mux.c
View File

@ -32,7 +32,7 @@ static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)}, /* MMC0_CD */ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1}, {-1},
}; };
@ -69,6 +69,12 @@ static struct module_pin_mux rmii1_pin_mux[] = {
{-1}, {-1},
}; };
static struct module_pin_mux gpio_pin_mux[] = {
{OFFSET(gpmc_ad10), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_26 */
{OFFSET(gpmc_ad11), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_27 */
{-1},
};
void enable_uart0_pin_mux(void) void enable_uart0_pin_mux(void)
{ {
configure_module_pin_mux(uart0_pin_mux); configure_module_pin_mux(uart0_pin_mux);
@ -85,4 +91,6 @@ void enable_board_pin_mux(void)
configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(mmc0_pin_mux);
/* Ethernet pinmux. */ /* Ethernet pinmux. */
configure_module_pin_mux(rmii1_pin_mux); configure_module_pin_mux(rmii1_pin_mux);
/* GPIO pinmux. */
configure_module_pin_mux(gpio_pin_mux);
} }

0
configs/am335x_igep0033_defconfig → configs/am335x_igep003x_defconfig
View File

15
include/configs/am335x_igep003x.h
View File

@ -34,7 +34,6 @@
DEFAULT_LINUX_BOOT_ENV \ DEFAULT_LINUX_BOOT_ENV \
"bootdir=/boot\0" \ "bootdir=/boot\0" \
"bootfile=zImage\0" \ "bootfile=zImage\0" \
"dtbfile=am335x-base0033.dtb\0" \
"console=ttyO0,115200n8\0" \ "console=ttyO0,115200n8\0" \
"mmcdev=0\0" \ "mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \
@ -48,7 +47,7 @@
"importbootenv=echo Importing environment from mmc ...; " \ "importbootenv=echo Importing environment from mmc ...; " \
"env import -t ${loadaddr} ${filesize}\0" \ "env import -t ${loadaddr} ${filesize}\0" \
"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \ "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
"load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${dtbfile}\0" \ "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcboot=mmc dev ${mmcdev}; " \ "mmcboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \ "if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \ "echo SD/MMC found on device ${mmcdev};" \
@ -79,10 +78,20 @@
"nandboot=echo Booting from nand ...; " \ "nandboot=echo Booting from nand ...; " \
"run nandargs; " \ "run nandargs; " \
"run nandload; " \ "run nandload; " \
"bootz ${loadaddr} - ${fdtaddr} \0" "bootz ${loadaddr} - ${fdtaddr} \0" \
"findfdt="\
"if test ${board_name} = igep0033; then " \
"setenv fdtfile am335x-igep-base0033.dtb; fi; " \
"if test ${board_name} = igep0034; then " \
"setenv fdtfile am335x-igep-base0040.dtb; fi; " \
"if test ${board_name} = igep0034-lite; then " \
"setenv fdtfile am335x-igep-base0040-lite.dtb; fi; " \
"if test ${fdtfile} = ''; then " \
"echo WARNING: Could not determine device tree to use; fi; \0"
#endif #endif
#define CONFIG_BOOTCOMMAND \ #define CONFIG_BOOTCOMMAND \
"run findfdt;" \
"run mmcboot;" \ "run mmcboot;" \
"run nandboot;" "run nandboot;"