arm: a37xx: Update DTS files to version from upstream Linux kernel
This change updates all Armada 37xx DTS files to version which is used by Linux kernel v5.18. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár
Stefan Roese
parent
6560bf4ede
commit
0934dddc64
@ -1,3 +1,4 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell Armada 371x family of SoCs
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* (also named 88F3710)
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@ -6,43 +7,6 @@
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
|
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "armada-37xx.dtsi"
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@ -1,3 +1,4 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell Armada 3720 development board
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* (DB-88F3720-DDR3)
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@ -5,47 +6,14 @@
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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* This file is compatible with the version 1.4 and the version 2.0 of
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* the board, however the CON numbers are different between the 2
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* version
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-372x.dtsi"
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/ {
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@ -56,41 +24,114 @@
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stdout-path = "serial0:115200n8";
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};
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aliases {
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ethernet0 = ð0;
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i2c0 = &i2c0;
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spi0 = &spi0;
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};
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memory {
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
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};
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};
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&comphy {
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phy0 {
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phy-type = <COMPHY_TYPE_USB3_HOST0>;
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phy-speed = <COMPHY_SPEED_5G>;
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exp_usb3_vbus: usb3-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb3-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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regulator-always-on;
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gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_PEX0>;
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phy-speed = <COMPHY_SPEED_2_5G>;
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usb3_phy: usb3-phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&exp_usb3_vbus>;
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};
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vcc_sd_reg1: regulator {
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compatible = "regulator-gpio";
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regulator-name = "vcc_sd1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
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gpios-states = <0>;
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states = <1800000 0x1
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3300000 0x0>;
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enable-active-high;
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};
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vcc_sd_reg2: regulator-vmcc {
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compatible = "regulator-fixed";
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regulator-name = "vcc_sd2";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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enable-active-high;
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gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
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};
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};
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/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
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ð0 {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
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pinctrl-0 = <&rgmii_pins>;
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phy-mode = "rgmii-id";
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phy = <&phy0>;
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status = "okay";
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};
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/* Gigabit module on CON18(V2.0)/CON20(V1.4) */
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ð1 {
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phy-mode = "sgmii";
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phy = <&phy1>;
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status = "okay";
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phy-mode = "rgmii";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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gpio_exp: pca9555@22 {
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x22>;
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/*
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* IO0_0: PWR_EN_USB2 IO1_0: PWR_EN_VTT
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* IO0_1: PWR_EN_USB23 IO1_1: MPCIE_WDISABLE
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* IO0_2: PWR_EN_SATA IO1_2: RGMII_DEV_RSTN
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* IO0_3: PWR_EN_PCIE IO1_3: SGMII_DEV_RSTN
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* IO0_4: PWR_EN_SD
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* IO0_5: PWR_EN_EMMC
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* IO0_6: PWR_EN_RGMII IO1_6: SATA_USB3.0_SEL
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* IO0_7: PWR_EN_SGMII IO1_7: PWR_MCI_PS
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*/
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};
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rtc@68 {
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/* PT7C4337A from pericom fully compatible with the ds1337 */
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compatible = "dallas,ds1337";
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reg = <0x68>;
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};
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};
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&mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
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reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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/* CON3 */
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@ -98,29 +139,24 @@
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status = "okay";
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};
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&sdhci1 {
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdio_pins>;
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status = "okay";
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};
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&sdhci0 {
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non-removable;
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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marvell,pad-type = "fixed-1-8v";
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pinctrl-names = "default";
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pinctrl-0 = <&mmc_pins>;
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status = "okay";
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};
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#address-cells = <1>;
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#size-cells = <0>;
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mmccard: mmccard@0 {
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compatible = "mmc-card";
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reg = <0>;
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};
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/* SD slot module on CON14(V2.0)/CON15(V1.4) */
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&sdhci1 {
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wp-inverted;
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cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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marvell,pad-type = "sd";
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vqmmc-supply = <&vcc_sd_reg1>;
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vmmc-supply = <&vcc_sd_reg2>;
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status = "okay";
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};
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&spi0 {
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@ -128,37 +164,57 @@
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pinctrl-names = "default";
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pinctrl-0 = <&spi_quad_pins>;
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p128", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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m25p80@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <108000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bootloader";
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reg = <0x0 0x200000>;
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};
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partition@200000 {
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label = "U-boot Env";
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reg = <0x200000 0x10000>;
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};
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partition@210000 {
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label = "Linux";
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reg = <0x210000 0xDF0000>;
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};
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};
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};
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};
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/* Exported on the micro USB connector CON32 through an FTDI */
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/*
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* Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through
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* an FTDI (also on CON24(V2.0)/CON26(V1.4)).
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*/
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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/* CON29 */
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/* CON26(V2.0)/CON28(V1.4) */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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};
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/* CON27(V2.0)/CON29(V1.4) */
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&usb2 {
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status = "okay";
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};
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/* CON31 */
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/* CON29(V2.0)/CON31(V1.4) */
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&usb3 {
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status = "okay";
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};
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/* CON17 */
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
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status = "okay";
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usb-phy = <&usb3_phy>;
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};
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@ -1,177 +1,20 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell Armada 3720 community board
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* (ESPRESSOBin)
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* Device Tree file for Globalscale Marvell ESPRESSOBin Board
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* Copyright (C) 2016 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Konstantin Porotchkin <kostap@marvell.com>
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* Romain Perier <romain.perier@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
|
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* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
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*
|
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* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
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*
|
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* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
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/*
|
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* Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
|
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*/
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/dts-v1/;
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#include "armada-372x.dtsi"
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#include "armada-3720-espressobin.dtsi"
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/ {
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model = "Globalscale Marvell ESPRESSOBin Board";
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compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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ethernet0 = ð0;
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i2c0 = &i2c0;
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spi0 = &spi0;
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
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};
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vcc_sd_reg0: regulator@0 {
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compatible = "regulator-gpio";
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regulator-name = "vcc_sd0";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-type = "voltage";
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states = <1800000 0x1
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3300000 0x0>;
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gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
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};
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};
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|
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ð0 {
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status = "okay";
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pinctrl-names = "default";
|
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pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
|
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phy-mode = "rgmii";
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phy_addr = <0x1>;
|
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
|
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};
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&i2c0 {
|
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pinctrl-names = "default";
|
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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};
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/* CON3 */
|
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&sata {
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status = "okay";
|
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phys = <&comphy2 0>;
|
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};
|
||||
|
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&sdhci1 {
|
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pinctrl-names = "default";
|
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pinctrl-0 = <&sdio_pins>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
|
||||
vqmmc-supply = <&vcc_sd_reg0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* U11 */
|
||||
&sdhci0 {
|
||||
non-removable;
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
marvell,xenon-emmc;
|
||||
marvell,xenon-tun-count = <9>;
|
||||
marvell,pad-type = "fixed-1-8v";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc_pins>;
|
||||
status = "okay";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mmccard: mmccard@0 {
|
||||
compatible = "mmc-card";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_quad_pins>;
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
||||
/* Exported on the micro USB connector CON32 through an FTDI */
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON29 */
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON31 */
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
phys = <&comphy0 0>;
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
phys = <&comphy1 0>;
|
||||
};
|
||||
|
||||
218
arch/arm/dts/armada-3720-espressobin.dtsi
Normal file
218
arch/arm/dts/armada-3720-espressobin.dtsi
Normal file
@ -0,0 +1,218 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree file for Globalscale Marvell ESPRESSOBin Board
|
||||
* Copyright (C) 2016 Marvell
|
||||
*
|
||||
* Romain Perier <romain.perier@free-electrons.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-372x.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
/* for dsa slave device */
|
||||
ethernet1 = &switch0port1;
|
||||
ethernet2 = &switch0port2;
|
||||
ethernet3 = &switch0port3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
vcc_sd_reg1: regulator {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vcc_sd1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
||||
gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <0>;
|
||||
states = <1800000 0x1
|
||||
3300000 0x0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
led2: gpio-led2 {
|
||||
/* led2 is working only on v7 board */
|
||||
status = "disabled";
|
||||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led2 {
|
||||
label = "led2";
|
||||
gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* J9 */
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
|
||||
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* J6 */
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* U11 */
|
||||
&sdhci0 {
|
||||
/* Main DTS file for Espressobin is without eMMC */
|
||||
status = "disabled";
|
||||
|
||||
non-removable;
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
marvell,xenon-emmc;
|
||||
marvell,xenon-tun-count = <9>;
|
||||
marvell,pad-type = "fixed-1-8v";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc_pins>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mmccard: mmccard@0 {
|
||||
compatible = "mmc-card";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* J1 */
|
||||
&sdhci1 {
|
||||
wp-inverted;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
|
||||
marvell,pad-type = "sd";
|
||||
vqmmc-supply = <&vcc_sd_reg1>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
reg = <0>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <104000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
||||
/* Exported on the micro USB connector J5 through an FTDI */
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* Connector J17 and J18 expose a number of different features. Some pins are
|
||||
* multiplexed. This is the case for instance for the following features:
|
||||
* - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
|
||||
* how to enable it. Beware that the signals are 1.8V TTL.
|
||||
* - I2C
|
||||
* - SPI
|
||||
* - MMC
|
||||
*/
|
||||
|
||||
/* J7 */
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* J8 */
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
switch0: switch0@1 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
dsa,member = <0 0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0port0: port@0 {
|
||||
reg = <0>;
|
||||
label = "cpu";
|
||||
ethernet = <ð0>;
|
||||
phy-mode = "rgmii-id";
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
switch0port1: port@1 {
|
||||
reg = <1>;
|
||||
label = "wan";
|
||||
phy-handle = <&switch0phy0>;
|
||||
};
|
||||
|
||||
switch0port2: port@2 {
|
||||
reg = <2>;
|
||||
label = "lan0";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
switch0port3: port@3 {
|
||||
reg = <3>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy0: switch0phy0@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
switch0phy1: switch0phy1@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
switch0phy2: switch0phy2@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
@ -1,18 +1,14 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ or X11
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree file for CZ.NIC Turris Mox Board
|
||||
* 2018 by Marek Behun <marek.behun@nic.cz>
|
||||
*
|
||||
* Based on armada-3720-espressobin.dts by:
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Konstantin Porotchkin <kostap@marvell.com>
|
||||
* 2019 by Marek Behún <kabel@kernel.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/bus/moxtet.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include "armada-372x.dtsi"
|
||||
|
||||
/ {
|
||||
@ -20,29 +16,29 @@
|
||||
compatible = "cznic,turris-mox", "marvell,armada3720",
|
||||
"marvell,armada3710";
|
||||
|
||||
aliases {
|
||||
spi0 = &spi0;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
i2c0 = &i2c0;
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
memory {
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led {
|
||||
red {
|
||||
label = "mox:red:activity";
|
||||
gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_ACTIVITY;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
};
|
||||
|
||||
@ -50,7 +46,6 @@
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
compatible = "gpio-keys";
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
|
||||
@ -58,16 +53,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
reg_usb3_vbus: usb3_vbus@0 {
|
||||
exp_usb3_vbus: usb3-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb3-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <2000000>;
|
||||
shutdown-delay-us = <1000000>;
|
||||
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
vsdc_reg: vsdc-reg {
|
||||
@ -84,42 +77,105 @@
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
vsdio_reg: vsdio-reg {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vsdio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
|
||||
eth_phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <0>;
|
||||
states = <1800000 0x1
|
||||
3300000 0x0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
sdhci1_pwrseq: sdhci1-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sfp: sfp {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&i2c0>;
|
||||
los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
|
||||
rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
|
||||
maximum-power-milliwatt = <3000>;
|
||||
|
||||
/* enabled by U-Boot if SFP module is present */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
firmware {
|
||||
armada-3700-rwtm {
|
||||
compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
|
||||
phy-mode = "rgmii";
|
||||
phy = <ð_phy1>;
|
||||
};
|
||||
|
||||
ð1 {
|
||||
phy-mode = "2500base-x";
|
||||
phys = <&comphy0 1>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <100000>;
|
||||
/delete-property/ mrvl,i2c-fast-mode;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtc@6f {
|
||||
compatible = "microchip,mcp7941x";
|
||||
compatible = "microchip,mcp7940x";
|
||||
reg = <0x6f>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
|
||||
status = "okay";
|
||||
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
||||
/*
|
||||
* U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
|
||||
* contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
|
||||
* 2 size cells and also expects that the second range starts at 16 MB offset. If these
|
||||
* conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
|
||||
* space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
|
||||
* for IO and the rest 112 MB (64+32+16) for MEM. Controller supports 32-bit IO mapping.
|
||||
* This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
|
||||
* U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
|
||||
* https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
|
||||
* https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
|
||||
* https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
|
||||
*/
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
|
||||
0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
|
||||
|
||||
/* enabled by U-Boot if PCIe module is present */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð1 {
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
phys = <&comphy0 1>;
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
wp-inverted;
|
||||
bus-width = <4>;
|
||||
@ -129,17 +185,23 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl_nb {
|
||||
spi_cs1_pins: spi-cs1-pins {
|
||||
groups = "spi_cs1";
|
||||
function = "spi";
|
||||
};
|
||||
&sdhci1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio_pins>;
|
||||
non-removable;
|
||||
bus-width = <4>;
|
||||
marvell,pad-type = "sd";
|
||||
vqmmc-supply = <&vsdio_reg>;
|
||||
mmc-pwrseq = <&sdhci1_pwrseq>;
|
||||
/* forbid SDR104 for FCC purposes */
|
||||
sdhci-caps-mask = <0x2 0x0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_cs1_pins>;
|
||||
pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
|
||||
assigned-clocks = <&nb_periph_clk 7>;
|
||||
assigned-clock-parents = <&tbg 1>;
|
||||
assigned-clock-rates = <20000000>;
|
||||
@ -147,10 +209,9 @@
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,s25fl064l", "jedec,spi-nor";
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
@ -184,38 +245,621 @@
|
||||
};
|
||||
};
|
||||
|
||||
moxtet@1 {
|
||||
moxtet: moxtet@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "cznic,moxtet";
|
||||
reg = <1>;
|
||||
reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
|
||||
spi-max-frequency = <1000000>;
|
||||
spi-max-frequency = <10000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
};
|
||||
};
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gpiosb>;
|
||||
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
|
||||
status = "okay";
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "okay";
|
||||
moxtet_sfp: gpio@0 {
|
||||
compatible = "cznic,moxtet-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&comphy2 {
|
||||
connector {
|
||||
compatible = "usb-a-connector";
|
||||
phy-supply = <&exp_usb3_vbus>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
vbus-supply = <®_usb3_vbus>;
|
||||
status = "okay";
|
||||
phys = <&comphy2 0>;
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
&mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
||||
status = "disabled";
|
||||
phys = <&comphy1 0>;
|
||||
pinctrl-0 = <&smi_pins>;
|
||||
status = "okay";
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
/* switch nodes are enabled by U-Boot if modules are present */
|
||||
switch0@10 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0x10 0>;
|
||||
dsa,member = <0 0>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
interrupts = <MOXTET_IRQ_PERIDOT(0)>;
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy1: switch0phy1@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch0phy4: switch0phy4@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch0phy5: switch0phy5@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch0phy6: switch0phy6@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch0phy7: switch0phy7@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch0phy8: switch0phy8@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <0x5>;
|
||||
label = "lan5";
|
||||
phy-handle = <&switch0phy5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <0x6>;
|
||||
label = "lan6";
|
||||
phy-handle = <&switch0phy6>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
reg = <0x7>;
|
||||
label = "lan7";
|
||||
phy-handle = <&switch0phy7>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
reg = <0x8>;
|
||||
label = "lan8";
|
||||
phy-handle = <&switch0phy8>;
|
||||
};
|
||||
|
||||
port@9 {
|
||||
reg = <0x9>;
|
||||
label = "cpu";
|
||||
ethernet = <ð1>;
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
switch0port10: port@a {
|
||||
reg = <0xa>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
link = <&switch1port9 &switch2port9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port-sfp@a {
|
||||
reg = <0xa>;
|
||||
label = "sfp";
|
||||
sfp = <&sfp>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
switch0@2 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <0x2 0>;
|
||||
dsa,member = <0 0>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
interrupts = <MOXTET_IRQ_TOPAZ>;
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy1_topaz: switch0phy1@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch0phy2_topaz: switch0phy2@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch0phy3_topaz: switch0phy3@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch0phy4_topaz: switch0phy4@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1_topaz>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy2_topaz>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3_topaz>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy4_topaz>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <0x5>;
|
||||
label = "cpu";
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
ethernet = <ð1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
switch1@11 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0x11 0>;
|
||||
dsa,member = <0 1>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
interrupts = <MOXTET_IRQ_PERIDOT(1)>;
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch1phy1: switch1phy1@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch1phy2: switch1phy2@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch1phy3: switch1phy3@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch1phy4: switch1phy4@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch1phy5: switch1phy5@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch1phy6: switch1phy6@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch1phy7: switch1phy7@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch1phy8: switch1phy8@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan9";
|
||||
phy-handle = <&switch1phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan10";
|
||||
phy-handle = <&switch1phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan11";
|
||||
phy-handle = <&switch1phy3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan12";
|
||||
phy-handle = <&switch1phy4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <0x5>;
|
||||
label = "lan13";
|
||||
phy-handle = <&switch1phy5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <0x6>;
|
||||
label = "lan14";
|
||||
phy-handle = <&switch1phy6>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
reg = <0x7>;
|
||||
label = "lan15";
|
||||
phy-handle = <&switch1phy7>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
reg = <0x8>;
|
||||
label = "lan16";
|
||||
phy-handle = <&switch1phy8>;
|
||||
};
|
||||
|
||||
switch1port9: port@9 {
|
||||
reg = <0x9>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
link = <&switch0port10>;
|
||||
};
|
||||
|
||||
switch1port10: port@a {
|
||||
reg = <0xa>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
link = <&switch2port9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port-sfp@a {
|
||||
reg = <0xa>;
|
||||
label = "sfp";
|
||||
sfp = <&sfp>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
switch1@2 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <0x2 0>;
|
||||
dsa,member = <0 1>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
interrupts = <MOXTET_IRQ_TOPAZ>;
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch1phy1_topaz: switch1phy1@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch1phy2_topaz: switch1phy2@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch1phy3_topaz: switch1phy3@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch1phy4_topaz: switch1phy4@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan9";
|
||||
phy-handle = <&switch1phy1_topaz>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan10";
|
||||
phy-handle = <&switch1phy2_topaz>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan11";
|
||||
phy-handle = <&switch1phy3_topaz>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan12";
|
||||
phy-handle = <&switch1phy4_topaz>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <0x5>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
link = <&switch0port10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
switch2@12 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
reg = <0x12 0>;
|
||||
dsa,member = <0 2>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
interrupts = <MOXTET_IRQ_PERIDOT(2)>;
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch2phy1: switch2phy1@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch2phy2: switch2phy2@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch2phy3: switch2phy3@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch2phy4: switch2phy4@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch2phy5: switch2phy5@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch2phy6: switch2phy6@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch2phy7: switch2phy7@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch2phy8: switch2phy8@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan17";
|
||||
phy-handle = <&switch2phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan18";
|
||||
phy-handle = <&switch2phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan19";
|
||||
phy-handle = <&switch2phy3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan20";
|
||||
phy-handle = <&switch2phy4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <0x5>;
|
||||
label = "lan21";
|
||||
phy-handle = <&switch2phy5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <0x6>;
|
||||
label = "lan22";
|
||||
phy-handle = <&switch2phy6>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
reg = <0x7>;
|
||||
label = "lan23";
|
||||
phy-handle = <&switch2phy7>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
reg = <0x8>;
|
||||
label = "lan24";
|
||||
phy-handle = <&switch2phy8>;
|
||||
};
|
||||
|
||||
switch2port9: port@9 {
|
||||
reg = <0x9>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
link = <&switch1port10 &switch0port10>;
|
||||
};
|
||||
|
||||
port-sfp@a {
|
||||
reg = <0xa>;
|
||||
label = "sfp";
|
||||
sfp = <&sfp>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
switch2@2 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <0x2 0>;
|
||||
dsa,member = <0 2>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
interrupts = <MOXTET_IRQ_TOPAZ>;
|
||||
status = "disabled";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch2phy1_topaz: switch2phy1@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch2phy2_topaz: switch2phy2@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch2phy3_topaz: switch2phy3@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch2phy4_topaz: switch2phy4@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
reg = <0x1>;
|
||||
label = "lan17";
|
||||
phy-handle = <&switch2phy1_topaz>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <0x2>;
|
||||
label = "lan18";
|
||||
phy-handle = <&switch2phy2_topaz>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <0x3>;
|
||||
label = "lan19";
|
||||
phy-handle = <&switch2phy3_topaz>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <0x4>;
|
||||
label = "lan20";
|
||||
phy-handle = <&switch2phy4_topaz>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <0x5>;
|
||||
label = "dsa";
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
link = <&switch1port10 &switch0port10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -3,30 +3,23 @@
|
||||
* Device tree for the uDPU board.
|
||||
* Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
|
||||
* Copyright (C) 2016 Marvell
|
||||
* Copyright (C) 2018 Methode
|
||||
* Copyright (C) 2018 Telus
|
||||
* Copyright (C) 2019 Methode Electronics
|
||||
* Copyright (C) 2019 Telus
|
||||
*
|
||||
* Vladimir Vid <vladimir.vid@sartura.hr>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "armada-37xx.dtsi"
|
||||
#include "armada-3720-uDPU-u-boot.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-372x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Methode uDPU Board";
|
||||
compatible = "methode,udpu";
|
||||
compatible = "methode,udpu", "marvell,armada3720";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs = "console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000";
|
||||
};
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
spi0 = &spi0;
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
@ -34,56 +27,39 @@
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
mdio: mdio@32004 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ethphy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
ethphy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
scsi: scsi {
|
||||
compatible = "marvell,mvebu-scsi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
max-id = <1>;
|
||||
max-lun = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@11080 {
|
||||
compatible = "marvell,armada-3700-i2c", "simple-bus";
|
||||
reg = <0x0 0x11080 0x0 0x80>;
|
||||
leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
compatible = "gpio-leds";
|
||||
|
||||
uart1: serial@12200 {
|
||||
compatible = "marvell,armada-3700-uart-ext";
|
||||
reg = <0x0 0x12200 0x0 0x30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "okay";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
};
|
||||
power1 {
|
||||
label = "udpu:green:power";
|
||||
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc_sd_reg0: regulator@0 {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "vcc_sd0";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-type = "voltage";
|
||||
states = <1800000 0x1
|
||||
3300000 0x0>;
|
||||
gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
|
||||
power2 {
|
||||
label = "udpu:red:power";
|
||||
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
network1 {
|
||||
label = "udpu:green:network";
|
||||
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
network2 {
|
||||
label = "udpu:red:network";
|
||||
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
alarm1 {
|
||||
label = "udpu:green:alarm";
|
||||
gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
alarm2 {
|
||||
label = "udpu:red:alarm";
|
||||
gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
sfp_eth0: sfp-eth0 {
|
||||
@ -93,40 +69,29 @@
|
||||
mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
|
||||
maximum-power-milliwatt = <3000>;
|
||||
};
|
||||
|
||||
sfp_eth1: sfp-eth1 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&i2c1>;
|
||||
sfp,ethernet = <ð1>;
|
||||
los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
|
||||
maximum-power-milliwatt = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
phy = <ðphy0>;
|
||||
phys = <&comphy1 0>;
|
||||
};
|
||||
|
||||
ð1 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
phy = <ðphy1>;
|
||||
phys = <&comphy0 1>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
marvell,pad-type = "fixed-1-8v";
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
@ -134,47 +99,90 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_quad_pins>;
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q1024a","n25q512a";
|
||||
m25p80@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
m25p,fast-read;
|
||||
spi-max-frequency = <54000000>;
|
||||
|
||||
partition@0 {
|
||||
label = "uboot";
|
||||
reg = <0 0x400000>;
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/* only bootloader is located on the SPI */
|
||||
partition@0 {
|
||||
label = "uboot";
|
||||
reg = <0 0x400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
non-removable;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-hs200-1_8v;
|
||||
bus-width = <4>;
|
||||
vqmmc-supply = <&vcc_sd_reg0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio_pins>;
|
||||
status = "okay";
|
||||
&pinctrl_nb {
|
||||
i2c1_recovery_pins: i2c1-recovery-pins {
|
||||
groups = "i2c1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mmccard: mmccard@0 {
|
||||
compatible = "mmc-card";
|
||||
reg = <0>;
|
||||
i2c2_recovery_pins: i2c2-recovery-pins {
|
||||
groups = "i2c2";
|
||||
function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "recovery";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-1 = <&i2c1_recovery_pins>;
|
||||
/delete-property/mrvl,i2c-fast-mode;
|
||||
scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "recovery";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
pinctrl-1 = <&i2c2_recovery_pins>;
|
||||
/delete-property/mrvl,i2c-fast-mode;
|
||||
scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
||||
|
||||
lm75@48 {
|
||||
status = "okay";
|
||||
compatible = "lm75";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
lm75@49 {
|
||||
status = "okay";
|
||||
compatible = "lm75";
|
||||
reg = <0x49>;
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
phy-mode = "sgmii";
|
||||
status = "okay";
|
||||
managed = "in-band-status";
|
||||
phys = <&comphy1 0>;
|
||||
sfp = <&sfp_eth0>;
|
||||
};
|
||||
|
||||
ð1 {
|
||||
phy-mode = "sgmii";
|
||||
status = "okay";
|
||||
managed = "in-band-status";
|
||||
phys = <&comphy0 1>;
|
||||
sfp = <&sfp_eth1>;
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
status = "okay";
|
||||
phys = <&usb2_utmi_otg_phy>;
|
||||
phy-names = "usb2-utmi-otg-phy";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 372x family of SoCs
|
||||
* (also named 88F3720)
|
||||
@ -6,43 +7,6 @@
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-37xx.dtsi"
|
||||
@ -52,10 +16,11 @@
|
||||
compatible = "marvell,armada3720", "marvell,armada3710";
|
||||
|
||||
cpus {
|
||||
cpu@1 {
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53","arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
clocks = <&nb_periph_clk 16>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 37xx family of SoCs.
|
||||
*
|
||||
@ -5,48 +6,9 @@
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/comphy/comphy_data.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 37xx SoC";
|
||||
@ -57,15 +19,32 @@
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/*
|
||||
* The PSCI firmware region depicted below is the default one
|
||||
* and should be updated by the bootloader.
|
||||
*/
|
||||
psci-area@4000000 {
|
||||
reg = <0 0x4000000 0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0>;
|
||||
clocks = <&nb_periph_clk 16>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
@ -77,14 +56,15 @@
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
soc {
|
||||
@ -93,53 +73,123 @@
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
internal-regs {
|
||||
internal-regs@d0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
/* 32M internal register @ 0xd000_0000 */
|
||||
ranges = <0x0 0x0 0xd0000000 0x2000000>;
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "marvell,armada-3700-uart";
|
||||
reg = <0x12000 0x400>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
wdt: watchdog@8300 {
|
||||
compatible = "marvell,armada-3700-wdt";
|
||||
reg = <0x8300 0x40>;
|
||||
marvell,system-controller = <&cpu_misc>;
|
||||
clocks = <&xtalclk>;
|
||||
};
|
||||
|
||||
cpu_misc: system-controller@d000 {
|
||||
compatible = "marvell,armada-3700-cpu-misc",
|
||||
"syscon";
|
||||
reg = <0xd000 0x1000>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-3700-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10600 0xA00>;
|
||||
clocks = <&nb_periph_clk 7>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
num-cs = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt: watchdog-timer@8300 {
|
||||
compatible = "marvell,armada-3700-wdt";
|
||||
reg = <0x8300 0x40>;
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,armada-3700-i2c";
|
||||
reg = <0x11000 0x24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&nb_periph_clk 10>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
mrvl,i2c-fast-mode;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11080 {
|
||||
compatible = "marvell,armada-3700-i2c";
|
||||
reg = <0x11080 0x24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&nb_periph_clk 9>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
mrvl,i2c-fast-mode;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
avs: avs@11500 {
|
||||
compatible = "marvell,armada-3700-avs",
|
||||
"syscon";
|
||||
reg = <0x11500 0x40>;
|
||||
};
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "marvell,armada-3700-uart";
|
||||
reg = <0x12000 0x18>;
|
||||
clocks = <&xtalclk>;
|
||||
interrupts =
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "uart-sum", "uart-tx", "uart-rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@12200 {
|
||||
compatible = "marvell,armada-3700-uart-ext";
|
||||
reg = <0x12200 0x30>;
|
||||
clocks = <&xtalclk>;
|
||||
interrupts =
|
||||
<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "uart-tx", "uart-rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nb_periph_clk: nb-periph-clk@13000 {
|
||||
compatible = "marvell,armada-3700-periph-clock-nb";
|
||||
compatible = "marvell,armada-3700-periph-clock-nb",
|
||||
"syscon";
|
||||
reg = <0x13000 0x100>;
|
||||
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
|
||||
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
|
||||
<&tbg 3>, <&xtalclk>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sb_periph_clk: sb-periph-clk@18000 {
|
||||
compatible = "marvell,armada-3700-periph-clock-sb";
|
||||
reg = <0x18000 0x100>;
|
||||
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
|
||||
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
|
||||
<&tbg 3>, <&xtalclk>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
tbg: tbg@13200 {
|
||||
compatible = "marvell,armada-3700-tbg-clock";
|
||||
reg = <0x13200 0x100>;
|
||||
clocks = <&xtalclk>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl_nb: pinctrl-nb@13800 {
|
||||
pinctrl_nb: pinctrl@13800 {
|
||||
compatible = "marvell,armada3710-nb-pinctrl",
|
||||
"syscon", "simple-mfd";
|
||||
"syscon", "simple-mfd";
|
||||
reg = <0x13800 0x100>, <0x13C00 0x20>;
|
||||
gpionb: gpionb {
|
||||
/* MPP1[19:0] */
|
||||
gpionb: gpio {
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl_nb 0 0 36>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts =
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@ -153,7 +203,12 @@
|
||||
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
xtalclk: xtal-clk {
|
||||
compatible = "marvell,armada-3700-xtal-clock";
|
||||
clock-output-names = "xtal";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
spi_quad_pins: spi-quad-pins {
|
||||
@ -161,6 +216,11 @@
|
||||
function = "spi";
|
||||
};
|
||||
|
||||
spi_cs1_pins: spi-cs1-pins {
|
||||
groups = "spi_cs1";
|
||||
function = "spi";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1-pins {
|
||||
groups = "i2c1";
|
||||
function = "i2c";
|
||||
@ -187,14 +247,54 @@
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sb: pinctrl-sb@18800 {
|
||||
nb_pm: syscon@14000 {
|
||||
compatible = "marvell,armada-3700-nb-pm",
|
||||
"syscon";
|
||||
reg = <0x14000 0x60>;
|
||||
};
|
||||
|
||||
comphy: phy@18300 {
|
||||
compatible = "marvell,comphy-a3700";
|
||||
reg = <0x18300 0x300>,
|
||||
<0x1F000 0x400>,
|
||||
<0x5C000 0x400>,
|
||||
<0xe0178 0x8>;
|
||||
reg-names = "comphy",
|
||||
"lane1_pcie_gbe",
|
||||
"lane0_usb3_gbe",
|
||||
"lane2_sata_usb3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&xtalclk>;
|
||||
clock-names = "xtal";
|
||||
|
||||
comphy0: phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
comphy1: phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
comphy2: phy@2 {
|
||||
reg = <2>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sb: pinctrl@18800 {
|
||||
compatible = "marvell,armada3710-sb-pinctrl",
|
||||
"syscon", "simple-mfd";
|
||||
"syscon", "simple-mfd";
|
||||
reg = <0x18800 0x100>, <0x18C00 0x20>;
|
||||
gpiosb: gpiosb {
|
||||
/* MPP2[23:0] */
|
||||
gpiosb: gpio {
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pinctrl_sb 0 0 30>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts =
|
||||
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@ -218,30 +318,92 @@
|
||||
function = "sdio";
|
||||
};
|
||||
|
||||
pcie_pins: pcie-pins {
|
||||
groups = "pcie1";
|
||||
pcie_reset_pins: pcie-reset-pins {
|
||||
groups = "pcie1"; /* this actually controls "pcie1_reset" */
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
pcie_clkreq_pins: pcie-clkreq-pins {
|
||||
groups = "pcie1_clkreq";
|
||||
function = "pcie";
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@30000 {
|
||||
compatible = "marvell,armada-3700-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sb_periph_clk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio: mdio@32004 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x32004 0x4>;
|
||||
};
|
||||
|
||||
eth1: ethernet@40000 {
|
||||
compatible = "marvell,armada-3700-neta";
|
||||
reg = <0x40000 0x4000>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sb_periph_clk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3: usb@58000 {
|
||||
compatible = "marvell,armada3700-xhci",
|
||||
"generic-xhci";
|
||||
reg = <0x58000 0x4000>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,usb-misc-reg = <&usb32_syscon>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sb_periph_clk 12>;
|
||||
phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
|
||||
phy-names = "usb3-phy", "usb2-utmi-otg-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_utmi_otg_phy: phy@5d000 {
|
||||
compatible = "marvell,a3700-utmi-otg-phy";
|
||||
reg = <0x5d000 0x800>;
|
||||
marvell,usb-misc-reg = <&usb32_syscon>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usb32_syscon: system-controller@5d800 {
|
||||
compatible = "marvell,armada-3700-usb2-host-device-misc",
|
||||
"syscon";
|
||||
reg = <0x5d800 0x800>;
|
||||
};
|
||||
|
||||
usb2: usb@5e000 {
|
||||
compatible = "marvell,armada-3700-ehci";
|
||||
reg = <0x5e000 0x450>;
|
||||
reg = <0x5e000 0x1000>;
|
||||
marvell,usb-misc-reg = <&usb2_syscon>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&usb2_utmi_host_phy>;
|
||||
phy-names = "usb2-utmi-host-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_utmi_host_phy: phy@5f000 {
|
||||
compatible = "marvell,a3700-utmi-host-phy";
|
||||
reg = <0x5f000 0x800>;
|
||||
marvell,usb-misc-reg = <&usb2_syscon>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usb2_syscon: system-controller@5f800 {
|
||||
compatible = "marvell,armada-3700-usb2-host-misc",
|
||||
"syscon";
|
||||
reg = <0x5f800 0x800>;
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,armada-3700-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
reg = <0x60900 0x100>,
|
||||
<0x60b00 0x100>;
|
||||
|
||||
xor10 {
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -251,26 +413,56 @@
|
||||
};
|
||||
};
|
||||
|
||||
crypto: crypto@90000 {
|
||||
compatible = "inside-secure,safexcel-eip97ies";
|
||||
reg = <0x90000 0x20000>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mem", "ring0", "ring1",
|
||||
"ring2", "ring3", "eip";
|
||||
clocks = <&nb_periph_clk 15>;
|
||||
};
|
||||
|
||||
rwtm: mailbox@b0000 {
|
||||
compatible = "marvell,armada-3700-rwtm-mailbox";
|
||||
reg = <0xb0000 0x100>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
sdhci1: sdhci@d0000 {
|
||||
compatible = "marvell,armada-3700-sdhci",
|
||||
"marvell,sdhci-xenon";
|
||||
reg = <0xd0000 0x300
|
||||
0x1e808 0x4>;
|
||||
"marvell,sdhci-xenon";
|
||||
reg = <0xd0000 0x300>,
|
||||
<0x1e808 0x4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&nb_periph_clk 0>;
|
||||
clock-names = "core";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci0: sdhci@d8000 {
|
||||
compatible = "marvell,armada-3700-sdhci",
|
||||
"marvell,sdhci-xenon";
|
||||
reg = <0xd8000 0x300
|
||||
0x17808 0x4>;
|
||||
"marvell,sdhci-xenon";
|
||||
reg = <0xd8000 0x300>,
|
||||
<0x17808 0x4>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&nb_periph_clk 0>;
|
||||
clock-names = "core";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@e0000 {
|
||||
compatible = "marvell,armada-3700-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
reg = <0xe0000 0x178>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&nb_periph_clk 1>;
|
||||
phys = <&comphy2 0>;
|
||||
phy-names = "sata-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -279,72 +471,26 @@
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x1d00000 0x10000>, /* GICD */
|
||||
<0x1d40000 0x40000>; /* GICR */
|
||||
};
|
||||
|
||||
eth0: neta@30000 {
|
||||
compatible = "marvell,armada-3700-neta";
|
||||
reg = <0x30000 0x20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth1: neta@40000 {
|
||||
compatible = "marvell,armada-3700-neta";
|
||||
reg = <0x40000 0x20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,armada-3700-i2c";
|
||||
reg = <0x11000 0x100>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-3700-spi";
|
||||
reg = <0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
clocks = <&nb_periph_clk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
comphy: comphy@18300 {
|
||||
compatible = "marvell,comphy-a3700";
|
||||
reg = <0x18300 0x28>,
|
||||
<0x1f300 0x3d000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
comphy0: phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
comphy1: phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
comphy2: phy@2 {
|
||||
reg = <2>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
<0x1d40000 0x40000>, /* GICR */
|
||||
<0x1d80000 0x2000>, /* GICC */
|
||||
<0x1d90000 0x2000>, /* GICH */
|
||||
<0x1da0000 0x20000>; /* GICV */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0: pcie@d0070000 {
|
||||
compatible = "marvell,armada-3700-pcie";
|
||||
device_type = "pci";
|
||||
status = "disabled";
|
||||
reg = <0 0xd0070000 0 0x20000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <1>;
|
||||
status = "disabled";
|
||||
|
||||
bus-range = <0 0xff>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
msi-parent = <&pcie0>;
|
||||
msi-controller;
|
||||
/*
|
||||
* The 128 MiB address range [0xe8000000-0xf0000000] is
|
||||
* dedicated for PCIe and can be assigned to 8 windows
|
||||
@ -352,10 +498,27 @@
|
||||
* IO at the end and the remaining seven windows
|
||||
* (totaling 127 MiB) for MEM.
|
||||
*/
|
||||
ranges = <0x82000000 0 0xe8000000
|
||||
0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
|
||||
0x81000000 0 0xeff00000
|
||||
0 0xeff00000 0 0x100000>; /* Port 0 IO*/
|
||||
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
|
||||
0x81000000 0 0xeff00000 0 0xeff00000 0 0x00100000>; /* Port 0 IO*/
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
<0 0 0 3 &pcie_intc 2>,
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
max-link-speed = <2>;
|
||||
phys = <&comphy1 0>;
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
armada-3700-rwtm {
|
||||
compatible = "marvell,armada-3700-rwtm-firmware";
|
||||
mboxes = <&rwtm 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
16
include/dt-bindings/bus/moxtet.h
Normal file
16
include/dt-bindings/bus/moxtet.h
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Constant for device tree bindings for Turris Mox module configuration bus
|
||||
*
|
||||
* Copyright (C) 2019 Marek Behún <kabel@kernel.org>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_BUS_MOXTET_H
|
||||
#define _DT_BINDINGS_BUS_MOXTET_H
|
||||
|
||||
#define MOXTET_IRQ_PCI 0
|
||||
#define MOXTET_IRQ_USB3 4
|
||||
#define MOXTET_IRQ_PERIDOT(n) (8 + (n))
|
||||
#define MOXTET_IRQ_TOPAZ 12
|
||||
|
||||
#endif /* _DT_BINDINGS_BUS_MOXTET_H */
|
||||
Loading…
Reference in New Issue
Block a user