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ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx

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This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.

Lot's of other macros are good candidates to be consolidated this way
in the future.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-10-21 08:12:41 +02:00
parent 770c7af580
commit 087dfdb79b
14 changed files with 113 additions and 202 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
board/amcc/taishan/showinfo.c
View File

@ -33,25 +33,25 @@ void show_reset_reg(void)
/* read clock regsiter */
printf("===== Display reset and initialize register Start =========\n");
mfclk(clk_pllc,reg);
mfcpr(clk_pllc,reg);
printf("cpr_pllc = %#010x\n",reg);
mfclk(clk_plld,reg);
mfcpr(clk_plld,reg);
printf("cpr_plld = %#010x\n",reg);
mfclk(clk_primad,reg);
mfcpr(clk_primad,reg);
printf("cpr_primad = %#010x\n",reg);
mfclk(clk_primbd,reg);
mfcpr(clk_primbd,reg);
printf("cpr_primbd = %#010x\n",reg);
mfclk(clk_opbd,reg);
mfcpr(clk_opbd,reg);
printf("cpr_opbd = %#010x\n",reg);
mfclk(clk_perd,reg);
mfcpr(clk_perd,reg);
printf("cpr_perd = %#010x\n",reg);
mfclk(clk_mald,reg);
mfcpr(clk_mald,reg);
printf("cpr_mald = %#010x\n",reg);
/* read sdr register */

6
board/amcc/yucca/yucca.c
View File

@ -36,13 +36,7 @@
DECLARE_GLOBAL_DATA_PTR;
void fpga_init (void);
void get_sys_info(PPC440_SYS_INFO *board_cfg );
int compare_to_true(char *str );
char *remove_l_w_space(char *in_str );
char *remove_t_w_space(char *in_str );
int get_console_port(void);
#define DEBUG_ENV
#ifdef DEBUG_ENV

2
board/lwmon5/sdram.c
View File

@ -71,7 +71,7 @@ static u32 is_ecc_enabled(void)
void board_add_ram_info(int use_default)
{
PPC440_SYS_INFO board_cfg;
PPC4xx_SYS_INFO board_cfg;
u32 val;
if (is_ecc_enabled())

2
board/mpl/common/common_util.c
View File

@ -587,7 +587,7 @@ extern int get_boot_mode(void);
void video_get_info_str (int line_number, char *info)
{
/* init video info strings for graphic console */
PPC405_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
char rev;
int i,boot;
unsigned long pvr;

2
board/netstal/hcu5/sdram.c
View File

@ -72,7 +72,7 @@ void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void board_add_ram_info(int use_default)
{
PPC440_SYS_INFO board_cfg;
PPC4xx_SYS_INFO board_cfg;
u32 val;
mfsdram(DDR0_22, val);
val &= DDR0_22_CTRL_RAW_MASK;

2
board/xilinx/ml300/ml300.c
View File

@ -108,7 +108,7 @@ ulong
get_PCI_freq(void)
{
ulong val;
PPC405_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
get_sys_info(&sys_info);
val = sys_info.freqPCI;

2
cpu/ppc4xx/40x_spd_sdram.c
View File

@ -148,7 +148,7 @@ long int spd_sdram(int(read_spd)(uint addr))
int t_rc;
int min_cas;
PPC405_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
unsigned long bus_period_x_10;
/*

6
cpu/ppc4xx/44x_spd_ddr.c
View File

@ -645,7 +645,7 @@ static void program_rtr(unsigned long *dimm_populated,
unsigned char refresh_rate_type;
unsigned long refresh_interval;
unsigned long sdram_rtr;
PPC440_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
/*
* get the board info
@ -721,7 +721,7 @@ static void program_tr0(unsigned long *dimm_populated,
unsigned long tcyc_2_0_ns_x_10;
unsigned long tcyc_reg;
unsigned long bus_period_x_10;
PPC440_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
unsigned long residue;
/*
@ -1065,7 +1065,7 @@ static void program_tr1(void)
unsigned char window_found;
unsigned char fail_found;
unsigned char pass_found;
PPC440_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
/*
* get the board info

27
cpu/ppc4xx/44x_spd_ddr2.c
View File

@ -623,7 +623,7 @@ static void get_spd_info(unsigned long *dimm_populated,
void board_add_ram_info(int use_default)
{
PPC440_SYS_INFO board_cfg;
PPC4xx_SYS_INFO board_cfg;
u32 val;
if (is_ecc_enabled())
@ -741,7 +741,7 @@ static void check_frequency(unsigned long *dimm_populated,
unsigned long calc_cycle_time;
unsigned long sdram_freq;
unsigned long sdr_ddrpll;
PPC440_SYS_INFO board_cfg;
PPC4xx_SYS_INFO board_cfg;
/*------------------------------------------------------------------
* Get the board configuration info.
@ -1353,7 +1353,7 @@ static void program_mode(unsigned long *dimm_populated,
unsigned long max_4_0_tcyc_ns_x_100;
unsigned long max_5_0_tcyc_ns_x_100;
unsigned long cycle_time_ns_x_100[3];
PPC440_SYS_INFO board_cfg;
PPC4xx_SYS_INFO board_cfg;
unsigned char cas_2_0_available;
unsigned char cas_2_5_available;
unsigned char cas_3_0_available;
@ -1640,7 +1640,7 @@ static void program_rtr(unsigned long *dimm_populated,
unsigned char *iic0_dimm_addr,
unsigned long num_dimm_banks)
{
PPC440_SYS_INFO board_cfg;
PPC4xx_SYS_INFO board_cfg;
unsigned long max_refresh_rate;
unsigned long dimm_num;
unsigned long refresh_rate_type;
@ -1737,7 +1737,7 @@ static void program_tr(unsigned long *dimm_populated,
unsigned long sdram_freq;
unsigned long sdr_ddrpll;
PPC440_SYS_INFO board_cfg;
PPC4xx_SYS_INFO board_cfg;
/*------------------------------------------------------------------
* Get the board configuration info.
@ -2048,14 +2048,10 @@ static void program_bxcf(unsigned long *dimm_populated,
/*------------------------------------------------------------------
* Set the BxCF regs. First, wipe out the bank config registers.
*-----------------------------------------------------------------*/
mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
mtdcr(SDRAMC_CFGDATA, 0x00000000);
mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
mtdcr(SDRAMC_CFGDATA, 0x00000000);
mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
mtdcr(SDRAMC_CFGDATA, 0x00000000);
mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
mtdcr(SDRAMC_CFGDATA, 0x00000000);
mtsdram(SDRAM_MB0CF, 0x00000000);
mtsdram(SDRAM_MB1CF, 0x00000000);
mtsdram(SDRAM_MB2CF, 0x00000000);
mtsdram(SDRAM_MB3CF, 0x00000000);
mode = SDRAM_BXCF_M_BE_ENABLE;
@ -2107,8 +2103,9 @@ static void program_bxcf(unsigned long *dimm_populated,
bank_0_populated = 1;
for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
mtdcr(SDRAMC_CFGDATA, mode);
mtsdram(SDRAM_MB0CF +
((dimm_num + bank_0_populated + ind_rank) << 2),
mode);
}
}
}

30
cpu/ppc4xx/speed.c
View File

@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_405GP) || defined(CONFIG_405CR)
void get_sys_info (PPC405_SYS_INFO * sysInfo)
void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
{
unsigned long pllmr;
unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
@ -173,7 +173,7 @@ ulong get_OPB_freq (void)
{
ulong val = 0;
PPC405_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllOpbDiv;
@ -189,7 +189,7 @@ ulong get_OPB_freq (void)
ulong get_PCI_freq (void)
{
ulong val;
PPC405_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllPciDiv;
@ -216,7 +216,7 @@ void get_sys_info (sys_info_t *sysInfo)
*/
/* Decode CPR0_PLLD0 for divisors */
mfclk(clk_plld, reg);
mfcpr(clk_plld, reg);
temp = (reg & PLLD_FWDVA_MASK) >> 16;
sysInfo->pllFwdDivA = temp ? temp : 16;
temp = (reg & PLLD_FWDVB_MASK) >> 8;
@ -225,19 +225,19 @@ void get_sys_info (sys_info_t *sysInfo)
sysInfo->pllFbkDiv = temp ? temp : 32;
lfdiv = reg & PLLD_LFBDV_MASK;
mfclk(clk_opbd, reg);
mfcpr(clk_opbd, reg);
temp = (reg & OPBDDV_MASK) >> 24;
sysInfo->pllOpbDiv = temp ? temp : 4;
mfclk(clk_perd, reg);
mfcpr(clk_perd, reg);
temp = (reg & PERDV_MASK) >> 24;
sysInfo->pllExtBusDiv = temp ? temp : 8;
mfclk(clk_primbd, reg);
mfcpr(clk_primbd, reg);
temp = (reg & PRBDV_MASK) >> 24;
prbdv0 = temp ? temp : 8;
mfclk(clk_spcid, reg);
mfcpr(clk_spcid, reg);
temp = (reg & SPCID_MASK) >> 24;
sysInfo->pllPciDiv = temp ? temp : 4;
@ -246,7 +246,7 @@ void get_sys_info (sys_info_t *sysInfo)
temp = (reg & PLLSYS0_SEL_MASK) >> 27;
if (temp == 0) { /* PLL output */
/* Figure which pll to use */
mfclk(clk_pllc, reg);
mfcpr(clk_pllc, reg);
temp = (reg & PLLC_SRC_MASK) >> 29;
if (!temp) /* PLLOUTA */
m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
@ -650,7 +650,7 @@ void get_sys_info (sys_info_t * sysInfo) {
}
#elif defined(CONFIG_405EP)
void get_sys_info (PPC405_SYS_INFO * sysInfo)
void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
{
unsigned long pllmr0;
unsigned long pllmr1;
@ -746,7 +746,7 @@ ulong get_OPB_freq (void)
{
ulong val = 0;
PPC405_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllOpbDiv;
@ -762,7 +762,7 @@ ulong get_OPB_freq (void)
ulong get_PCI_freq (void)
{
ulong val;
PPC405_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllPciDiv;
@ -770,7 +770,7 @@ ulong get_PCI_freq (void)
}
#elif defined(CONFIG_405EZ)
void get_sys_info (PPC405_SYS_INFO * sysInfo)
void get_sys_info (PPC4xx_SYS_INFO * sysInfo)
{
unsigned long cpr_plld;
unsigned long cpr_pllc;
@ -871,7 +871,7 @@ ulong get_OPB_freq (void)
{
ulong val = 0;
PPC405_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv;
@ -1032,7 +1032,7 @@ ulong get_OPB_freq (void)
{
ulong val = 0;
PPC405_SYS_INFO sys_info;
PPC4xx_SYS_INFO sys_info;
get_sys_info (&sys_info);
val = sys_info.freqPLB / sys_info.pllOpbDiv;

4
include/common.h
View File

@ -513,15 +513,13 @@ void get_sys_info ( sys_info_t * );
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
typedef PPC440_SYS_INFO sys_info_t;
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
unsigned long determine_pci_clock_per(void);
int ppc440spe_revB(void);
# endif
# else
typedef PPC405_SYS_INFO sys_info_t;
# endif
typedef PPC4xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
#endif

58
include/ppc405.h
View File

@ -344,9 +344,6 @@
/******************************************************************************
* SDRAM Controller
******************************************************************************/
#define SDRAM_DCR_BASE 0x10
#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
/* values for memcfga register - indirect addressing of these regs */
#ifndef CONFIG_405EP
#define mem_besra 0x00 /* bus error syndrome reg a */
@ -412,9 +409,6 @@
/******************************************************************************
* Extrnal Bus Controller
******************************************************************************/
#define EBC_DCR_BASE 0x12
#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
/* values for ebccfga register - indirect addressing of these regs */
#define pb0cr 0x00 /* periph bank 0 config reg */
#define pb1cr 0x01 /* periph bank 1 config reg */
@ -1574,56 +1568,4 @@
#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
#endif
/******************************************************************************
* SDR Registers
******************************************************************************/
#define SDR_DCR_BASE 0x0E
#define sdrcfga (SDR_DCR_BASE+0x0)
#define sdrcfgd (SDR_DCR_BASE+0x1)
#define CPR0_DCR_BASE 0x0C
#define cprcfga (CPR0_DCR_BASE+0x0)
#define cprcfgd (CPR0_DCR_BASE+0x1)
#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
#ifndef __ASSEMBLY__
typedef struct
{
unsigned long pllFwdDiv;
unsigned long pllFwdDivB;
unsigned long pllFbkDiv;
unsigned long pllPlbDiv;
unsigned long pllPciDiv;
unsigned long pllExtBusDiv;
unsigned long pllOpbDiv;
unsigned long freqVCOMhz; /* in MHz */
unsigned long freqProcessor;
unsigned long freqPLB;
unsigned long freqPCI;
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
unsigned long pciClkSync; /* PCI clock is synchronous */
unsigned long freqVCOHz;
unsigned long freqOPB;
unsigned long freqEBC;
unsigned long freqDDR;
} PPC405_SYS_INFO;
#endif /* _ASMLANGUAGE */
#define RESET_VECTOR 0xfffffffc
#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
line aligned data. */
#endif /* __PPC405_H__ */

87
include/ppc440.h
View File

@ -123,10 +123,6 @@
/*-----------------------------------------------------------------------------
| Clocking Controller
+----------------------------------------------------------------------------*/
#define CLOCKING_DCR_BASE 0x0c
#define clkcfga (CLOCKING_DCR_BASE+0x0)
#define clkcfgd (CLOCKING_DCR_BASE+0x1)
/* values for clkcfga register - indirect addressing of these regs */
#define clk_clkukpd 0x0020
#define clk_pllc 0x0040
@ -140,9 +136,6 @@
#define clk_icfg 0x0140
/* 440gx sdr register definations */
#define SDR_DCR_BASE 0x0e
#define sdrcfga (SDR_DCR_BASE+0x0)
#define sdrcfgd (SDR_DCR_BASE+0x1)
#define sdr_sdstp0 0x0020 /* */
#define sdr_sdstp1 0x0021 /* */
#define SDR_PINSTP 0x0040
@ -242,10 +235,6 @@
/*-----------------------------------------------------------------------------
| SDRAM Controller
+----------------------------------------------------------------------------*/
#define SDRAM_DCR_BASE 0x10
#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
/* values for memcfga register - indirect addressing of these regs */
#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
@ -331,9 +320,6 @@
#define sdr_sdstp6 0x4005
#define sdr_sdstp7 0x4007
#define SDR0_CFGADDR 0x00E
#define SDR0_CFGDATA 0x00F
/******************************************************************************
* PCI express defines
******************************************************************************/
@ -480,10 +466,6 @@
/*----------------------------------------------------------------------------+
| Memory controller defines
+----------------------------------------------------------------------------*/
#define SDRAMC_DCR_BASE 0x010
#define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */
#define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */
/* A REVOIR versus specs 4 bank - SG*/
#define SDRAM_MCSTAT 0x14 /* memory controller status */
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
@ -834,9 +816,6 @@
/*-----------------------------------------------------------------------------
| External Bus Controller
+----------------------------------------------------------------------------*/
#define EBC_DCR_BASE 0x12
#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
/* values for ebccfga register - indirect addressing of these regs */
#define pb0cr 0x00 /* periph bank 0 config reg */
#define pb1cr 0x01 /* periph bank 1 config reg */
@ -2207,9 +2186,6 @@
#define SDR0_CP440_NTO1_NTO1 0x00000002
#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
#define SDR0_CFGADDR 0x00E /*already defined line 277 */
#define SDR0_CFGDATA 0x00F
#define SDR0_SDSTP0 0x0020
#define SDR0_SDSTP0_ENG_MASK 0x80000000
@ -3289,71 +3265,8 @@
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
#endif
/*
* Macros for accessing the indirect EBC registers
*/
#define mtebc(reg, data) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } while (0)
#define mfebc(reg, data) do { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } while (0)
/*
* Macros for accessing the indirect SDRAM controller registers
*/
#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0)
#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0)
/*
* Macros for accessing the indirect clocking controller registers
*/
#define mtclk(reg, data) do { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } while (0)
#define mfclk(reg, data) do { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } while (0)
/*
* Macros for accessing the sdr controller registers
*/
#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0)
#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0)
/*
* All 44x except 440GP have CPR registers (indirect DCR)
*/
#if !defined(CONFIG_440GP)
#define CPR0_CFGADDR 0x00C
#define CPR0_CFGDATA 0x00D
#define mtcpr(reg, data) do { \
mtdcr(CPR0_CFGADDR, reg); \
mtdcr(CPR0_CFGDATA, data); \
} while (0)
#define mfcpr(reg, data) do { \
mtdcr(CPR0_CFGADDR, reg); \
data = mfdcr(CPR0_CFGDATA); \
} while (0)
#endif
#ifndef __ASSEMBLY__
typedef struct {
unsigned long pllFwdDivA;
unsigned long pllFwdDivB;
unsigned long pllFbkDiv;
unsigned long pllOpbDiv;
unsigned long pllPciDiv;
unsigned long pllExtBusDiv;
unsigned long freqVCOMhz; /* in MHz */
unsigned long freqProcessor;
unsigned long freqTmrClk;
unsigned long freqPLB;
unsigned long freqOPB;
unsigned long freqEBC;
unsigned long freqPCI;
#ifdef CONFIG_440SPE
unsigned long freqDDR;
#endif
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
unsigned long pciClkSync; /* PCI clock is synchronous */
} PPC440_SYS_INFO;
static inline u32 get_mcsr(void)
{
u32 val;

73
include/ppc4xx.h
View File

@ -22,13 +22,80 @@
#ifndef __PPC4XX_H__
#define __PPC4XX_H__
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
#if defined(CONFIG_440)
#include <ppc440.h>
#else
#include <ppc405.h>
#endif
/*
* Common stuff for 4xx (405 and 440)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
#define RESET_VECTOR 0xfffffffc
#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
line aligned data. */
#define CPR0_DCR_BASE 0x0C
#define cprcfga (CPR0_DCR_BASE+0x0)
#define cprcfgd (CPR0_DCR_BASE+0x1)
#define SDR_DCR_BASE 0x0E
#define sdrcfga (SDR_DCR_BASE+0x0)
#define sdrcfgd (SDR_DCR_BASE+0x1)
#define SDRAM_DCR_BASE 0x10
#define memcfga (SDRAM_DCR_BASE+0x0)
#define memcfgd (SDRAM_DCR_BASE+0x1)
#define EBC_DCR_BASE 0x12
#define ebccfga (EBC_DCR_BASE+0x0)
#define ebccfgd (EBC_DCR_BASE+0x1)
/*
* Macros for indirect DCR access
*/
#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
#ifndef __ASSEMBLY__
typedef struct
{
unsigned long freqDDR;
unsigned long freqEBC;
unsigned long freqOPB;
unsigned long freqPCI;
unsigned long freqPLB;
unsigned long freqTmrClk;
unsigned long freqUART;
unsigned long freqProcessor;
unsigned long freqVCOHz;
unsigned long freqVCOMhz; /* in MHz */
unsigned long pciClkSync; /* PCI clock is synchronous */
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
unsigned long pllExtBusDiv;
unsigned long pllFbkDiv;
unsigned long pllFwdDiv;
unsigned long pllFwdDivA;
unsigned long pllFwdDivB;
unsigned long pllOpbDiv;
unsigned long pllPciDiv;
unsigned long pllPlbDiv;
} PPC4xx_SYS_INFO;
#endif /* __ASSEMBLY__ */
#endif /* __PPC4XX_H__ */