Merge branch 'master' of git://www.denx.de/git/u-boot-tq-group
This commit is contained in:
Wolfgang Denk
commit
07dd6eb040
@ -354,6 +354,8 @@ long int initdram (int board_type)
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udelay (10000);
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#ifdef CONFIG_CAN_DRIVER
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/* UPM initialization for CAN @ CLKOUT <= 66 MHz */
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/* Initialize OR3 / BR3 */
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memctl->memc_or3 = CFG_OR3_CAN;
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memctl->memc_br3 = CFG_BR3_CAN;
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@ -362,7 +364,7 @@ long int initdram (int board_type)
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memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
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/* Initialize UPMB for CAN: single read */
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memctl->memc_mdr = 0xFFFFC004;
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memctl->memc_mdr = 0xFFFFCC04;
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memctl->memc_mcr = 0x0100 | UPMB;
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memctl->memc_mdr = 0x0FFFD004;
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@ -374,23 +376,23 @@ long int initdram (int board_type)
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memctl->memc_mdr = 0x3FFFC004;
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memctl->memc_mcr = 0x0103 | UPMB;
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memctl->memc_mdr = 0xFFFFDC05;
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memctl->memc_mdr = 0xFFFFDC07;
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memctl->memc_mcr = 0x0104 | UPMB;
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/* Initialize UPMB for CAN: single write */
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memctl->memc_mdr = 0xFFFCC004;
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memctl->memc_mdr = 0xFFFCCC04;
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memctl->memc_mcr = 0x0118 | UPMB;
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memctl->memc_mdr = 0xCFFCD004;
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memctl->memc_mdr = 0xCFFCDC04;
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memctl->memc_mcr = 0x0119 | UPMB;
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memctl->memc_mdr = 0x0FFCC000;
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memctl->memc_mdr = 0x3FFCC000;
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memctl->memc_mcr = 0x011A | UPMB;
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memctl->memc_mdr = 0x7FFCC004;
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memctl->memc_mdr = 0xFFFCC004;
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memctl->memc_mcr = 0x011B | UPMB;
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memctl->memc_mdr = 0xFFFDCC05;
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memctl->memc_mdr = 0xFFFDC405;
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memctl->memc_mcr = 0x011C | UPMB;
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#endif /* CONFIG_CAN_DRIVER */
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@ -69,9 +69,14 @@
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_8xx\0" \
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"bootfile=/tftpboot/TQM860M/uImage\0" \
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"fdt_addr=40080000\0" \
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"kernel_addr=400A0000\0" \
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"fdt_addr=400C0000\0" \
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"kernel_addr=40100000\0" \
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"ramdisk_addr=40280000\0" \
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"load=tftp 200000 ${u-boot}\0" \
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"update=protect off 40000000 +${filesize};" \
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"erase 40000000 +${filesize};" \
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"cp.b 200000 40000000 ${filesize};" \
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"protect on 40000000 +${filesize}\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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@ -172,7 +177,7 @@
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#define CFG_FLASH_BASE 0x40000000
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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@ -193,7 +198,7 @@
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
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@ -81,9 +81,14 @@
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_8xx\0" \
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"bootfile=/tftpboot/TQM866M/uImage\0" \
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"fdt_addr=40080000\0" \
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"kernel_addr=400A0000\0" \
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"fdt_addr=400C0000\0" \
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"kernel_addr=40100000\0" \
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"ramdisk_addr=40280000\0" \
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"load=tftp 200000 ${u-boot}\0" \
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"update=protect off 40000000 +${filesize};" \
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"erase 40000000 +${filesize};" \
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"cp.b 200000 40000000 ${filesize};" \
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"protect on 40000000 +${filesize}\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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@ -215,7 +220,7 @@
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#define CFG_FLASH_BASE 0x40000000
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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@ -236,7 +241,7 @@
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
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@ -421,26 +426,30 @@
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#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
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/*
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* Memory Periodic Timer Prescaler
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* Periodic timer for refresh, start with refresh rate for 40 MHz clock
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* (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
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* Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
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*
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* CPUclock(MHz) * 31.2
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* CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0
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* 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
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*
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* CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us
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* CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us
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* CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us
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* CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us
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*
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* Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
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* be met also in the default configuration, i.e. if environment variable
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* 'cpuclk' is not set.
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*/
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#define CFG_MAMR_PTA 39
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#define CFG_MAMR_PTA 97
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/*
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* For 16 MBit, refresh rates could be 31.3 us
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* (= 64 ms / 2K = 125 / quad bursts).
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* For a simpler initialization, 15.6 us is used instead.
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*
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* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
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* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
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* Memory Periodic Timer Prescaler Register (MPTPR) values.
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*/
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
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#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
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/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16
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/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
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#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8
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/*
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* MAMR settings for SDRAM
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