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sunxi: Update DRAM clock for Olimex A20 boards

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Originally dram clock was set to 480MHz, but this behaves
unstable. To improve stability the clock is reduced to 384MHz

Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Stefan Mavrodiev 2016-10-29 14:34:07 +02:00 committed by Hans de Goede
parent 6301e80ccf
commit 06de070130
1 changed files with 1 additions and 1 deletions
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2
configs/A20-Olimex-SOM-EVB_defconfig
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@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y CONFIG_ARCH_SUNXI=y
CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y
CONFIG_MACH_SUN7I=y CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480 CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC3_CD_PIN="PH0" CONFIG_MMC3_CD_PIN="PH0"
CONFIG_MMC3_PINS="PH" CONFIG_MMC3_PINS="PH"