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Merge git://git.denx.de/u-boot-marvell

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- Misc dts files sync'ed with Linux version (Chris)
- Orion watchdog fix (Chris)
- kwbimage changed to also support Marvell bin_hdr binary (Chris)
- Add DM support to enable CONFIG_BLK for sata_mv (Stefan)
- Enable BLK on multiple platforms (Stefan)
- Misc minor fixes to AXP theadorable board (Stefan)
- Correct logic for DM_SCSI + unconverted drivers check (stefan)
- Misc changes to kirkwood to enable DM_USB here (Chris)
- Change ahci_mvebu to enable usage on A38x (Baruch)
- Update the kirkwood entry in git-mailrc (Baruch)
- Misc minor improvements (turris, documentation) (Baruch)
- Enhance sata_mv to support Kirkwood as well (Michael)
- Add wdt command (Michael)
- Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG
  board support (Chris)
This commit is contained in:
Tom Rini 2019-04-12 12:34:44 -04:00
commit 066cc7c6cf
83 changed files with 2102 additions and 1010 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
Makefile
View File

@ -945,11 +945,22 @@ ifneq ($(CONFIG_DM_USB)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
@echo >&2 "===================================================="
endif
endif
ifeq ($(CONFIG_LIBATA)$(CONFIG_MVSATA_IDE),y)
ifneq ($(CONFIG_DM_SCSI),y)
ifeq ($(CONFIG_MVSATA_IDE),y)
@echo >&2 "===================== WARNING ======================"
@echo >&2 "This board does not use CONFIG_DM_SCSI. Please update"
@echo >&2 "the storage controller to use CONFIG_DM_SCSI before the v2019.07 release."
@echo >&2 "This board does use CONFIG_MVSATA_IDE which is not"
@echo >&2 "ported to driver-model (DM) yet. Please update the storage"
@echo >&2 "controller driver to use CONFIG_AHCI before the v2019.07"
@echo >&2 "release."
@echo >&2 "Failure to update by the deadline may result in board removal."
@echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
@echo >&2 "===================================================="
endif
ifeq ($(CONFIG_LIBATA),y)
ifneq ($(CONFIG_AHCI),y)
@echo >&2 "===================== WARNING ======================"
@echo >&2 "This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
@echo >&2 "enabled. Please update the storage controller driver to use"
@echo >&2 "CONFIG_AHCI before the v2019.07 release."
@echo >&2 "Failure to update by the deadline may result in board removal."
@echo >&2 "See doc/driver-model/MIGRATION.txt for more info."
@echo >&2 "===================================================="

5
arch/arm/dts/Makefile
View File

@ -138,7 +138,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-388-clearfog.dtb \
armada-388-gp.dtb \
armada-388-helios4.dtb \
armada-385-amc.dtb \
armada-385-db-88f6820-amc.dtb \
armada-385-turris-omnia.dtb \
armada-7040-db.dtb \
armada-7040-db-nand.dtb \
@ -151,7 +151,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-xp-theadorable.dtb \
armada-38x-controlcenterdc.dtb \
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb
armada-385-atl-x530DP.dtb \
armada-xp-db-xc3-24g4xg.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \

133
arch/arm/dts/armada-370-xp.dtsi
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
*
@ -8,50 +9,10 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* This file contains the definitions that are common to the Armada
* 370 and Armada XP SoC.
*/
/include/ "skeleton64.dtsi"
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
@ -86,7 +47,7 @@
pcie-mem-aperture = <0xf8000000 0x7e00000>;
pcie-io-aperture = <0xffe00000 0x100000>;
devbus-bootcs {
devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@ -96,7 +57,7 @@
status = "disabled";
};
devbus-cs0 {
devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@ -106,7 +67,7 @@
status = "disabled";
};
devbus-cs1 {
devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@ -116,7 +77,7 @@
status = "disabled";
};
devbus-cs2 {
devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@ -126,7 +87,7 @@
status = "disabled";
};
devbus-cs3 {
devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@ -141,34 +102,13 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
u-boot,dm-pre-reloc;
rtc@10300 {
rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <50>;
};
spi0: spi@10600 {
reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
#address-cells = <1>;
@ -235,33 +175,38 @@
msi-controller;
};
coherency-fabric@20200 {
coherencyfab: coherency-fabric@20200 {
compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21010 0x1c>;
};
timer@20300 {
timer: timer@20300 {
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
};
watchdog@20300 {
watchdog: watchdog@20300 {
reg = <0x20300 0x34>, <0x20704 0x4>;
};
pmsu@22000 {
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x8>;
};
pmsu: pmsu@22000 {
compatible = "marvell,armada-370-pmsu";
reg = <0x22000 0x1000>;
};
usb@50000 {
usb0: usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};
usb@51000 {
usb1: usb@51000 {
compatible = "marvell,orion-ehci";
reg = <0x51000 0x500>;
interrupts = <46>;
@ -275,7 +220,7 @@
status = "disabled";
};
mdio: mdio {
mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
@ -290,7 +235,7 @@
status = "disabled";
};
sata@a0000 {
sata: sata@a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <55>;
@ -309,7 +254,7 @@
status = "disabled";
};
mvsdio@d4000 {
sdio: mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <54>;
@ -321,6 +266,42 @@
status = "disabled";
};
};
spi0: spi@10600 {
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
<MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
<MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
<MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
<MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
<MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
<MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
<MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
<MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
<MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
<MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
<MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
<MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
<MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
<MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
};
clocks {

166
arch/arm/dts/armada-385-amc.dts
View File

@ -1,166 +0,0 @@
/*
* Device Tree file for Marvell Armada 385 development board
* (DB-88F6820-AMC)
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 385 AMC";
compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth0;
ethernet1 = &eth2;
i2c0 = &i2c0;
spi1 = &spi1;
};
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
i2c@11000 {
clock-frequency = <100000>;
u-boot,i2c-slave-addr = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
serial@12000 {
/*
* Exported on the micro USB connector CON16
* through an FTDI
*/
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
u-boot,dm-pre-reloc;
};
ethernet@34000 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
usb@58000 {
status = "okay";
};
ethernet@70000 {
pinctrl-names = "default";
/*
* The Reference Clock 0 is used to provide a
* clock to the PHY
*/
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
mdio@72004 {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@0 {
reg = <0>;
};
};
flash@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
};
pcie {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
};
};
&refclk {
clock-frequency = <20000000>;
};

4
arch/arm/dts/armada-385-atl-x530-u-boot.dtsi
View File

@ -11,3 +11,7 @@
&uart0 {
u-boot,dm-pre-reloc;
};
&watchdog {
u-boot,dm-pre-reloc;
};

146
arch/arm/dts/armada-385-db-88f6820-amc.dts Normal file
View File

@ -0,0 +1,146 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Marvell Armada 385 AMC board
* (DB-88F6820-AMC)
*
* Copyright (C) 2017 Allied Telesis Labs
*/
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 385 AMC";
compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth0;
ethernet1 = &eth2;
i2c0 = &i2c0;
spi1 = &spi1;
};
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
};
};
&i2c0 {
u-boot,i2c-slave-addr = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&uart0 {
/*
* Exported on the micro USB connector CON3
* through an FTDI
*/
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
u-boot,dm-pre-reloc;
};
&eth0 {
pinctrl-names = "default";
/*
* The Reference Clock 0 is used to provide a
* clock to the PHY
*/
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
&eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
&usb0 {
status = "okay";
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@0 {
reg = <0>;
};
};
&nand_controller {
status = "okay";
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
&pciec {
status = "okay";
};
&pcie1 {
/* Port 0, Lane 0 */
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000000 0x00100000>;
label = "u-boot";
};
partition@100000 {
reg = <0x00100000 0x00040000>;
label = "u-boot-env";
};
};
};
};
&refclk {
clock-frequency = <20000000>;
};

343
arch/arm/dts/armada-xp-98dx3236.dtsi Normal file
View File

@ -0,0 +1,343 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell 98dx3236 family SoC
*
* Copyright (C) 2016 Allied Telesis Labs
*
* Contains definitions specific to the 98dx3236 SoC that are not
* common to all Armada XP SoCs.
*/
#include "armada-370-xp.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Marvell 98DX3236 SoC";
compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,98dx3236-smp";
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
clock-latency = <1000000>;
};
};
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
/*
* 98DX3236 has 1 x1 PCIe unit Gen2.0
*/
pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
};
internal-regs {
sdramc: sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
L2: l2-cache@8000 {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
cache-level = <2>;
cache-unified;
wt-override;
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
/* does not exist */
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
status = "disabled";
};
gpio2: gpio@18180 { /* rework some properties */
compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <1>; /* only gpio #32 */
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>;
};
systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,mv98dx3236-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
cpuclk: clock-complex@18700 {
#clock-cells = <1>;
compatible = "marvell,mv98dx3236-cpu-clock";
reg = <0x18700 0x24>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
};
corediv-clock@18740 {
status = "disabled";
};
cpu-config@21000 {
compatible = "marvell,armada-xp-cpu-config";
reg = <0x21000 0x8>;
};
ethernet@70000 {
compatible = "marvell,armada-xp-neta";
};
ethernet@74000 {
compatible = "marvell,armada-xp-neta";
};
xor1: xor@f0800 {
compatible = "marvell,orion-xor";
reg = <0xf0800 0x100
0xf0a00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor10 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
nand_controller: nand@d0000 {
clocks = <&dfx_coredivclk 0>;
};
xor0: xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
0xF0B00 0x100>;
clocks = <&gateclk 28>;
status = "okay";
xor00 {
interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
};
dfx: dfx-server@ac000000 {
compatible = "marvell,dfx-server", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
thermal: thermal@f8078 {
compatible = "marvell,armada380-thermal";
reg = <0xf8078 0x4>, <0xf8074 0x4>;
status = "okay";
};
coreclk: mvebu-sar@f8204 {
compatible = "marvell,mv98dx3236-core-clock";
reg = <0xf8204 0x4>;
#clock-cells = <1>;
};
dfx_coredivclk: corediv-clock@f8268 {
compatible = "marvell,mv98dx3236-corediv-clock";
reg = <0xf8268 0xc>;
#clock-cells = <1>;
clocks = <&mainpll>;
clock-output-names = "nand";
};
};
switch: switch@a8000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
pp0: packet-processor@0 {
compatible = "marvell,prestera-98dx3236", "marvell,prestera";
reg = <0 0x4000000>;
interrupts = <33>, <34>, <35>;
dfx = <&dfx>;
};
};
};
clocks {
/* 25 MHz reference crystal */
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
};
&i2c0 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
&i2c1 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};
&mpic {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
&rtc {
status = "disabled";
};
&timer {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&watchdog {
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&cpurst {
reg = <0x20800 0x20>;
};
&usb0 {
clocks = <&gateclk 18>;
};
&usb1 {
clocks = <&gateclk 19>;
};
&pinctrl {
compatible = "marvell,98dx3236-pinctrl";
nand_pins: nand-pins {
marvell,pins = "mpp20", "mpp21", "mpp22",
"mpp23", "mpp24", "mpp25",
"mpp26", "mpp27", "mpp28",
"mpp29", "mpp30";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp19";
marvell,function = "nand";
};
spi0_pins: spi0-pins {
marvell,pins = "mpp0", "mpp1",
"mpp2", "mpp3";
marvell,function = "spi0";
};
};
&spi0 {
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
};
&sdio {
status = "disabled";
};

39
arch/arm/dts/armada-xp-98dx3336.dtsi Normal file
View File

@ -0,0 +1,39 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell 98dx3336 family SoC
*
* Copyright (C) 2016 Allied Telesis Labs
*
* Contains definitions specific to the 98dx3236 SoC that are not
* common to all Armada XP SoCs.
*/
#include "armada-xp-98dx3236.dtsi"
/ {
model = "Marvell 98DX3336 SoC";
compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
cpus {
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
clock-latency = <1000000>;
};
};
soc {
internal-regs {
resume@20980 {
compatible = "marvell,98dx3336-resume-ctrl";
reg = <0x20980 0x10>;
};
};
};
};
&pp0 {
compatible = "marvell,prestera-98dx3336", "marvell,prestera";
};

54
arch/arm/dts/armada-xp-98dx4251.dtsi Normal file
View File

@ -0,0 +1,54 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell 98dx4521 family SoC
*
* Copyright (C) 2016 Allied Telesis Labs
*
* Contains definitions specific to the 98dx4521 SoC that are not
* common to all Armada XP SoCs.
*/
#include "armada-xp-98dx3236.dtsi"
/ {
model = "Marvell 98DX4251 SoC";
compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
cpus {
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
clock-latency = <1000000>;
};
};
soc {
internal-regs {
resume@20980 {
compatible = "marvell,98dx3336-resume-ctrl";
reg = <0x20980 0x10>;
};
};
};
};
&sdio {
status = "okay";
};
&pinctrl {
compatible = "marvell,98dx4251-pinctrl";
sdio_pins: sdio-pins {
marvell,pins = "mpp5", "mpp6", "mpp7",
"mpp8", "mpp9", "mpp10";
marvell,function = "sd0";
};
};
&pp0 {
compatible = "marvell,prestera-98dx4251", "marvell,prestera";
interrupts = <33>, <34>, <35>, <36>;
};

24
arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
&uart0 {
u-boot,dm-pre-reloc;
};
&nand_controller {
compatible="marvell,mvebu-pxa3xx-nand";
status = "okay";
label = "pxa3xx_nand-0";
nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
};
&spi0 {
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
};
};

110
arch/arm/dts/armada-xp-db-xc3-24g4xg.dts Normal file
View File

@ -0,0 +1,110 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for DB-XC3-24G4XG board
*
* Copyright (C) 2016 Allied Telesis Labs
*
* Based on armada-xp-db.dts
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
* boards were delivered with an older version of the bootloader that
* left internal registers mapped at 0xd0000000. If you are in this
* situation, you should either update your bootloader (preferred
* solution) or the below Device Tree should be adjusted.
*/
/dts-v1/;
#include "armada-xp-98dx3336.dtsi"
#include "armada-xp-db-xc3-24g4xg-u-boot.dtsi"
/ {
model = "DB-XC3-24G4XG";
compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
chosen {
stdout-path = "serial0:115200n8";
bootargs = "console=ttyS0,115200 earlyprintk";
};
aliases {
spi0 = &spi0;
};
memory {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
};
};
&L2 {
arm,parity-enable;
marvell,ecc-enable;
};
&devbus_bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
};
&usb0 {
status = "okay";
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x00100000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x00100000 0x00040000>;
label = "u-boot-env";
};
partition@unused {
reg = <0x00140000 0x00ec0000>;
label = "unused";
};
};
};

167
arch/arm/dts/armada-xp-gp.dts
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada XP development board
* (DB-MV784MP-GP)
@ -8,44 +9,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
@ -68,11 +31,7 @@
stdout-path = "serial0:115200n8";
};
aliases {
spi0 = &spi0;
};
memory {
memory@0 {
device_type = "memory";
/*
* 8 GB of plug-in RAM modules by default.The amount
@ -98,7 +57,10 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
devbus-bootcs {
status = "okay";
@ -128,31 +90,9 @@
};
};
pcie-controller {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
u-boot,dm-pre-reloc;
};
serial@12100 {
status = "okay";
@ -177,43 +117,33 @@
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <16>;
};
phy1: ethernet-phy@1 {
reg = <17>;
};
phy2: ethernet-phy@2 {
reg = <18>;
};
phy3: ethernet-phy@3 {
reg = <19>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "qsgmii";
buffer-manager = <&bm>;
bm,pool-long = <0>;
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "qsgmii";
buffer-manager = <&bm>;
bm,pool-long = <1>;
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "qsgmii";
buffer-manager = <&bm>;
bm,pool-long = <2>;
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "qsgmii";
buffer-manager = <&bm>;
bm,pool-long = <3>;
};
/* Front-side USB slot */
@ -226,27 +156,72 @@
status = "okay";
};
spi0: spi@10600 {
bm@c0000 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
nand@d0000 {
status = "okay";
label = "pxa3xx_nand-0";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
};
bm-bppi {
status = "okay";
};
};
};
&pciec {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@a,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 {
reg = <16>;
};
phy1: ethernet-phy@1 {
reg = <17>;
};
phy2: ethernet-phy@2 {
reg = <18>;
};
phy3: ethernet-phy@3 {
reg = <19>;
};
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};

24
arch/arm/dts/armada-xp-maxbcm.dts
View File

@ -225,18 +225,6 @@
status = "okay";
};
spi0: spi@10600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
nand@d0000 {
status = "okay";
num-cs = <1>;
@ -247,3 +235,15 @@
};
};
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};

55
arch/arm/dts/armada-xp-mv78230.dtsi
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Contains definitions specific to the Armada XP MV78230 SoC that are not
* common to all Armada XP SoCs.
*/
@ -207,25 +170,33 @@
internal-regs {
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18100 0x40>, <0x181c0 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18140 0x40>, <0x181c8 0x08>;
reg-names = "gpio", "pwm";
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>;
clocks = <&coreclk 0>;
};
};
};

58
arch/arm/dts/armada-xp-mv78260.dtsi
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Contains definitions specific to the Armada XP MV78260 SoC that are not
* common to all Armada XP SoCs.
*/
@ -294,29 +257,38 @@
internal-regs {
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18100 0x40>, <0x181c0 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18140 0x40>, <0x181c8 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
clocks = <&coreclk 0>;
};
gpio2: gpio@18180 {
compatible = "marvell,orion-gpio";
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;

58
arch/arm/dts/armada-xp-mv78460.dtsi
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Contains definitions specific to the Armada XP MV78460 SoC that are not
* common to all Armada XP SoCs.
*/
@ -333,29 +296,38 @@
internal-regs {
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18100 0x40>, <0x181c0 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18140 0x40>, <0x181c8 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
clocks = <&coreclk 0>;
};
gpio2: gpio@18180 {
compatible = "marvell,orion-gpio";
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;

199
arch/arm/dts/armada-xp-synology-ds414.dts
View File

@ -1,13 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Synology DS414
*
* Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the old 0xd0000000).
* The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
@ -42,36 +38,16 @@
spi0 = &spi0;
};
memory {
memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/*
* Connected to Marvell 88SX7042 SATA-II controller
* handling the four disks.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/*
* Connected to EtronTech EJ168A XHCI controller
* providing the two rear USB 3.0 ports.
*/
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
internal-regs {
@ -80,64 +56,6 @@
status = "disabled";
};
spi0: spi@10600 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
/*
* Warning!
*
* Synology u-boot uses its compiled-in environment
* and it seems Synology did not care to change u-boot
* default configuration in order to allow saving a
* modified environment at a sensible location. So,
* if you do a 'saveenv' under u-boot, your modified
* environment will be saved at 1MB after the start
* of the flash, i.e. in the middle of the uImage.
* For that reason, it is strongly advised not to
* change the default environment, unless you know
* what you are doing.
*/
partition@00000000 { /* u-boot */
label = "RedBoot";
reg = <0x00000000 0x000d0000>; /* 832KB */
};
partition@000c0000 { /* uImage */
label = "zImage";
reg = <0x000d0000 0x002d0000>; /* 2880KB */
};
partition@003a0000 { /* uInitramfs */
label = "rd.gz";
reg = <0x003a0000 0x00430000>; /* 4250KB */
};
partition@007d0000 { /* MAC address and serial number */
label = "vendor";
reg = <0x007d0000 0x00010000>; /* 64KB */
};
partition@007e0000 {
label = "RedBoot config";
reg = <0x007e0000 0x00010000>; /* 64KB */
};
partition@007f0000 {
label = "FIS directory";
reg = <0x007f0000 0x00010000>; /* 64KB */
};
};
};
i2c@11000 {
clock-frequency = <400000>;
status = "okay";
@ -179,16 +97,6 @@
status = "okay";
};
mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
reg = <1>;
};
};
ethernet@70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
@ -215,7 +123,7 @@
&sata3_pwr_pin &sata4_pwr_pin>;
pinctrl-names = "default";
sata1_regulator: sata1-regulator {
sata1_regulator: sata1-regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA1 Power";
@ -228,7 +136,7 @@
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
sata2_regulator: sata2-regulator {
sata2_regulator: sata2-regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA2 Power";
@ -241,7 +149,7 @@
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
sata3_regulator: sata3-regulator {
sata3_regulator: sata3-regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "SATA3 Power";
@ -254,7 +162,7 @@
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
sata4_regulator: sata4-regulator {
sata4_regulator: sata4-regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "SATA4 Power";
@ -269,6 +177,39 @@
};
};
&pciec {
status = "okay";
/*
* Connected to Marvell 88SX7042 SATA-II controller
* handling the four disks.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/*
* Connected to EtronTech EJ168A XHCI controller
* providing the two rear USB 3.0 ports.
*/
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
reg = <1>;
};
};
&pinctrl {
sata1_pwr_pin: sata1-pwr-pin {
marvell,pins = "mpp42";
@ -335,3 +276,59 @@
marvell,function = "gpio";
};
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
/*
* Warning!
*
* Synology u-boot uses its compiled-in environment
* and it seems Synology did not care to change u-boot
* default configuration in order to allow saving a
* modified environment at a sensible location. So,
* if you do a 'saveenv' under u-boot, your modified
* environment will be saved at 1MB after the start
* of the flash, i.e. in the middle of the uImage.
* For that reason, it is strongly advised not to
* change the default environment, unless you know
* what you are doing.
*/
partition@0 { /* u-boot */
label = "RedBoot";
reg = <0x00000000 0x000d0000>; /* 832KB */
};
partition@c0000 { /* uImage */
label = "zImage";
reg = <0x000d0000 0x002d0000>; /* 2880KB */
};
partition@3a0000 { /* uInitramfs */
label = "rd.gz";
reg = <0x003a0000 0x00430000>; /* 4250KB */
};
partition@7d0000 { /* MAC address and serial number */
label = "vendor";
reg = <0x007d0000 0x00010000>; /* 64KB */
};
partition@7e0000 {
label = "RedBoot config";
reg = <0x007e0000 0x00010000>; /* 64KB */
};
partition@7f0000 {
label = "FIS directory";
reg = <0x007f0000 0x00010000>; /* 64KB */
};
};
};

69
arch/arm/dts/armada-xp-theadorable.dts
View File

@ -126,40 +126,6 @@
status = "okay";
};
spi0: spi@10600 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
fpga@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-generic-device";
reg = <1>; /* Chip select 1 */
spi-max-frequency = <27777777>;
};
};
spi1: spi@10680 {
status = "okay";
fpga@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-generic-device";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
};
/* The LCD controller is only used on this board */
lcd0: lcd-controller@e0000 {
compatible = "marvell,armada-xp-lcd";
@ -188,6 +154,41 @@
};
};
&spi0 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
fpga@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-generic-device";
reg = <1>; /* Chip select 1 */
spi-max-frequency = <27777777>;
};
};
&spi1 {
status = "okay";
fpga@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-generic-device";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
};
&pciec {
status = "okay";

214
arch/arm/dts/armada-xp.dtsi
View File

@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@ -8,44 +9,6 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Contains definitions specific to the Armada XP SoC that are not
* common to all Armada SoCs.
*/
@ -53,6 +16,9 @@
#include "armada-370-xp.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
@ -71,12 +37,12 @@
};
internal-regs {
sdramc@1400 {
sdramc: sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
L2: l2-cache {
L2: l2-cache@8000 {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
@ -85,29 +51,6 @@
wt-override;
};
spi0: spi@10600 {
compatible = "marvell,armada-xp-spi",
"marvell,orion-spi";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
};
spi1: spi@10680 {
compatible = "marvell,armada-xp-spi",
"marvell,orion-spi";
};
i2c0: i2c@11000 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
i2c1: i2c@11100 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};
uart2: serial@12200 {
compatible = "snps,dw-apb-uart";
pinctrl-0 = <&uart2_pins>;
@ -132,7 +75,7 @@
status = "disabled";
};
system-controller@18200 {
systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
@ -150,7 +93,7 @@
#clock-cells = <1>;
};
thermal@182b0 {
thermal: thermal@182b0 {
compatible = "marvell,armadaxp-thermal";
reg = <0x182b0 0x4
0x184d0 0x4>;
@ -164,25 +107,9 @@
clocks = <&coreclk 1>;
};
interrupt-controller@20a00 {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
timer@20300 {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
watchdog@20300 {
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x20>;
cpu-config@21000 {
compatible = "marvell,armada-xp-cpu-config";
reg = <0x21000 0x8>;
};
eth2: ethernet@30000 {
@ -193,15 +120,7 @@
status = "disabled";
};
usb@50000 {
clocks = <&gateclk 18>;
};
usb@51000 {
clocks = <&gateclk 19>;
};
usb@52000 {
usb2: usb@52000 {
compatible = "marvell,orion-ehci";
reg = <0x52000 0x500>;
interrupts = <47>;
@ -209,7 +128,7 @@
status = "disabled";
};
xor@60900 {
xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@ -237,7 +156,27 @@
compatible = "marvell,armada-xp-neta";
};
xor@f0900 {
cesa: crypto@90000 {
compatible = "marvell,armada-xp-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <48>, <49>;
clocks = <&gateclk 23>, <&gateclk 23>;
clock-names = "cesa0", "cesa1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
bm: bm@c0000 {
compatible = "marvell,armada-380-neta-bm";
reg = <0xc0000 0xac>;
clocks = <&gateclk 13>;
internal-mem = <&bm_bppi>;
status = "disabled";
};
xor0: xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
0xF0B00 0x100>;
@ -257,6 +196,35 @@
};
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
};
bm_bppi: bm-bppi {
compatible = "mmio-sram";
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gateclk 13>;
no-memory-wc;
status = "disabled";
};
};
clocks {
@ -269,6 +237,44 @@
};
};
&i2c0 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
&i2c1 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};
&mpic {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
&timer {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&watchdog {
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&cpurst {
reg = <0x20800 0x20>;
};
&usb0 {
clocks = <&gateclk 18>;
};
&usb1 {
clocks = <&gateclk 19>;
};
&pinctrl {
ge0_gmii_pins: ge0-gmii-pins {
marvell,pins =
@ -309,6 +315,12 @@
marvell,function = "spi0";
};
spi1_pins: spi1-pins {
marvell,pins = "mpp13", "mpp14",
"mpp16", "mpp17";
marvell,function = "spi1";
};
uart2_pins: uart2-pins {
marvell,pins = "mpp42", "mpp43";
marvell,function = "uart2";
@ -319,3 +331,15 @@
marvell,function = "uart3";
};
};
&spi0 {
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
};
&spi1 {
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
};

74
arch/arm/mach-kirkwood/cpu.c
View File

@ -46,69 +46,31 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval)
return (0x0000ffff & j);
}
/*
* kw_config_adr_windows - Configure address Windows
*
* There are 8 address windows supported by Kirkwood Soc to addess different
* devices. Each window can be configured for size, BAR and remap addr
* Below configuration is standard for most of the cases
*
* If remap function not used, remap_lo must be set as base
*
* Reference Documentation:
* Mbus-L to Mbus Bridge Registers Configuration.
* (Sec 25.1 and 25.3 of Datasheet)
*/
int kw_config_adr_windows(void)
{
struct kwwin_registers *winregs =
(struct kwwin_registers *)KW_CPU_WIN_BASE;
static struct mbus_win windows[] = {
/* Window 0: PCIE MEM address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
writel(0x0, &winregs[0].remap_hi);
{ KW_DEFADR_PCI_MEM, 1024 * 1024 * 256,
KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
/* Window 1: PCIE IO address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
writel(KW_DEFADR_PCI_IO, &winregs[1].base);
writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
writel(0x0, &winregs[1].remap_hi);
{ KW_DEFADR_PCI_IO, 1024 * 64,
KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO },
/* Window 2: NAND Flash address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
writel(KW_DEFADR_NANDF, &winregs[2].base);
writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
writel(0x0, &winregs[2].remap_hi);
{ KW_DEFADR_NANDF, 1024 * 1024 * 128,
KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH },
/* Window 3: SPI Flash address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
writel(KW_DEFADR_SPIF, &winregs[3].base);
writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
writel(0x0, &winregs[3].remap_hi);
{ KW_DEFADR_SPIF, 1024 * 1024 * 128,
KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH },
/* Window 4: BOOT Memory address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
writel(KW_DEFADR_BOOTROM, &winregs[4].base);
{ KW_DEFADR_BOOTROM, 1024 * 1024 * 128,
KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM },
/* Window 5: Security SRAM address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
writel(KW_DEFADR_SASRAM, &winregs[5].base);
/* Window 6-7: Disabled */
writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
return 0;
}
{ KW_DEFADR_SASRAM, 1024 * 64,
KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM },
};
/*
* SYSRSTn Duration Counter Support
@ -221,15 +183,13 @@ int arch_cpu_init(void)
struct kwcpu_registers *cpureg =
(struct kwcpu_registers *)KW_CPU_REG_BASE;
/* Linux expects` the internal registers to be at 0xf1000000 */
/* Linux expects the internal registers to be at 0xf1000000 */
writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
/* Enable and invalidate L2 cache in write through mode */
writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
invalidate_l2_cache();
kw_config_adr_windows();
#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
/*
* Configures the I/O voltage of the pads connected to Egigabit
@ -291,11 +251,13 @@ int arch_misc_init(void)
temp |= (1 << 22);
writefr_extra_feature_reg(temp);
icache_enable();
/* Change reset vector to address 0x0 */
temp = get_cr();
set_cr(temp & ~CR_V);
/* Configure mbus windows */
mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
/* checks and execute resset to factory event */
kw_sysrst_check();

13
arch/arm/mach-kirkwood/include/mach/cpu.h
View File

@ -63,12 +63,18 @@ enum kwcpu_attrib {
*/
#define KW_DEFADR_PCI_MEM 0x90000000
#define KW_DEFADR_PCI_IO 0xC0000000
#define KW_DEFADR_PCI_IO_REMAP 0xC0000000
#define KW_DEFADR_SASRAM 0xC8010000
#define KW_DEFADR_NANDF 0xD8000000
#define KW_DEFADR_SPIF 0xE8000000
#define KW_DEFADR_BOOTROM 0xF8000000
struct mbus_win {
u32 base;
u32 size;
u8 target;
u8 attr;
};
/*
* read feroceon/sheeva core extra feature register
* using co-proc instruction
@ -135,13 +141,16 @@ struct kwgpio_registers {
u32 irq_level;
};
/* Needed for dynamic (board-specific) mbus configuration */
extern struct mvebu_mbus_state mbus_state;
/*
* functions
*/
unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
int kw_config_adr_windows(void);
int mvebu_mbus_probe(struct mbus_win windows[], int count);
void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,

2
arch/arm/mach-kirkwood/include/mach/soc.h
View File

@ -31,7 +31,7 @@
#define KW_RTC_BASE (KW_REGISTER(0x10300))
#define KW_NANDF_BASE (KW_REGISTER(0x10418))
#define MVEBU_SPI_BASE (KW_REGISTER(0x10600))
#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000))
#define MVEBU_CPU_WIN_BASE (KW_REGISTER(0x20000))
#define KW_CPU_REG_BASE (KW_REGISTER(0x20100))
#define MVEBU_TIMER_BASE (KW_REGISTER(0x20300))
#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000))

34
arch/arm/mach-mvebu/Kconfig
View File

@ -9,10 +9,10 @@ config ARMADA_32BIT
select ARCH_MISC_INIT
select BOARD_EARLY_INIT_F
select CPU_V7A
select SPL_DM
select SPL_DM_SEQ_ALIAS
select SPL_OF_CONTROL
select SPL_SIMPLE_BUS
select SPL_DM if SPL
select SPL_DM_SEQ_ALIAS if SPL
select SPL_OF_CONTROL if SPL
select SPL_SIMPLE_BUS if SPL
select SUPPORT_SPL
config ARMADA_64BIT
@ -46,7 +46,7 @@ config ARMADA_8K
# Armada PLL frequency (used for NAND clock generation)
config SYS_MVEBU_PLL_CLOCK
int
default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K || ARMADA_MSYS
default "1000000000" if ARMADA_38X || ARMADA_375
# Armada XP/38x SoC types...
@ -63,6 +63,22 @@ config MV78460
bool
select ARMADA_XP
config ARMADA_MSYS
bool
select ARMADA_32BIT
config 98DX4251
bool
select ARMADA_MSYS
config 98DX3336
bool
select ARMADA_MSYS
config 98DX3236
bool
select ARMADA_MSYS
config 88F6820
bool
select ARMADA_38X
@ -136,6 +152,10 @@ config TARGET_X530
bool "Support Allied Telesis x530"
select 88F6820
config TARGET_DB_XC3_24G4XG
bool "Support DB-XC3-24G4XG"
select 98DX3336
endchoice
config SYS_BOARD
@ -154,6 +174,7 @@ config SYS_BOARD
default "theadorable" if TARGET_THEADORABLE
default "a38x" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
@ -171,6 +192,7 @@ config SYS_CONFIG_NAME
default "turris_mox" if TARGET_TURRIS_MOX
default "controlcenterdc" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
@ -179,6 +201,8 @@ config SYS_VENDOR
default "Marvell" if TARGET_DB_88F6820_GP
default "Marvell" if TARGET_DB_88F6820_AMC
default "Marvell" if TARGET_MVEBU_ARMADA_8K
default "Marvell" if TARGET_DB_XC3_24G4XG
default "Marvell" if TARGET_MVEBU_DB_88F7040
default "solidrun" if TARGET_CLEARFOG
default "kobol" if TARGET_HELIOS4
default "Synology" if TARGET_DS414

2
arch/arm/mach-mvebu/Makefile
View File

@ -14,6 +14,7 @@ ifdef CONFIG_KIRKWOOD
obj-y = dram.o
obj-y += gpio.o
obj-y += mbus.o
obj-y += timer.o
else # CONFIG_KIRKWOOD
@ -24,6 +25,7 @@ ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
extra-y += kwbimage.cfg

46
arch/arm/mach-mvebu/cpu.c
View File

@ -23,6 +23,11 @@ static struct mbus_win windows[] = {
/* NOR */
{ MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
#ifdef CONFIG_ARMADA_MSYS
/* DFX */
{ MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
#endif
};
void lowlevel_init(void)
@ -121,6 +126,14 @@ static const struct sar_freq_modes sar_freq_tab[] = {
{ 0x13, 0x0, 2000, 1000, 933 },
{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
};
#elif defined(CONFIG_ARMADA_MSYS)
static const struct sar_freq_modes sar_freq_tab[] = {
{ 0x0, 0x0, 400, 400, 400 },
{ 0x2, 0x0, 667, 333, 667 },
{ 0x3, 0x0, 800, 400, 800 },
{ 0x5, 0x0, 800, 400, 800 },
{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
};
#else
/* SAR frequency values for Armada XP */
static const struct sar_freq_modes sar_freq_tab[] = {
@ -144,7 +157,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
u32 freq;
int i;
#if defined(CONFIG_ARMADA_375)
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
#else
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
@ -160,7 +173,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
#endif
for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
if (sar_freq_tab[i].val == freq) {
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
*sar_freq = sar_freq_tab[i];
return;
#else
@ -270,6 +283,20 @@ int print_cpuinfo(void)
}
}
if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
switch (revid) {
case 3:
puts("A0");
break;
case 4:
puts("A1");
break;
default:
printf("?? (%x)", revid);
break;
}
}
get_sar_freq(&sar_freq);
printf(" at %d MHz\n", sar_freq.p_clk);
@ -472,6 +499,8 @@ u32 mvebu_get_nand_clock(void)
if (mvebu_soc_family() == MVEBU_SOC_A38X)
reg = MVEBU_DFX_DIV_CLK_CTRL(1);
else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
reg = MVEBU_DFX_DIV_CLK_CTRL(8);
else
reg = MVEBU_CORE_DIV_CLK_CTRL(1);
@ -501,7 +530,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
#ifdef CONFIG_SCSI_AHCI_PLAT
#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
@ -545,11 +573,19 @@ static void ahci_mvebu_regret_option(void __iomem *base)
writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
}
int board_ahci_enable(void)
{
ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
return 0;
}
#ifdef CONFIG_SCSI_AHCI_PLAT
void scsi_init(void)
{
printf("MVEBU SATA INIT\n");
ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
board_ahci_enable();
ahci_init((void __iomem *)MVEBU_SATA0_BASE);
}
#endif

2
arch/arm/mach-mvebu/include/mach/config.h
View File

@ -17,7 +17,7 @@
#include <asm/arch/soc.h>
#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
|| defined(CONFIG_ARMADA_38X)
|| defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
/*
* Set this for the common xor register definitions needed in dram.c
* for A38x as well here.

3
arch/arm/mach-mvebu/include/mach/cpu.h
View File

@ -34,6 +34,7 @@ enum cpu_target {
CPU_TARGET_PCIE02 = 0x4,
CPU_TARGET_ETH01 = 0x7,
CPU_TARGET_PCIE13 = 0x8,
CPU_TARGET_DFX = 0x8,
CPU_TARGET_SASRAM = 0x9,
CPU_TARGET_SATA01 = 0xa, /* A38X */
CPU_TARGET_NAND = 0xd,
@ -79,6 +80,8 @@ enum {
#define MBUS_PCI_IO_SIZE (64 << 10)
#define MBUS_SPI_BASE 0xF4000000
#define MBUS_SPI_SIZE (8 << 20)
#define MBUS_DFX_BASE 0xF6000000
#define MBUS_DFX_SIZE (1 << 20)
#define MBUS_BOOTROM_BASE 0xF8000000
#define MBUS_BOOTROM_SIZE (8 << 20)

31
arch/arm/mach-mvebu/include/mach/soc.h
View File

@ -76,7 +76,11 @@
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
#ifdef CONFIG_ARMADA_MSYS
#define MVEBU_DFX_BASE (MBUS_DFX_BASE)
#else
#define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
#endif
#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
#define MBUS_ERR_PROP_EN (1 << 8)
@ -96,9 +100,20 @@
#define SPI_PUP_EN BIT(5)
#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
#ifdef CONFIG_ARMADA_MSYS
#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4))
#define NAND_ECC_DIVCKL_RATIO_OFFS 6
#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
#else
#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
#endif
#ifdef CONFIG_ARMADA_MSYS
#define NAND_ECC_DIVCKL_RATIO_OFFS 6
#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
#else
#define NAND_ECC_DIVCKL_RATIO_OFFS 8
#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
#endif
#define SDRAM_MAX_CS 4
#define SDRAM_ADDR_MASK 0xFF000000
@ -149,6 +164,22 @@
#define BOOT_FROM_SPI 0x32
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
#elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */
#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
#define SAR_CPU_FREQ_OFFS 18
#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
#define SAR_BOOT_DEVICE_OFFS 11
#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS)
#define BOOT_DEV_SEL_OFFS 11
#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS)
#define BOOT_FROM_NAND 0x1
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
#else
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))

9
arch/arm/mach-mvebu/mbus.c
View File

@ -344,6 +344,11 @@ static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
}
}
mbus_dram_info.num_cs = cs;
#if defined(CONFIG_ARMADA_MSYS)
/* Disable MBUS Err Prop - in order to avoid data aborts */
clrbits_le32(mbus->mbuswins_base + 0x200, BIT(8));
#endif
}
static const struct mvebu_mbus_soc_data
@ -405,6 +410,7 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size)
return 0;
}
#ifndef CONFIG_KIRKWOOD
static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus,
phys_addr_t *base)
{
@ -451,6 +457,7 @@ static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus)
val = (size / (64 << 10)) - 1;
writel((val << 16) | 0x1, MBUS_BRIDGE_WIN_CTRL_REG);
}
#endif
int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
u32 base, u32 size, u8 target, u8 attr)
@ -471,12 +478,14 @@ int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
return -ENOMEM;
}
#ifndef CONFIG_KIRKWOOD
/*
* Re-configure the mbus bridge registers each time this function
* is called. Since it may get called from the board code in
* later boot stages as well.
*/
mvebu_config_mbus_bridge(mbus);
#endif
return 0;
}

8
arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
View File

@ -35,7 +35,7 @@ int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
#define ETM_MODULE_DETECT 2
#define PEX_MODE_GET(satr) ((satr & 0x6) >> 1)
#define PEX_CAPABILITY_GET(satr) (satr & 1)
#define PEX_CAPABILITY_GET(satr, port) ((satr >> port) & 1)
#define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9)
/* Static parametes */
@ -176,7 +176,7 @@ u8 board_cpu_freq_get(void)
return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
}
__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
{
u32 board_id;
u32 serdes_cfg_val = 0; /* default */
@ -352,7 +352,7 @@ int serdes_phy_config(void)
DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
}
info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
info = board_serdes_cfg_get();
if (info == NULL) {
DEBUG_INIT_S("Hight speed PHY Error #1\n");
@ -675,7 +675,7 @@ int serdes_phy_config(void)
tmp |= (0x1 << 4);
if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
tmp |= (0x4 << 4);
if (0 == PEX_CAPABILITY_GET(satr11))
if (0 == PEX_CAPABILITY_GET(satr11, pex_unit))
tmp |= 0x1;
else
tmp |= 0x2;

2
board/CZ.NIC/turris_omnia/turris_omnia.c
View File

@ -379,7 +379,7 @@ int board_init(void)
puts("Cannot find Armada 385 watchdog!\n");
} else {
puts("Enabling Armada 385 watchdog.\n");
wdt_start(watchdog_dev, (u32) 25000000 * 120, 0);
wdt_start(watchdog_dev, 120000, 0);
}
# endif

1
board/Marvell/db-xc3-24g4xg/.gitignore vendored Normal file
View File

@ -0,0 +1 @@
kwbimage.cfg

7
board/Marvell/db-xc3-24g4xg/MAINTAINERS Normal file
View File

@ -0,0 +1,7 @@
DB-XC3-24G4XG BOARD
M: Chris Packham <chris.packham@alliedtelesis.co.nz>
S: Maintained
F: board/Marvell/db-xc3-24g4xg/
F: include/configs/db-xc3-24g4xg.h
F: configs/db-xc3-24g4xg_defconfig
F: arch/arm/dts/armada-xp-db-xc3-24g4xg.dts

14
board/Marvell/db-xc3-24g4xg/Makefile Normal file
View File

@ -0,0 +1,14 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2015 Stefan Roese <sr@denx.de>
obj-y := db-xc3-24g4xg.o
extra-y := kwbimage.cfg
quiet_cmd_sed = SED $@
cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F)
SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|"
$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \
include/config/auto.conf
$(call if_changed,sed)

4
board/Marvell/db-xc3-24g4xg/README Normal file
View File

@ -0,0 +1,4 @@
To generate binary.0 from Marvell's bin_hdr.elf use the following command
arm-softfloat-linux-gnueabi-objcopy -S -O binary bin_hdr.elf \
board/Marvell/db-xc3-24g4xg/binary.0

11
board/Marvell/db-xc3-24g4xg/binary.0 Normal file
View File

@ -0,0 +1,11 @@
--------
WARNING:
--------
This file should contain the bin_hdr generated by the original Marvell
U-Boot implementation. As this is currently not included in this
U-Boot version, we have added this placeholder, so that the U-Boot
image can be generated without errors.
If you have a known to be working bin_hdr for your board, then you
just need to replace this text file here with the binary header
and recompile U-Boot.

68
board/Marvell/db-xc3-24g4xg/db-xc3-24g4xg.c Normal file
View File

@ -0,0 +1,68 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
*/
#include <common.h>
#include <i2c.h>
#include <asm/gpio.h>
#include <linux/mbus.h>
#include <linux/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* These values and defines are taken from the Marvell U-Boot version
* "u-boot-2013.01-2016_T1.0.eng_drop_v6"
*/
#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30)))
#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0))
#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(6) | BIT(12) \
| BIT(13) | BIT(16) | BIT(17) | BIT(20) | BIT(29) | BIT(30))
#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0
#define DB_DX_AC3_GPP_POL_LOW 0x0
#define DB_DX_AC3_GPP_POL_MID 0x0
int board_early_init_f(void)
{
/* Configure MPP */
writel(0x00142222, MVEBU_MPP_BASE + 0x00);
writel(0x11122000, MVEBU_MPP_BASE + 0x04);
writel(0x44444004, MVEBU_MPP_BASE + 0x08);
writel(0x14444444, MVEBU_MPP_BASE + 0x0c);
writel(0x00000001, MVEBU_MPP_BASE + 0x10);
/* Set GPP Out value */
writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
/* Set GPP Polarity */
writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
/* Set GPP Out Enable */
writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
puts("Board: " CONFIG_SYS_BOARD "\n");
return 0;
}
#endif

12
board/Marvell/db-xc3-24g4xg/kwbimage.cfg.in Normal file
View File

@ -0,0 +1,12 @@
#
# Copyright (C) 2014 Stefan Roese <sr@denx.de>
#
# Armada XP uses version 1 image format
VERSION 1
# Boot Media configurations
BOOT_FROM spi
# Binary Header (bin_hdr) with DDR3 training code
BINARY board/Marvell/db-xc3-24g4xg/binary.0 0000005b 00000068

4
board/Synology/ds414/ds414.c
View File

@ -115,14 +115,14 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
return &ds414_ddr_modes[0];
}
MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
{
return &ds414_serdes_cfg[0];
}
u8 board_sat_r_get(u8 dev_num, u8 reg)
{
return (0x1 << 1 | 1);
return 0xf; /* All PEX ports support PCIe Gen2 */
}
int board_early_init_f(void)

48
board/alliedtelesis/x530/x530.c
View File

@ -7,6 +7,7 @@
#include <command.h>
#include <dm.h>
#include <i2c.h>
#include <wdt.h>
#include <asm/gpio.h>
#include <linux/mbus.h>
#include <linux/io.h>
@ -24,6 +25,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_NVS_LOCATION 0xf4800000
#define CONFIG_NVS_SIZE (512 << 10)
#ifdef CONFIG_WATCHDOG
static struct udevice *watchdog_dev;
#endif
static struct serdes_map board_serdes_map[] = {
{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
@ -75,6 +80,10 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
int board_early_init_f(void)
{
#ifdef CONFIG_WATCHDOG
watchdog_dev = NULL;
#endif
/* Configure MPP */
writel(0x00001111, MVEBU_MPP_BASE + 0x00);
writel(0x00000000, MVEBU_MPP_BASE + 0x04);
@ -88,6 +97,17 @@ int board_early_init_f(void)
return 0;
}
void spl_board_init(void)
{
#ifdef CONFIG_WATCHDOG
int ret;
ret = uclass_get_device(UCLASS_WDT, 0, &watchdog_dev);
if (!ret)
wdt_start(watchdog_dev, 120000, 0);
#endif
}
int board_init(void)
{
/* address of boot parameters */
@ -100,9 +120,37 @@ int board_init(void)
/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
spl_board_init();
return 0;
}
void arch_preboot_os(void)
{
#ifdef CONFIG_WATCHDOG
wdt_stop(watchdog_dev);
#endif
}
#ifdef CONFIG_WATCHDOG
void watchdog_reset(void)
{
static ulong next_reset = 0;
ulong now;
if (!watchdog_dev)
return;
now = timer_get_us();
/* Do not reset the watchdog too often */
if (now > next_reset) {
wdt_reset(watchdog_dev);
next_reset = now + 1000;
}
}
#endif
static int led_7seg_init(unsigned int segments)
{
int node;

2
board/maxbcm/maxbcm.c
View File

@ -95,7 +95,7 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
return &maxbcm_ddr_modes[0];
}
MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
{
return &maxbcm_serdes_cfg[0];
}

23
board/solidrun/clearfog/README
View File

@ -17,6 +17,29 @@ $ sudo dd if=u-boot-spl.kwb of=/dev/sdX bs=512 seek=1
Please use the correct device node for your setup instead
of "/dev/sdX" here!
Install U-Boot on eMMC:
-----------------------
The ROM loads the bootloader from eMMC first boot partition at offset 0. This
is unlike load from SD card that is at offset 512. As a result, the offset of
the main U-Boot image on the eMMC boot partition changes. Set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR to 0x140 for SPL to load U-Boot from
the correct location.
To make SPL load the main U-Boot image from the eMMC boot partition enable
eMMC boot acknowledgement and boot partition with the following U-Boot
command:
mmc partconf 0 1 1 0
Install U-Boot on eMMC boot partition from Linux running on Clearfog:
echo 0 > /sys/block/mmcblk0boot0/force_ro
dd if=u-boot-spl.kwb of=/dev/mmcblk0boot0
Note that the SD card is not accessible when the Clearfog SOM has eMMC.
Consider initial boot from UART (see below).
Boot selection:
---------------

38
board/theadorable/theadorable.c
View File

@ -1,11 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
* Copyright (C) 2015-2019 Stefan Roese <sr@denx.de>
*/
#include <common.h>
#include <console.h>
#include <i2c.h>
#include <pci.h>
#if !defined(CONFIG_SPL_BUILD)
#include <bootcount.h>
#endif
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
@ -42,6 +46,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define STM_I2C_BUS 1
#define STM_I2C_ADDR 0x27
#define REBOOT_DELAY 1000 /* reboot-delay in ms */
#define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */
/* DDR3 static configuration */
static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
@ -127,15 +132,15 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
return &board_ddr_modes[0];
}
MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
{
return &theadorable_serdes_cfg[0];
}
u8 board_sat_r_get(u8 dev_num, u8 reg)
{
/* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
return 0x01;
/* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
}
int board_early_init_f(void)
@ -218,7 +223,7 @@ int board_eth_init(bd_t *bis)
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
int board_late_init(void)
{
pci_dev_t bdf;
@ -232,6 +237,7 @@ int board_late_init(void)
*/
bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
if (bdf == -1) {
unsigned long start_time = get_timer(0);
u8 i2c_buf[8];
int ret;
@ -239,6 +245,28 @@ int board_late_init(void)
bootcount = bootcount_load();
printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
bootcount);
/*
* The user can exit this boot-loop in the error case by
* hitting Ctrl-C. So wait some time for this key here.
*/
printf("Continue booting with Ctrl-C, otherwise rebooting\n");
do {
/* Handle control-c and timeouts */
if (ctrlc()) {
printf("PEX error boot-loop aborted!\n");
return 0;
}
} while (get_timer(start_time) < ABORT_TIMEOUT);
/*
* At this stage the bootcounter has not been incremented
* yet. We need to do this manually here to get an actually
* working bootcounter in this error case.
*/
bootcount_inc();
if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
printf("Issuing power-switch via uC!\n");

6
cmd/Kconfig
View File

@ -1101,6 +1101,12 @@ config CMD_VIRTIO
help
VirtIO block device support
config CMD_WDT
bool "wdt"
depends on WDT
help
This provides commands to control the watchdog timer devices.
config CMD_AXI
bool "axi"
depends on AXI

1
cmd/Makefile
View File

@ -142,6 +142,7 @@ obj-$(CONFIG_CMD_UBIFS) += ubifs.o
obj-$(CONFIG_CMD_UNIVERSE) += universe.o
obj-$(CONFIG_CMD_UNZIP) += unzip.o
obj-$(CONFIG_CMD_VIRTIO) += virtio.o
obj-$(CONFIG_CMD_WDT) += wdt.o
obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o
obj-$(CONFIG_CMD_USB) += usb.o disk.o

174
cmd/wdt.c Normal file
View File

@ -0,0 +1,174 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Watchdog commands
*
* Copyright (c) 2019 Michael Walle <michael@walle.cc>
*/
#include <common.h>
#include <command.h>
#include <dm.h>
#include <wdt.h>
static struct udevice *currdev;
static int do_wdt_list(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
struct udevice *dev;
struct uclass *uc;
int ret;
ret = uclass_get(UCLASS_WDT, &uc);
if (ret)
return CMD_RET_FAILURE;
uclass_foreach_dev(dev, uc)
printf("%s (%s)\n", dev->name, dev->driver->name);
return CMD_RET_SUCCESS;
}
static int do_wdt_dev(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
int ret;
if (argc > 1) {
ret = uclass_get_device_by_name(UCLASS_WDT, argv[1], &currdev);
if (ret) {
printf("Can't get the watchdog timer: %s\n", argv[1]);
return CMD_RET_FAILURE;
}
} else {
if (!currdev) {
printf("No watchdog timer device set!\n");
return CMD_RET_FAILURE;
}
printf("dev: %s\n", currdev->name);
}
return CMD_RET_SUCCESS;
}
static int check_currdev(void)
{
if (!currdev) {
printf("No device set, use 'wdt dev' first\n");
return CMD_RET_FAILURE;
}
return 0;
}
static int do_wdt_start(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
int ret;
u64 timeout;
ulong flags = 0;
if (argc < 2)
return CMD_RET_USAGE;
ret = check_currdev();
if (ret)
return ret;
timeout = simple_strtoull(argv[1], NULL, 0);
if (argc > 2)
flags = simple_strtoul(argv[2], NULL, 0);
ret = wdt_start(currdev, timeout, flags);
if (ret == -ENOSYS) {
printf("Starting watchdog timer not supported.\n");
return CMD_RET_FAILURE;
} else if (ret) {
printf("Starting watchdog timer failed (%d)\n", ret);
return CMD_RET_FAILURE;
}
return CMD_RET_SUCCESS;
}
static int do_wdt_stop(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
int ret;
ret = check_currdev();
if (ret)
return ret;
ret = wdt_stop(currdev);
if (ret == -ENOSYS) {
printf("Stopping watchdog timer not supported.\n");
return CMD_RET_FAILURE;
} else if (ret) {
printf("Stopping watchdog timer failed (%d)\n", ret);
return CMD_RET_FAILURE;
}
return CMD_RET_SUCCESS;
}
static int do_wdt_reset(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
int ret;
ret = check_currdev();
if (ret)
return ret;
ret = wdt_reset(currdev);
if (ret == -ENOSYS) {
printf("Resetting watchdog timer not supported.\n");
return CMD_RET_FAILURE;
} else if (ret) {
printf("Resetting watchdog timer failed (%d)\n", ret);
return CMD_RET_FAILURE;
}
return CMD_RET_SUCCESS;
}
static int do_wdt_expire(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
int ret;
ulong flags = 0;
ret = check_currdev();
if (ret)
return ret;
if (argc > 1)
flags = simple_strtoul(argv[1], NULL, 0);
ret = wdt_expire_now(currdev, flags);
if (ret == -ENOSYS) {
printf("Expiring watchdog timer not supported.\n");
return CMD_RET_FAILURE;
} else if (ret) {
printf("Expiring watchdog timer failed (%d)\n", ret);
return CMD_RET_FAILURE;
}
return CMD_RET_SUCCESS;
}
static char wdt_help_text[] =
"list - list watchdog devices\n"
"wdt dev [<name>] - get/set current watchdog device\n"
"wdt start <timeout ms> [flags] - start watchdog timer\n"
"wdt stop - stop watchdog timer\n"
"wdt reset - reset watchdog timer\n"
"wdt expire [flags] - expire watchdog timer immediately\n";
U_BOOT_CMD_WITH_SUBCMDS(wdt, "Watchdog sub-system", wdt_help_text,
U_BOOT_SUBCMD_MKENT(list, 1, 1, do_wdt_list),
U_BOOT_SUBCMD_MKENT(dev, 2, 1, do_wdt_dev),
U_BOOT_SUBCMD_MKENT(start, 3, 1, do_wdt_start),
U_BOOT_SUBCMD_MKENT(stop, 1, 1, do_wdt_stop),
U_BOOT_SUBCMD_MKENT(reset, 1, 1, do_wdt_reset),
U_BOOT_SUBCMD_MKENT(expire, 2, 1, do_wdt_expire));

2
configs/db-88f6820-amc_defconfig
View File

@ -41,7 +41,7 @@ CONFIG_CMD_FS_GENERIC=y
CONFIG_EFI_PARTITION=y
# CONFIG_PARTITION_UUIDS is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc"
CONFIG_DEFAULT_DEVICE_TREE="armada-385-db-88f6820-amc"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000

1
configs/db-mv784mp-gp_defconfig
View File

@ -46,6 +46,7 @@ CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_NAND=y
CONFIG_NAND_PXA3XX=y

55
configs/db-xc3-24g4xg_defconfig Normal file
View File

@ -0,0 +1,55 @@
CONFIG_ARM=y
CONFIG_ARCH_MVEBU=y
CONFIG_SYS_TEXT_BASE=0x00800000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_DB_XC3_24G4XG=y
CONFIG_BUILD_TARGET="u-boot.kwb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-db-xc3-24g4xg"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_BLK=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_DEVICE=y
CONFIG_NAND=y
CONFIG_NAND_PXA3XX=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y

2
configs/dns325_defconfig
View File

@ -30,6 +30,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-dns325"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_MVGBE=y
CONFIG_MII=y
@ -37,5 +38,6 @@ CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

2
configs/dreamplug_defconfig
View File

@ -27,6 +27,7 @@ CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
@ -40,5 +41,6 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

2
configs/ds109_defconfig
View File

@ -22,6 +22,7 @@ CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
# CONFIG_MMC is not set
@ -37,5 +38,6 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_FS_EXT4=y

1
configs/ds414_defconfig
View File

@ -43,6 +43,7 @@ CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y

2
configs/goflexhome_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-goflexnet"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_MVGBE=y
CONFIG_MII=y
@ -38,5 +39,6 @@ CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

2
configs/guruplug_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-guruplug-server-plus"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_MVGBE=y
CONFIG_MII=y
@ -38,6 +39,7 @@ CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y

6
configs/lschlv2_defconfig
View File

@ -16,7 +16,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
@ -26,7 +26,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lschlv2"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
@ -39,4 +40,5 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y

6
configs/lsxhl_defconfig
View File

@ -16,7 +16,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
@ -26,7 +26,8 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-lsxhl"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
@ -39,4 +40,5 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y

2
configs/nas220_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-blackarmor-nas220"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_BLK=y
# CONFIG_MMC is not set
CONFIG_MVGBE=y
CONFIG_MII=y
@ -38,5 +39,6 @@ CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

1
configs/sheevaplug_defconfig
View File

@ -39,6 +39,7 @@ CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_LZMA=y

1
configs/theadorable_debug_defconfig
View File

@ -51,6 +51,7 @@ CONFIG_ENV_SPI_MAX_HZ=50000000
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_SATA_MV=y
CONFIG_BLK=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_RAM=y
CONFIG_FPGA_ALTERA=y

1
configs/turris_omnia_defconfig
View File

@ -43,6 +43,7 @@ CONFIG_ATSHA204A=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y

5
configs/x530_defconfig
View File

@ -19,6 +19,8 @@ CONFIG_SILENT_CONSOLE=y
CONFIG_SILENT_U_BOOT_ONLY=y
CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
@ -72,3 +74,6 @@ CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_WATCHDOG=y
CONFIG_WDT=y
CONFIG_WDT_ORION=y

4
doc/git-mailrc
View File

@ -26,7 +26,6 @@ alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
alias jaehoon Jaehoon Chung <jh80.chung@samsung.com>
alias jagan Jagan Teki <jagan@openedev.com>
alias jhersh Joe Hershberger <joe.hershberger@ni.com>
alias luka Luka Perkov <luka.perkov@sartura.hr>
alias lukma Lukasz Majewski <lukma@denx.de>
alias macpaul Macpaul Lin <macpaul@andestech.com>
alias marex Marek Vasut <marex@denx.de>
@ -35,7 +34,6 @@ alias masahiro Masahiro Yamada <yamada.masahiro@socionext.com>
alias mateusz Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
alias maxime Maxime Ripard <maxime.ripard@free-electrons.com>
alias monstr Michal Simek <monstr@monstr.eu>
alias prafulla Prafulla Wadaskar <prafulla@marvell.com>
alias prom Minkyu Kang <mk7.kang@samsung.com>
alias ptomsich Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
alias sbabic Stefano Babic <sbabic@denx.de>
@ -56,7 +54,7 @@ alias arm uboot, aaribaud, trini
alias at91 uboot, abiessmann
alias davinci ti
alias imx uboot, sbabic
alias kirkwood uboot, prafulla, luka, stroese
alias kirkwood uboot, stroese
alias omap ti
alias pxa uboot, marex
alias rmobile uboot, iwamatsu

2
drivers/ata/Kconfig
View File

@ -81,7 +81,9 @@ config MVSATA_IDE
config SATA_MV
bool "Enable Marvell SATA controller driver support"
select AHCI
select LIBATA
depends on BLK
help
Enable this driver to support the SATA controller found in
some Marvell SoCs.

1
drivers/ata/ahci_mvebu.c
View File

@ -44,6 +44,7 @@ static int mvebu_ahci_probe(struct udevice *dev)
}
static const struct udevice_id mvebu_ahci_ids[] = {
{ .compatible = "marvell,armada-380-ahci" },
{ .compatible = "marvell,armada-3700-ahci" },
{ .compatible = "marvell,armada-8k-ahci" },
{ }

354
drivers/ata/sata_mv.c
View File

@ -3,7 +3,7 @@
* Copyright (C) Excito Elektronik i Skåne AB, 2010.
* Author: Tor Krill <tor@excito.com>
*
* Copyright (C) 2015 Stefan Roese <sr@denx.de>
* Copyright (C) 2015, 2019 Stefan Roese <sr@denx.de>
*/
/*
@ -32,6 +32,10 @@
*/
#include <common.h>
#include <ahci.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <fis.h>
#include <libata.h>
#include <malloc.h>
@ -40,11 +44,10 @@
#include <asm/io.h>
#include <linux/mbus.h>
#include <asm/arch/soc.h>
#if defined(CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
#define SATAHC_BASE KW_SATA_BASE
#else
#include <asm/arch/soc.h>
#define SATAHC_BASE MVEBU_AXP_SATA_BASE
#endif
@ -214,8 +217,8 @@ struct crqb {
#define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
#define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
#define MVSATA_WIN_CONTROL(w) (SATAHC_BASE + 0x30 + ((w) << 4))
#define MVSATA_WIN_BASE(w) (SATAHC_BASE + 0x34 + ((w) << 4))
struct eprd {
u32 phyaddr_low;
@ -256,6 +259,7 @@ struct mv_priv {
u16 pio;
u16 mwdma;
u16 udma;
int dev_nr;
void *crqb_alloc;
struct crqb *request;
@ -278,9 +282,9 @@ static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
}
/* Cut from sata_mv in linux kernel */
static int mv_stop_edma_engine(int port)
static int mv_stop_edma_engine(struct udevice *dev, int port)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
int i;
/* Disable eDMA. The disable bit auto clears. */
@ -299,9 +303,9 @@ static int mv_stop_edma_engine(int port)
return -1;
}
static int mv_start_edma_engine(int port)
static int mv_start_edma_engine(struct udevice *dev, int port)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
u32 tmp;
/* Check preconditions */
@ -351,12 +355,12 @@ static int mv_start_edma_engine(int port)
return 0;
}
static int mv_reset_channel(int port)
static int mv_reset_channel(struct udevice *dev, int port)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
/* Make sure edma is stopped */
mv_stop_edma_engine(port);
mv_stop_edma_engine(dev, port);
out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
udelay(25); /* allow reset propagation */
@ -366,11 +370,11 @@ static int mv_reset_channel(int port)
return 0;
}
static void mv_reset_port(int port)
static void mv_reset_port(struct udevice *dev, int port)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
mv_reset_channel(port);
mv_reset_channel(dev, port);
out_le32(priv->regbase + EDMA_CMD, 0x0);
out_le32(priv->regbase + EDMA_CFG, 0x101f);
@ -392,9 +396,9 @@ static void mv_reset_one_hc(void)
out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
}
static int probe_port(int port)
static int probe_port(struct udevice *dev, int port)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
int tries, tries2, set15 = 0;
u32 tmp;
@ -446,7 +450,7 @@ static int probe_port(int port)
tmp &= ~SIR_CFG_GEN2EN;
out_le32(priv->regbase + SIR_ICFG, tmp);
mv_reset_channel(port);
mv_reset_channel(dev, port);
}
}
@ -455,9 +459,9 @@ static int probe_port(int port)
}
/* Get request queue in pointer */
static int get_reqip(int port)
static int get_reqip(struct udevice *dev, int port)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
u32 tmp;
tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
@ -466,9 +470,9 @@ static int get_reqip(int port)
return tmp;
}
static void set_reqip(int port, int reqin)
static void set_reqip(struct udevice *dev, int port, int reqin)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
u32 tmp;
tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
@ -477,17 +481,17 @@ static void set_reqip(int port, int reqin)
}
/* Get next available slot, ignoring possible overwrite */
static int get_next_reqip(int port)
static int get_next_reqip(struct udevice *dev, int port)
{
int slot = get_reqip(port);
int slot = get_reqip(dev, port);
slot = (slot + 1) % REQUEST_QUEUE_SIZE;
return slot;
}
/* Get response queue in pointer */
static int get_rspip(int port)
static int get_rspip(struct udevice *dev, int port)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
u32 tmp;
tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
@ -497,9 +501,9 @@ static int get_rspip(int port)
}
/* Get response queue out pointer */
static int get_rspop(int port)
static int get_rspop(struct udevice *dev, int port)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
u32 tmp;
tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
@ -508,15 +512,15 @@ static int get_rspop(int port)
}
/* Get next response queue pointer */
static int get_next_rspop(int port)
static int get_next_rspop(struct udevice *dev, int port)
{
return (get_rspop(port) + 1) % RESPONSE_QUEUE_SIZE;
return (get_rspop(dev, port) + 1) % RESPONSE_QUEUE_SIZE;
}
/* Set response queue pointer */
static void set_rspop(int port, int reqin)
static void set_rspop(struct udevice *dev, int port, int reqin)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
u32 tmp;
tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
@ -525,7 +529,8 @@ static void set_rspop(int port, int reqin)
out_le32(priv->regbase + EDMA_RSOPR, tmp);
}
static int wait_dma_completion(int port, int index, u32 timeout_msec)
static int wait_dma_completion(struct udevice *dev, int port, int index,
u32 timeout_msec)
{
u32 tmp, res;
@ -538,13 +543,13 @@ static int wait_dma_completion(int port, int index, u32 timeout_msec)
return res;
}
static void process_responses(int port)
static void process_responses(struct udevice *dev, int port)
{
#ifdef DEBUG
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
#endif
u32 tmp;
u32 outind = get_rspop(port);
u32 outind = get_rspop(dev, port);
/* Ack interrupts */
tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
@ -555,20 +560,21 @@ static void process_responses(int port)
tmp &= ~(BIT(4));
out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
while (get_rspip(port) != outind) {
while (get_rspip(dev, port) != outind) {
#ifdef DEBUG
debug("Response index %d flags %08x on port %d\n", outind,
priv->response[outind].flags, port);
#endif
outind = get_next_rspop(port);
set_rspop(port, outind);
outind = get_next_rspop(dev, port);
set_rspop(dev, port, outind);
}
}
static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis,
static int mv_ata_exec_ata_cmd(struct udevice *dev, int port,
struct sata_fis_h2d *cfis,
u8 *buffer, u32 len, u32 iswrite)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
struct crqb *req;
int slot;
u32 start;
@ -579,7 +585,7 @@ static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis,
}
/* Initialize request */
slot = get_reqip(port);
slot = get_reqip(dev, port);
memset(&priv->request[slot], 0, sizeof(struct crqb));
req = &priv->request[slot];
@ -633,16 +639,16 @@ static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis,
start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
/* Trigger operation */
slot = get_next_reqip(port);
set_reqip(port, slot);
slot = get_next_reqip(dev, port);
set_reqip(dev, port, slot);
/* Wait for completion */
if (wait_dma_completion(port, slot, 10000)) {
if (wait_dma_completion(dev, port, slot, 10000)) {
printf("ATA operation timed out\n");
return -1;
}
process_responses(port);
process_responses(dev, port);
/* Invalidate data on read */
if (buffer && len) {
@ -654,7 +660,8 @@ static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis,
return len;
}
static u32 mv_sata_rw_cmd_ext(int port, lbaint_t start, u32 blkcnt,
static u32 mv_sata_rw_cmd_ext(struct udevice *dev, int port, lbaint_t start,
u32 blkcnt,
u8 *buffer, int is_write)
{
struct sata_fis_h2d cfis;
@ -678,14 +685,14 @@ static u32 mv_sata_rw_cmd_ext(int port, lbaint_t start, u32 blkcnt,
cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
cfis.sector_count = blkcnt & 0xff;
res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
is_write);
res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
ATA_SECT_SIZE * blkcnt, is_write);
return res >= 0 ? blkcnt : res;
}
static u32 mv_sata_rw_cmd(int port, lbaint_t start, u32 blkcnt, u8 *buffer,
int is_write)
static u32 mv_sata_rw_cmd(struct udevice *dev, int port, lbaint_t start,
u32 blkcnt, u8 *buffer, int is_write)
{
struct sata_fis_h2d cfis;
lbaint_t block;
@ -705,20 +712,21 @@ static u32 mv_sata_rw_cmd(int port, lbaint_t start, u32 blkcnt, u8 *buffer,
cfis.lba_low = block & 0xff;
cfis.sector_count = (u8)(blkcnt & 0xff);
res = mv_ata_exec_ata_cmd(port, &cfis, buffer, ATA_SECT_SIZE * blkcnt,
is_write);
res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
ATA_SECT_SIZE * blkcnt, is_write);
return res >= 0 ? blkcnt : res;
}
static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt,
void *buffer, int is_write)
static u32 ata_low_level_rw(struct udevice *dev, int port, lbaint_t blknr,
lbaint_t blkcnt, void *buffer, int is_write)
{
struct blk_desc *desc = dev_get_uclass_platdata(dev);
lbaint_t start, blks;
u8 *addr;
int max_blks;
debug("%s: %ld %ld\n", __func__, blknr, blkcnt);
debug("%s: " LBAFU " " LBAFU "\n", __func__, blknr, blkcnt);
start = blknr;
blks = blkcnt;
@ -727,22 +735,22 @@ static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt,
max_blks = MV_ATA_MAX_SECTORS;
do {
if (blks > max_blks) {
if (sata_dev_desc[dev].lba48) {
mv_sata_rw_cmd_ext(dev, start, max_blks, addr,
is_write);
if (desc->lba48) {
mv_sata_rw_cmd_ext(dev, port, start, max_blks,
addr, is_write);
} else {
mv_sata_rw_cmd(dev, start, max_blks, addr,
is_write);
mv_sata_rw_cmd(dev, port, start, max_blks,
addr, is_write);
}
start += max_blks;
blks -= max_blks;
addr += ATA_SECT_SIZE * max_blks;
} else {
if (sata_dev_desc[dev].lba48) {
mv_sata_rw_cmd_ext(dev, start, blks, addr,
if (desc->lba48) {
mv_sata_rw_cmd_ext(dev, port, start, blks, addr,
is_write);
} else {
mv_sata_rw_cmd(dev, start, blks, addr,
mv_sata_rw_cmd(dev, port, start, blks, addr,
is_write);
}
start += blks;
@ -754,11 +762,11 @@ static u32 ata_low_level_rw(int dev, lbaint_t blknr, lbaint_t blkcnt,
return blkcnt;
}
static int mv_ata_exec_ata_cmd_nondma(int port,
static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port,
struct sata_fis_h2d *cfis, u8 *buffer,
u32 len, u32 iswrite)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
int i;
u16 *tp;
@ -791,7 +799,7 @@ static int mv_ata_exec_ata_cmd_nondma(int port,
return len;
}
static int mv_sata_identify(int port, u16 *id)
static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
{
struct sata_fis_h2d h2d;
@ -803,13 +811,13 @@ static int mv_sata_identify(int port, u16 *id)
/* Give device time to get operational */
mdelay(10);
return mv_ata_exec_ata_cmd_nondma(port, &h2d, (u8 *)id,
return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
ATA_ID_WORDS * 2, READ_CMD);
}
static void mv_sata_xfer_mode(int port, u16 *id)
static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
priv->pio = id[ATA_ID_PIO_MODES];
priv->mwdma = id[ATA_ID_MWDMA_MODES];
@ -818,9 +826,9 @@ static void mv_sata_xfer_mode(int port, u16 *id)
priv->udma);
}
static void mv_sata_set_features(int port)
static void mv_sata_set_features(struct udevice *dev, int port)
{
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
struct mv_priv *priv = dev_get_platdata(dev);
struct sata_fis_h2d cfis;
u8 udma_cap;
@ -842,53 +850,7 @@ static void mv_sata_set_features(int port)
if (udma_cap == ATA_UDMA3)
cfis.sector_count = XFER_UDMA_3;
mv_ata_exec_ata_cmd_nondma(port, &cfis, NULL, 0, READ_CMD);
}
int mv_sata_spin_down(int dev)
{
struct sata_fis_h2d cfis;
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
if (priv->link == 0) {
debug("No device on port: %d\n", dev);
return 1;
}
memset(&cfis, 0, sizeof(struct sata_fis_h2d));
cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis.command = ATA_CMD_STANDBY;
return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
}
int mv_sata_spin_up(int dev)
{
struct sata_fis_h2d cfis;
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[dev].priv;
if (priv->link == 0) {
debug("No device on port: %d\n", dev);
return 1;
}
memset(&cfis, 0, sizeof(struct sata_fis_h2d));
cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis.command = ATA_CMD_IDLE;
return mv_ata_exec_ata_cmd_nondma(dev, &cfis, NULL, 0, READ_CMD);
}
ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
return ata_low_level_rw(dev, blknr, blkcnt, buffer, READ_CMD);
}
ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
return ata_low_level_rw(dev, blknr, blkcnt, (void *)buffer, WRITE_CMD);
mv_ata_exec_ata_cmd_nondma(dev, port, &cfis, NULL, 0, READ_CMD);
}
/*
@ -916,25 +878,17 @@ static void mvsata_ide_conf_mbus_windows(void)
}
}
int init_sata(int dev)
static int sata_mv_init_sata(struct udevice *dev, int port)
{
struct mv_priv *priv;
struct mv_priv *priv = dev_get_platdata(dev);
debug("Initialize sata dev: %d\n", dev);
debug("Initialize sata dev: %d\n", port);
if (dev < 0 || dev >= CONFIG_SYS_SATA_MAX_DEVICE) {
printf("Invalid sata device %d\n", dev);
if (port < 0 || port >= CONFIG_SYS_SATA_MAX_DEVICE) {
printf("Invalid sata device %d\n", port);
return -1;
}
priv = (struct mv_priv *)malloc(sizeof(struct mv_priv));
if (!priv) {
printf("Failed to allocate memory for private sata data\n");
return -ENOMEM;
}
memset((void *)priv, 0, sizeof(struct mv_priv));
/* Allocate and align request buffer */
priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
CRQB_ALIGN);
@ -959,11 +913,9 @@ int init_sata(int dev)
priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
~(CRPB_ALIGN - 1));
sata_dev_desc[dev].priv = (void *)priv;
sprintf(priv->name, "SATA%d", port);
sprintf(priv->name, "SATA%d", dev);
priv->regbase = dev == 0 ? SATA0_BASE : SATA1_BASE;
priv->regbase = port == 0 ? SATA0_BASE : SATA1_BASE;
if (!hw_init) {
debug("Initialize sata hw\n");
@ -972,9 +924,9 @@ int init_sata(int dev)
mvsata_ide_conf_mbus_windows();
}
mv_reset_port(dev);
mv_reset_port(dev, port);
if (probe_port(dev)) {
if (probe_port(dev, port)) {
priv->link = 0;
return -ENODEV;
}
@ -983,19 +935,15 @@ int init_sata(int dev)
return 0;
}
int reset_sata(int dev)
{
return 0;
}
int scan_sata(int port)
static int sata_mv_scan_sata(struct udevice *dev, int port)
{
struct blk_desc *desc = dev_get_uclass_platdata(dev);
struct mv_priv *priv = dev_get_platdata(dev);
unsigned char serial[ATA_ID_SERNO_LEN + 1];
unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
unsigned char product[ATA_ID_PROD_LEN + 1];
u64 n_sectors;
u16 *id;
struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv;
if (!priv->link)
return -ENODEV;
@ -1006,7 +954,7 @@ int scan_sata(int port)
return -ENOMEM;
}
mv_sata_identify(port, id);
mv_sata_identify(dev, port, id);
ata_swap_buf_le16(id, ATA_ID_WORDS);
#ifdef DEBUG
ata_dump_id(id);
@ -1014,23 +962,23 @@ int scan_sata(int port)
/* Serial number */
ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
memcpy(sata_dev_desc[port].product, serial, sizeof(serial));
memcpy(desc->product, serial, sizeof(serial));
/* Firmware version */
ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
memcpy(sata_dev_desc[port].revision, firmware, sizeof(firmware));
memcpy(desc->revision, firmware, sizeof(firmware));
/* Product model */
ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
memcpy(sata_dev_desc[port].vendor, product, sizeof(product));
memcpy(desc->vendor, product, sizeof(product));
/* Total sectors */
n_sectors = ata_id_n_sectors(id);
sata_dev_desc[port].lba = n_sectors;
desc->lba = n_sectors;
/* Check if support LBA48 */
if (ata_id_has_lba48(id)) {
sata_dev_desc[port].lba48 = 1;
desc->lba48 = 1;
debug("Device support LBA48\n");
}
@ -1038,13 +986,111 @@ int scan_sata(int port)
priv->queue_depth = ata_id_queue_depth(id);
/* Get the xfer mode from device */
mv_sata_xfer_mode(port, id);
mv_sata_xfer_mode(dev, port, id);
/* Set the xfer mode to highest speed */
mv_sata_set_features(port);
mv_sata_set_features(dev, port);
/* Start up */
mv_start_edma_engine(port);
mv_start_edma_engine(dev, port);
return 0;
}
static ulong sata_mv_read(struct udevice *blk, lbaint_t blknr,
lbaint_t blkcnt, void *buffer)
{
struct mv_priv *priv = dev_get_platdata(blk);
return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
buffer, READ_CMD);
}
static ulong sata_mv_write(struct udevice *blk, lbaint_t blknr,
lbaint_t blkcnt, const void *buffer)
{
struct mv_priv *priv = dev_get_platdata(blk);
return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
(void *)buffer, WRITE_CMD);
}
static const struct blk_ops sata_mv_blk_ops = {
.read = sata_mv_read,
.write = sata_mv_write,
};
U_BOOT_DRIVER(sata_mv_driver) = {
.name = "sata_mv_blk",
.id = UCLASS_BLK,
.ops = &sata_mv_blk_ops,
.platdata_auto_alloc_size = sizeof(struct mv_priv),
};
static int sata_mv_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
struct mv_priv *priv;
struct udevice *blk;
int nr_ports;
int ret;
int i;
/* Get number of ports of this SATA controller */
nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
CONFIG_SYS_SATA_MAX_DEVICE);
for (i = 0; i < nr_ports; i++) {
ret = blk_create_devicef(dev, "sata_mv_blk", "blk",
IF_TYPE_SATA, -1, 512, 0, &blk);
if (ret) {
debug("Can't create device\n");
return ret;
}
priv = dev_get_platdata(blk);
priv->dev_nr = i;
/* Init SATA port */
ret = sata_mv_init_sata(blk, i);
if (ret) {
debug("%s: Failed to init bus\n", __func__);
return ret;
}
/* Scan SATA port */
ret = sata_mv_scan_sata(blk, i);
if (ret) {
debug("%s: Failed to scan bus\n", __func__);
return ret;
}
}
return 0;
}
static int sata_mv_scan(struct udevice *dev)
{
/* Nothing to do here */
return 0;
}
static const struct udevice_id sata_mv_ids[] = {
{ .compatible = "marvell,armada-370-sata" },
{ .compatible = "marvell,orion-sata" },
{ }
};
struct ahci_ops sata_mv_ahci_ops = {
.scan = sata_mv_scan,
};
U_BOOT_DRIVER(sata_mv_ahci) = {
.name = "sata_mv_ahci",
.id = UCLASS_AHCI,
.of_match = sata_mv_ids,
.ops = &sata_mv_ahci_ops,
.probe = sata_mv_probe,
};

4
drivers/ddr/marvell/axp/xor_regs.h
View File

@ -13,7 +13,11 @@
#define XOR_UNIT(chan) ((chan) >> 1)
#define XOR_CHAN(chan) ((chan) & 1)
#ifdef CONFIG_ARMADA_MSYS
#define MV_XOR_REGS_OFFSET(unit) (0xF0800)
#else
#define MV_XOR_REGS_OFFSET(unit) (0x60900)
#endif
#define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit))
/* XOR Engine Control Register Map */

1
drivers/watchdog/Kconfig
View File

@ -97,6 +97,7 @@ config WDT_BCM6345
config WDT_ORION
bool "Orion watchdog timer support"
depends on WDT
select CLK
help
Select this to enable Orion watchdog timer, which can be found on some
Marvell Armada chips.

27
drivers/watchdog/orion_wdt.c
View File

@ -14,7 +14,9 @@
#include <common.h>
#include <dm.h>
#include <clk.h>
#include <wdt.h>
#include <linux/kernel.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
@ -27,6 +29,8 @@ struct orion_wdt_priv {
void __iomem *rstout;
void __iomem *rstout_mask;
u32 timeout;
unsigned long clk_rate;
struct clk clk;
};
#define RSTOUT_ENABLE_BIT BIT(8)
@ -44,17 +48,18 @@ static int orion_wdt_reset(struct udevice *dev)
struct orion_wdt_priv *priv = dev_get_priv(dev);
/* Reload watchdog duration */
writel(priv->timeout, priv->reg + priv->wdt_counter_offset);
writel(priv->clk_rate * priv->timeout,
priv->reg + priv->wdt_counter_offset);
return 0;
}
static int orion_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
static int orion_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
struct orion_wdt_priv *priv = dev_get_priv(dev);
u32 reg;
priv->timeout = (u32) timeout;
priv->timeout = DIV_ROUND_UP(timeout_ms, 1000);
/* Enable the fixed watchdog clock input */
reg = readl(priv->reg + TIMER_CTRL);
@ -62,7 +67,8 @@ static int orion_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
writel(reg, priv->reg + TIMER_CTRL);
/* Set watchdog duration */
writel(priv->timeout, priv->reg + priv->wdt_counter_offset);
writel(priv->clk_rate * priv->timeout,
priv->reg + priv->wdt_counter_offset);
/* Clear the watchdog expiration bit */
reg = readl(priv->reg + TIMER_A370_STATUS);
@ -114,9 +120,7 @@ static inline bool save_reg_from_ofdata(struct udevice *dev, int index,
fdt_addr_t addr;
fdt_size_t off;
addr = fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, dev_of_offset(dev), "reg", index, &off, true);
addr = devfdt_get_addr_size_index(dev, index, &off);
if (addr == FDT_ADDR_T_NONE)
return false;
@ -149,9 +153,18 @@ err:
static int orion_wdt_probe(struct udevice *dev)
{
struct orion_wdt_priv *priv = dev_get_priv(dev);
int ret;
debug("%s: Probing wdt%u\n", __func__, dev->seq);
orion_wdt_stop(dev);
ret = clk_get_by_name(dev, "fixed", &priv->clk);
if (!ret)
priv->clk_rate = clk_get_rate(&priv->clk);
else
priv->clk_rate = 25000000;
return 0;
}

2
include/configs/clearfog.h
View File

@ -21,8 +21,6 @@
* Commands configuration
*/
/* SPI NOR flash default params, used by sf commands */
/*
* SDIO/MMC Card Configuration
*/

2
include/configs/db-88f6720.h
View File

@ -32,8 +32,6 @@
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* SPI NOR flash default params, used by sf commands */
/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */

2
include/configs/db-88f6820-amc.h
View File

@ -16,8 +16,6 @@
* Commands configuration
*/
/* SPI NOR flash default params, used by sf commands */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

6
include/configs/db-88f6820-gp.h
View File

@ -23,12 +23,6 @@
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000
/*
* SPI Flash configuration for the environemnt access
*/
/* SPI NOR flash default params, used by sf commands */
/*
* SDIO/MMC Card Configuration
*/

2
include/configs/db-mv784mp-gp.h
View File

@ -29,8 +29,6 @@
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* SPI NOR flash default params, used by sf commands */
/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */

41
include/configs/db-xc3-24g4xg.h Normal file
View File

@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
*/
#ifndef _CONFIG_DB_XC3_24G4G_H
#define _CONFIG_DB_XC3_24G4G_H
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
/* NAND */
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x10000000\0" \
"initrd_high=0x10000000\0"
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 96
#endif /* _CONFIG_DB_XC3_24G4G_H */

2
include/configs/ds414.h
View File

@ -28,8 +28,6 @@
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000
/* SPI NOR flash default params, used by sf commands */
/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */

2
include/configs/helios4.h
View File

@ -23,8 +23,6 @@
* Commands configuration
*/
/* SPI NOR flash default params, used by sf commands */
/*
* SDIO/MMC Card Configuration
*/

23
include/configs/lsxl.h
View File

@ -76,9 +76,9 @@
"kernel_addr=0x00800000\0" \
"ramdisk_addr=0x01000000\0" \
"fdt_addr=0x00ff0000\0" \
"bootcmd_legacy=ide reset " \
"&& load ide ${hdpart} ${kernel_addr} /uImage.buffalo " \
"&& load ide ${hdpart} ${ramdisk_addr} /initrd.buffalo "\
"bootcmd_legacy=sata init " \
"&& load sata ${hdpart} ${kernel_addr} /uImage.buffalo "\
"&& load sata ${hdpart} ${ramdisk_addr} /initrd.buffalo "\
"&& bootm ${kernel_addr} ${ramdisk_addr}\0" \
"bootcmd_net=bootp ${kernel_addr} vmlinuz " \
"&& tftpboot ${ramdisk_addr} initrd.img " \
@ -86,11 +86,11 @@
"&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \
"&& bootz ${kernel_addr} " \
"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \
"bootcmd_hdd=ide reset " \
"&& load ide ${hdpart} ${kernel_addr} /vmlinuz " \
"&& load ide ${hdpart} ${ramdisk_addr} /initrd.img " \
"bootcmd_hdd=sata init " \
"&& load sata ${hdpart} ${kernel_addr} /vmlinuz " \
"&& load sata ${hdpart} ${ramdisk_addr} /initrd.img " \
"&& setenv ramdisk_len ${filesize} " \
"&& load ide ${hdpart} ${fdt_addr} /dtb " \
"&& load sata ${hdpart} ${fdt_addr} /dtb " \
"&& bootz ${kernel_addr} " \
"${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \
"bootcmd_usb=usb start " \
@ -131,13 +131,10 @@
#undef CONFIG_RESET_PHY_R
#endif /* CONFIG_CMD_NET */
#ifdef CONFIG_IDE
#undef CONFIG_SYS_IDE_MAXBUS
#define CONFIG_SYS_IDE_MAXBUS 1
#undef CONFIG_SYS_IDE_MAXDEVICE
#define CONFIG_SYS_IDE_MAXDEVICE 1
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#ifdef CONFIG_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_SYS_64BIT_LBA
#define CONFIG_LBA48
#endif
#endif /* _CONFIG_LSXL_H */

4
include/configs/mvebu_armada-8k.h
View File

@ -49,10 +49,6 @@
/* End of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000)
/*
* SPI Flash configuration
*/
#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */

2
include/configs/theadorable.h
View File

@ -39,8 +39,6 @@
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
/* SPI NOR flash default params, used by sf commands */
/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */

4
include/configs/turris_mox.h
View File

@ -63,10 +63,6 @@
#define CONFIG_I2C_MV
#define CONFIG_SYS_I2C_SLAVE 0x0
/*
* SPI Flash configuration
*/
/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */

3
include/configs/turris_omnia.h
View File

@ -34,9 +34,6 @@
# define CONFIG_WATCHDOG
#endif
/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SPI_FLASH_SPANSION
/*
* SDIO/MMC Card Configuration
*/

7
tools/kwbimage.c
View File

@ -1273,6 +1273,13 @@ static void *image_create_v1(size_t *imagesz, struct image_tool_params *params,
e = image_find_option(IMAGE_CFG_DEBUG);
if (e)
main_hdr->flags = e->debug ? 0x1 : 0;
e = image_find_option(IMAGE_CFG_BINARY);
if (e) {
char *s = strrchr(e->binary.file, '/');
if (strcmp(s, "/binary.0") == 0)
main_hdr->destaddr = cpu_to_le32(params->addr);
}
#if defined(CONFIG_KWB_SECURE)
if (image_get_csk_index() >= 0) {