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pci: layerscape: Only set EP CFG READY bit

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In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.

While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.

Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Pankaj Bansal 2019-10-14 11:43:19 +00:00 committed by Priyanka Jain
parent d911087889
commit 05c81d98e4
1 changed files with 5 additions and 1 deletions
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6
drivers/pci/pcie_layerscape.c
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@ -406,7 +406,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base)
static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
{
ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
u32 config;
config = ctrl_readl(pcie, PCIE_PF_CONFIG);
config |= PCIE_CONFIG_READY;
ctrl_writel(pcie, config, PCIE_PF_CONFIG);
}
static void ls_pcie_setup_ep(struct ls_pcie *pcie)