mx7ulp: Add support for Embedded Artists COM board
The Embedded Artists COM board is based on NXP i.MX7ULP. It has a BD70528 PMIC from Rohm with discrete DCDC powering option and improved current observability (compared to the existing NXP i.MX7ULP EVK). Add the initial support for the board. Signed-off-by: Fabio Estevam <festevam@gmail.com>
This commit is contained in:
Fabio Estevam
Stefano Babic
parent
97c4275771
commit
0417ef17ac
@ -688,7 +688,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
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imx7d-pico-hobbit.dtb
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dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
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dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
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imx7ulp-evk.dtb
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dtb-$(CONFIG_ARCH_IMX8) += \
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fsl-imx8qm-apalis.dtb \
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90
arch/arm/dts/imx7ulp-com.dts
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90
arch/arm/dts/imx7ulp-com.dts
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@ -0,0 +1,90 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2019 NXP
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// Author: Fabio Estevam <fabio.estevam@nxp.com>
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/dts-v1/;
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#include "imx7ulp.dtsi"
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/ {
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model = "Embedded Artists i.MX7ULP COM";
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compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
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chosen {
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stdout-path = &lpuart4;
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};
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memory {
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device_type = "memory";
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reg = <0x60000000 0x8000000>;
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};
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};
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&lpuart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart4>;
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_id>;
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usbphy1 {
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fsl,tx-d-cal = <88>;
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};
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&usdhc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0>;
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non-removable;
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bus-width = <8>;
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no-1-8-v;
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status = "okay";
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};
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&iomuxc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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IMX7ULP_PAD_PTC1__PTC1 0x20000
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>;
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};
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
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IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
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IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
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IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
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IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
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IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
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IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
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IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
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IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
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IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
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IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
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>;
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};
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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IMX7ULP_PAD_PTC13__USB0_ID 0x10003
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>;
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};
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};
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@ -15,6 +15,11 @@ choice
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prompt "MX7ULP board select"
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optional
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config TARGET_MX7ULP_COM
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bool "Support MX7ULP COM board"
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select MX7ULP
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select SYS_ARCH_TIMER
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config TARGET_MX7ULP_EVK
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bool "Support mx7ulp EVK board"
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select MX7ULP
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@ -22,6 +27,7 @@ config TARGET_MX7ULP_EVK
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endchoice
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source "board/ea/mx7ulp_com/Kconfig"
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source "board/freescale/mx7ulp_evk/Kconfig"
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endif
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12
board/ea/mx7ulp_com/Kconfig
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12
board/ea/mx7ulp_com/Kconfig
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@ -0,0 +1,12 @@
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if TARGET_MX7ULP_COM
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config SYS_BOARD
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default "mx7ulp_com"
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config SYS_VENDOR
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default "ea"
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config SYS_CONFIG_NAME
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default "mx7ulp_com"
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endif
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6
board/ea/mx7ulp_com/MAINTAINERS
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6
board/ea/mx7ulp_com/MAINTAINERS
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@ -0,0 +1,6 @@
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MX7ULPCOM BOARD
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M: Fabio Estevam <festevam@gmail.com>
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S: Maintained
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F: board/ea/mx7ulp_com/
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F: include/configs/mx7ulp_com.h
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F: configs/mx7ulp_com_defconfig
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6
board/ea/mx7ulp_com/Makefile
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6
board/ea/mx7ulp_com/Makefile
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@ -0,0 +1,6 @@
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# (C) Copyright 2016 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx7ulp_com.o
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137
board/ea/mx7ulp_com/imximage.cfg
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137
board/ea/mx7ulp_com/imximage.cfg
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@ -0,0 +1,137 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi/sd/nand/onenand, qspi/nor
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*/
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BOOT_FROM sd
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x403f00dc 0x00000000
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DATA 4 0x403e0040 0x01000020
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DATA 4 0x403e0500 0x01000000
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DATA 4 0x403e050c 0x80808080
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DATA 4 0x403e0508 0x00160002
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DATA 4 0x403E0510 0x00000001
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DATA 4 0x403E0514 0x00000014
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DATA 4 0x403e0500 0x00000001
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CHECK_BITS_SET 4 0x403e0500 0x01000000
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/*
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* Default PFD0 divide is 27, which generates:
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* PFD0 Freq = A7 APLL (528MHz) * 18 / 27 = 352MHz
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*
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* i.MX7ULP COM board can not run DDR at 352MHz, so
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* use a divider of 30 (0x1E), which gives:
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*
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* PFD0 Freq = A7 APLL (528MHz) * 18 / 30 = 316.8MHz
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*/
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DATA 4 0x403e050c 0x8080801E
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CHECK_BITS_SET 4 0x403e050c 0x00000040
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DATA 4 0x403E0030 0x00000001
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DATA 4 0x403e0040 0x11000020
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DATA 4 0x403f00dc 0x42000000
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DATA 4 0x40B300AC 0x40000000
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DATA 4 0x40AD0128 0x00040000
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DATA 4 0x40AD00F8 0x00000000
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DATA 4 0x40AD00D8 0x00000180
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DATA 4 0x40AD0104 0x00000180
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DATA 4 0x40AD0108 0x00000180
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DATA 4 0x40AD0124 0x00010000
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DATA 4 0x40AD0080 0x0000018C
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DATA 4 0x40AD0084 0x0000018C
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DATA 4 0x40AD0088 0x0000018C
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DATA 4 0x40AD008C 0x0000018C
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DATA 4 0x40AD0120 0x00010000
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DATA 4 0x40AD010C 0x00000180
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DATA 4 0x40AD0110 0x00000180
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DATA 4 0x40AD0114 0x00000180
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DATA 4 0x40AD0118 0x00000180
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DATA 4 0x40AD0090 0x00000180
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DATA 4 0x40AD0094 0x00000180
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DATA 4 0x40AD0098 0x00000180
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DATA 4 0x40AD009C 0x00000180
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DATA 4 0x40AD00E0 0x00040000
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DATA 4 0x40AD00E4 0x00040000
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DATA 4 0x40AB001C 0x00008000
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DATA 4 0x40AB085C 0x0D3900A0
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DATA 4 0x40AB0800 0xA1390003
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DATA 4 0x40AB0890 0x00400000
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DATA 4 0x40AB081C 0x33333333
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DATA 4 0x40AB0820 0x33333333
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DATA 4 0x40AB0824 0x33333333
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DATA 4 0x40AB0828 0x33333333
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DATA 4 0x40AB08C0 0x24922492
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DATA 4 0x40AB0848 0x3A3E3838
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DATA 4 0x40AB0850 0x28282C2A
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DATA 4 0x40AB083C 0x20000000
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DATA 4 0x40AB0840 0x00000000
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DATA 4 0x40AB08B8 0x00000800
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DATA 4 0x40AB000C 0x292C40F5
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DATA 4 0x40AB0004 0x00020064
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DATA 4 0x40AB0010 0xB6AD0A83
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DATA 4 0x40AB0014 0x00C70093
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DATA 4 0x40AB0018 0x00211708
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DATA 4 0x40AB002C 0x0F9F26D2
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DATA 4 0x40AB0030 0x009F0E10
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DATA 4 0x40AB0038 0x00130556
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DATA 4 0x40AB0008 0x12272000
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DATA 4 0x40AB0040 0x0000003F
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DATA 4 0x40AB0000 0xC3110000
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DATA 4 0x40AB001C 0x00008010
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DATA 4 0x40AB001C 0x00008018
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DATA 4 0x40AB001C 0x003F8030
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DATA 4 0x40AB001C 0xFF0A8030
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DATA 4 0x40AB001C 0x82018030
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DATA 4 0x40AB001C 0x06028030
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DATA 4 0x40AB001C 0x01038030
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DATA 4 0x40AB001C 0x003F8038
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DATA 4 0x40AB001C 0xFF0A8038
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DATA 4 0x40AB001C 0x82018038
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DATA 4 0x40AB001C 0x06028038
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DATA 4 0x40AB001C 0x01038038
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DATA 4 0x40AB083C 0xA0000000
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DATA 4 0x40AB083C 0xA0000000
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DATA 4 0x40AB0020 0x00001800
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DATA 4 0x40AB0800 0xA1310003
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DATA 4 0x40AB001C 0x00000000
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#endif
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48
board/ea/mx7ulp_com/mx7ulp_com.c
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48
board/ea/mx7ulp_com/mx7ulp_com.c
Normal file
@ -0,0 +1,48 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mx7ulp-pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_cfg_t const lpuart4_pads[] = {
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MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
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ARRAY_SIZE(lpuart4_pads));
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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60
configs/mx7ulp_com_defconfig
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60
configs/mx7ulp_com_defconfig
Normal file
@ -0,0 +1,60 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX7ULP=y
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CONFIG_SYS_TEXT_BASE=0x67800000
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CONFIG_LDO_ENABLED_MODE=y
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CONFIG_TARGET_MX7ULP_COM=y
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0xC0000
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ea/mx7ulp_com/imximage.cfg"
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CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
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CONFIG_BOUNCE_BUFFER=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_READ=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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CONFIG_CMD_FAT=y
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CONFIG_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
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CONFIG_ENV_IS_IN_MMC=y
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# CONFIG_NET is not set
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CONFIG_DM=y
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CONFIG_DM_GPIO=y
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CONFIG_IMX_RGPIO2P=y
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# CONFIG_MXC_GPIO is not set
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_IMX_LPI2C=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_USDHC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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CONFIG_SF_DEFAULT_SPEED=40000000
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CONFIG_SPI_FLASH_ATMEL=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX7ULP=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_DM_SERIAL=y
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CONFIG_FSL_LPUART=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_QSPI=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_MANUFACTURER="FSL"
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CONFIG_USB_GADGET_VENDOR_NUM=0x0525
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CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
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CONFIG_CI_UDC=y
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CONFIG_USB_GADGET_DOWNLOAD=y
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CONFIG_ULP_WATCHDOG=y
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103
include/configs/mx7ulp_com.h
Normal file
103
include/configs/mx7ulp_com.h
Normal file
@ -0,0 +1,103 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Embedded Artists i.MX7ULP COM board.
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*/
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#ifndef __MX7ULP_COM_CONFIG_H
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#define __MX7ULP_COM_CONFIG_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_BOARD_POSTCLK_INIT
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#define CONFIG_SYS_BOOTM_LEN 0x1000000
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#define SRC_BASE_ADDR CMC1_RBASE
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#define IRAM_BASE_ADDR OCRAM_0_BASE
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#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
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/*
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* Detect overlap between U-Boot image and environment area in build-time
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*
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* CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot-dtb.imx offset
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* CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
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*
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* Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
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* write the direct value here
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*/
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#define CONFIG_BOARD_SIZE_LIMIT 785408
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_MMCROOT "/dev/mmcblk0p2"
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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|
||||
/* Using ULP WDOG for reset */
|
||||
#define WDOG_BASE_ADDR WDG1_RBASE
|
||||
|
||||
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */
|
||||
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
|
||||
|
||||
/* UART */
|
||||
#define LPUART_BASE LPUART4_RBASE
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Physical Memory Map */
|
||||
|
||||
#define PHYS_SDRAM 0x60000000
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
|
||||
#define CONFIG_LOADADDR 0x60800000
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"image=zImage\0" \
|
||||
"console=ttyLP0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx7ulp-com.dtb\0" \
|
||||
"fdt_addr=0x63000000\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"fi;\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"fi; " \
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
|
||||
#define CONFIG_CMD_CACHE
|
||||
#endif
|
||||
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user