Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
This commit is contained in:
Wolfgang Denk
commit
02c631e6ee
@ -36,6 +36,7 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
mecp5200 MPC5200
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pf5200 MPC5200
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caddy2 MPC8349
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vme8349 MPC8349
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CPCI750 PPC750FX/GX
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2
MAKEALL
2
MAKEALL
@ -358,10 +358,12 @@ LIST_8260=" \
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#########################################################################
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LIST_83xx=" \
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caddy2 \
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kmeter1 \
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MPC8313ERDB_33 \
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MPC8313ERDB_NAND_66 \
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MPC8315ERDB \
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MPC8315ERDB_NAND \
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MPC8323ERDB \
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MPC832XEMDS \
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MPC832XEMDS_ATM \
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9
Makefile
9
Makefile
@ -2261,8 +2261,12 @@ MPC8313ERDB_NAND_66_config: unconfig
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echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
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fi ;
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MPC8315ERDB_NAND_config \
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MPC8315ERDB_config: unconfig
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@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
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@if [ "$(findstring _NAND_,$@)" ] ; then \
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ln -sf mpc8313erdb nand_spl/board/freescale/mpc8315erdb ; \
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fi ;
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@$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
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MPC8323ERDB_config: unconfig
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@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
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@ -2396,8 +2400,9 @@ SIMPC8313_SP_config: unconfig
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TQM834x_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
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caddy2_config \
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vme8349_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
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@$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
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#########################################################################
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## MPC85xx Systems
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@ -2,6 +2,9 @@
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* pci.c -- esd VME8349 PCI board support.
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* Copyright (c) 2006 Wind River Systems, Inc.
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 esd gmbh.
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*
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* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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*
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* Based on MPC8349 PCI support but w/o PIB related code.
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*
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@ -32,6 +35,7 @@
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#include <pci.h>
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#include <i2c.h>
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#include <asm/fsl_i2c.h>
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#include "vme8349pin.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -93,17 +97,22 @@ pci_init_board(void)
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udelay(2000);
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/*
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* Assert/deassert PCI reset
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* Assert/deassert VME reset
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*/
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setbits_be32(&immr->gpio[0].dat, 0x00800000);
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setbits_be32(&immr->gpio[0].dir, 0x00800000);
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setbits_be32(&immr->gpio[1].dir, 0x08800000);
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clrsetbits_be32(&immr->gpio[1].dat,
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GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
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GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
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setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
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GPIO2_TSI_POWERUP_RESET_N |
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GPIO2_VME_RESET_N |
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GPIO2_L_RESET_EN_N);
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clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
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udelay(200);
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setbits_be32(&immr->gpio[1].dat, 0x08000000);
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setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
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udelay(200);
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setbits_be32(&immr->gpio[1].dat, 0x08800000);
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setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
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udelay(600000);
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clrbits_be32(&immr->gpio[1].dat, 0x00100000);
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clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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@ -114,6 +123,14 @@ pci_init_board(void)
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udelay(2000);
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if (monarch == 0)
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if (monarch == 0) {
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mpc83xx_pci_init(1, reg, 0);
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} else {
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/*
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* Release PCI RST Output signal
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*/
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out_be32(&immr->pci_ctrl[0].gcr, 0);
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udelay(2000);
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out_be32(&immr->pci_ctrl[0].gcr, 1);
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}
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}
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@ -38,63 +38,13 @@
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#endif
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <spd.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include <netdev.h>
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void ddr_enable_ecc(unsigned int dram_size);
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CONFIG_SYS_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1);
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ddr_size = ddr_size>>1, ddr_size_log2++) {
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if (ddr_size & 1)
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return -1;
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}
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
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LAWAR_SIZE);
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#if (CONFIG_SYS_DDR_SIZE == 512)
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im->ddr.csbnds[0].csbnds = 0x0000001f;
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#else
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#warning Currently any DDR size other than 512MiB is not supported
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#endif
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000;
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/* currently we use only one CS, so disable the other banks */
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im->ddr.csbnds[1].csbnds = 0x00000000;
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im->ddr.csbnds[2].csbnds = 0x00000000;
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im->ddr.csbnds[3].csbnds = 0x00000000;
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im->ddr.cs_config[1] = 0;
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im->ddr.cs_config[2] = 0;
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im->ddr.cs_config[3] = 0;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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sync();
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udelay(200);
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/* enable DDR controller */
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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@ -103,10 +53,10 @@ phys_size_t initdram(int board_type)
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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/* DDR SDRAM - Main memory */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
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msize = fixed_sdram();
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msize = spd_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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@ -124,17 +74,148 @@ phys_size_t initdram(int board_type)
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int checkboard(void)
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{
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puts("Board: esd VME8349\n");
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#ifdef VME_CADDY2
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puts("Board: esd VME-CADDY/2\n");
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#else
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puts("Board: esd VME-CPU/8349\n");
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#endif
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return 0;
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}
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#ifdef VME_CADDY2
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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}
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#endif
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int misc_init_r()
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
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return 0;
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}
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/*
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* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
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* and VME-CADDY/2) have different SDRAM configurations.
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*/
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#ifdef VME_CADDY2
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#define SMALL_RAM 0xff
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#define LARGE_RAM 0x00
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#else
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#define SMALL_RAM 0x00
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#define LARGE_RAM 0xff
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#endif
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#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
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static spd_eeprom_t default_spd_eeprom = {
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SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
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SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
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SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
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SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
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SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
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SPD_VAL(0x00, 0x00), /* 05 */
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SPD_VAL(0x40, 0x40), /* 06 */
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SPD_VAL(0x00, 0x00), /* 07 */
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SPD_VAL(0x05, 0x05), /* 08 */
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SPD_VAL(0x30, 0x30), /* 09 */
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SPD_VAL(0x45, 0x45), /* 10 */
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SPD_VAL(0x02, 0x02), /* 11 ecc used */
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||||
SPD_VAL(0x82, 0x82), /* 12 */
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SPD_VAL(0x10, 0x10), /* 13 */
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SPD_VAL(0x08, 0x08), /* 14 */
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||||
SPD_VAL(0x00, 0x00), /* 15 */
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SPD_VAL(0x0c, 0x0c), /* 16 */
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SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
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SPD_VAL(0x38, 0x38), /* 18 */
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||||
SPD_VAL(0x00, 0x00), /* 19 */
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||||
SPD_VAL(0x02, 0x02), /* 20 */
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||||
SPD_VAL(0x00, 0x00), /* 21 */
|
||||
SPD_VAL(0x03, 0x03), /* 22 */
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||||
SPD_VAL(0x3d, 0x3d), /* 23 */
|
||||
SPD_VAL(0x45, 0x45), /* 24 */
|
||||
SPD_VAL(0x50, 0x50), /* 25 */
|
||||
SPD_VAL(0x45, 0x45), /* 26 */
|
||||
SPD_VAL(0x3c, 0x3c), /* 27 */
|
||||
SPD_VAL(0x28, 0x28), /* 28 */
|
||||
SPD_VAL(0x3c, 0x3c), /* 29 */
|
||||
SPD_VAL(0x2d, 0x2d), /* 30 */
|
||||
SPD_VAL(0x20, 0x80), /* 31 */
|
||||
SPD_VAL(0x20, 0x20), /* 32 */
|
||||
SPD_VAL(0x27, 0x27), /* 33 */
|
||||
SPD_VAL(0x10, 0x10), /* 34 */
|
||||
SPD_VAL(0x17, 0x17), /* 35 */
|
||||
SPD_VAL(0x3c, 0x3c), /* 36 */
|
||||
SPD_VAL(0x1e, 0x1e), /* 37 */
|
||||
SPD_VAL(0x1e, 0x1e), /* 38 */
|
||||
SPD_VAL(0x00, 0x00), /* 39 */
|
||||
SPD_VAL(0x00, 0x06), /* 40 */
|
||||
SPD_VAL(0x37, 0x37), /* 41 */
|
||||
SPD_VAL(0x4b, 0x7f), /* 42 */
|
||||
SPD_VAL(0x80, 0x80), /* 43 */
|
||||
SPD_VAL(0x18, 0x18), /* 44 */
|
||||
SPD_VAL(0x22, 0x22), /* 45 */
|
||||
SPD_VAL(0x00, 0x00), /* 46 */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
SPD_VAL(0x10, 0x10), /* 62 */
|
||||
SPD_VAL(0x7e, 0x1d), /* 63 */
|
||||
{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
|
||||
SPD_VAL(0x00, 0x00), /* 72 */
|
||||
#ifdef VME_CADDY2
|
||||
{ "vme-caddy/2 ram " }
|
||||
#else
|
||||
{ "vme-cpu/2 ram " }
|
||||
#endif
|
||||
};
|
||||
|
||||
int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
||||
{
|
||||
int old_bus = I2C_GET_BUS();
|
||||
unsigned int l, sum;
|
||||
int valid = 0;
|
||||
|
||||
I2C_SET_BUS(0);
|
||||
|
||||
if (i2c_read(chip, addr, alen, buffer, len) == 0)
|
||||
if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
|
||||
sum = 0;
|
||||
for (l = 0; l < 63; l++)
|
||||
sum = (sum + buffer[l]) & 0xff;
|
||||
if (sum == buffer[63])
|
||||
valid = 1;
|
||||
else
|
||||
printf("Invalid checksum in EEPROM %02x %02x\n",
|
||||
sum, buffer[63]);
|
||||
}
|
||||
|
||||
if (valid == 0) {
|
||||
memcpy(buffer, (void *)&default_spd_eeprom, len);
|
||||
sum = 0;
|
||||
for (l = 0; l < 63; l++)
|
||||
sum = (sum + buffer[l]) & 0xff;
|
||||
if (sum != buffer[63])
|
||||
printf("Invalid checksum in FLASH %02x %02x\n",
|
||||
sum, buffer[63]);
|
||||
buffer[63] = sum;
|
||||
}
|
||||
|
||||
I2C_SET_BUS(old_bus);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
36
board/esd/vme8349/vme8349pin.h
Normal file
36
board/esd/vme8349/vme8349pin.h
Normal file
@ -0,0 +1,36 @@
|
||||
/*
|
||||
* vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
|
||||
* Copyright (c) 2009 esd gmbh.
|
||||
*
|
||||
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __VME8349PIN_H__
|
||||
#define __VME8349PIN_H__
|
||||
|
||||
#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */
|
||||
#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */
|
||||
#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */
|
||||
#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */
|
||||
#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/
|
||||
|
||||
#endif /* of ifndef __VME8349PIN_H__ */
|
||||
@ -1 +1,9 @@
|
||||
ifndef NAND_SPL
|
||||
ifeq ($(CONFIG_MK_NAND), y)
|
||||
TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
|
||||
endif
|
||||
endif
|
||||
|
||||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xFE000000
|
||||
endif
|
||||
|
||||
@ -32,6 +32,8 @@
|
||||
#include <mpc83xx.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <ns16550.h>
|
||||
#include <nand.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@ -45,6 +47,8 @@ int board_early_init_f(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
|
||||
static u8 read_board_info(void)
|
||||
{
|
||||
u8 val8;
|
||||
@ -220,3 +224,41 @@ int board_eth_init(bd_t *bis)
|
||||
cpu_eth_init(bis); /* Initialize TSECs first */
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#else /* CONFIG_NAND_SPL */
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Freescale MPC8315ERDB\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
board_early_init_f();
|
||||
NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
|
||||
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
|
||||
puts("NAND boot... ");
|
||||
init_timebase();
|
||||
initdram(0);
|
||||
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
|
||||
CONFIG_SYS_NAND_U_BOOT_RELOC);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
nand_boot();
|
||||
}
|
||||
|
||||
void putc(char c)
|
||||
{
|
||||
if (gd->flags & GD_FLG_SILENT)
|
||||
return;
|
||||
|
||||
if (c == '\n')
|
||||
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
|
||||
|
||||
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
@ -54,6 +54,7 @@ static void resume_from_sleep(void)
|
||||
* This is useful for faster booting in configs where the RAM is unlikely
|
||||
* to be changed, or for things like NAND booting where space is tight.
|
||||
*/
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
static long fixed_sdram(void)
|
||||
{
|
||||
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
|
||||
@ -68,7 +69,7 @@ static long fixed_sdram(void)
|
||||
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
|
||||
* or the DDR2 controller may fail to initialize correctly.
|
||||
*/
|
||||
udelay(50000);
|
||||
__udelay(50000);
|
||||
|
||||
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
|
||||
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
|
||||
@ -100,6 +101,12 @@ static long fixed_sdram(void)
|
||||
|
||||
return msize;
|
||||
}
|
||||
#else
|
||||
static long fixed_sdram(void)
|
||||
{
|
||||
return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
|
||||
}
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
|
||||
@ -69,6 +69,12 @@ void cpu_init_f (volatile immap_t * im)
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
|
||||
(ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
|
||||
(ACR_APARK << ACR_APARK_SHIFT) |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
|
||||
(ACR_PARKM << ACR_PARKM_SHIFT) |
|
||||
#endif
|
||||
0;
|
||||
__be32 acr_val =
|
||||
@ -77,6 +83,12 @@ void cpu_init_f (volatile immap_t * im)
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
|
||||
(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
|
||||
(CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
|
||||
(CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
|
||||
#endif
|
||||
0;
|
||||
__be32 spcr_mask =
|
||||
|
||||
@ -29,6 +29,7 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <i2c.h>
|
||||
#include <spd.h>
|
||||
#include <asm/mmu.h>
|
||||
@ -150,6 +151,14 @@ long int spd_sdram()
|
||||
unsigned int ddrc_ecc_enable;
|
||||
unsigned int pvr = get_pvr();
|
||||
|
||||
/*
|
||||
* First disable the memory controller (could be enabled
|
||||
* by the debugger)
|
||||
*/
|
||||
clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
|
||||
sync();
|
||||
isync();
|
||||
|
||||
/* Read SPD parameters with I2C */
|
||||
CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
|
||||
#ifdef SPD_DEBUG
|
||||
|
||||
@ -15,6 +15,18 @@ Freescale MPC8315ERDB Board
|
||||
4321 4321
|
||||
(where the '*' indicates the position of the tab of the switch.)
|
||||
|
||||
To boot the image at the beginning of NAND flash, use these
|
||||
DIP switch settings for S3 S4:
|
||||
|
||||
+------+ +------+
|
||||
| * | | *** |
|
||||
| *** | | * |
|
||||
+------+ ON +------+ ON
|
||||
4321 4321
|
||||
(where the '*' indicates the position of the tab of the switch.)
|
||||
|
||||
When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
|
||||
|
||||
2. Memory Map
|
||||
The memory map looks like this:
|
||||
|
||||
@ -26,6 +38,9 @@ Freescale MPC8315ERDB Board
|
||||
0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
|
||||
0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
|
||||
|
||||
When booting from NAND, NAND flash is CS0 and NOR flash
|
||||
is CS1.
|
||||
|
||||
3. Definitions
|
||||
|
||||
3.1 Explanation of NEW definitions in:
|
||||
@ -43,13 +58,15 @@ Freescale MPC8315ERDB Board
|
||||
|
||||
export CROSS_COMPILE=your-cross-compiler-prefix-
|
||||
make distclean
|
||||
make MPC8315ERDB_config
|
||||
make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
|
||||
make all
|
||||
|
||||
5. Downloading and Flashing Images
|
||||
|
||||
5.1 Reflash U-boot Image using U-boot
|
||||
|
||||
NOR flash:
|
||||
|
||||
tftp 40000 u-boot.bin
|
||||
protect off all
|
||||
erase fe000000 fe1fffff
|
||||
@ -60,6 +77,15 @@ Freescale MPC8315ERDB Board
|
||||
You have to supply the correct byte count with 'xxxx'
|
||||
from the TFTP result log.
|
||||
|
||||
NAND flash:
|
||||
|
||||
=>tftpboot $loadaddr <filename>
|
||||
=>nand erase 0 0x80000
|
||||
=>nand write $loadaddr 0 0x80000
|
||||
|
||||
...where 0x80000 is the filesize rounded up to
|
||||
the next 0x20000 increment.
|
||||
|
||||
5.2 Downloading and Booting Linux Kernel
|
||||
|
||||
Ensure that all networking-related environment variables are set
|
||||
@ -76,5 +102,4 @@ Freescale MPC8315ERDB Board
|
||||
|
||||
6 Notes
|
||||
|
||||
Booting from NAND flash is not yet supported.
|
||||
The console baudrate for MPC8315ERDB is 115200bps.
|
||||
|
||||
@ -25,6 +25,11 @@
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#ifdef CONFIG_MK_NAND
|
||||
#define CONFIG_NAND_U_BOOT 1
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE 0x00100000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
@ -51,20 +56,29 @@
|
||||
HRCWL_SVCOD_DIV_2 |\
|
||||
HRCWL_CSB_TO_CLKIN_2X1 |\
|
||||
HRCWL_CORE_TO_CSB_3X1)
|
||||
#define CONFIG_SYS_HRCW_HIGH (\
|
||||
#define CONFIG_SYS_HRCW_HIGH_BASE (\
|
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY |\
|
||||
HRCWH_TSEC1M_IN_RGMII |\
|
||||
HRCWH_TSEC2M_IN_RGMII |\
|
||||
HRCWH_BIG_ENDIAN |\
|
||||
HRCWH_LALE_NORMAL)
|
||||
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
|
||||
HRCWH_FROM_0XFFF00100 |\
|
||||
HRCWH_ROM_LOC_NAND_SP_8BIT |\
|
||||
HRCWH_RL_EXT_NAND)
|
||||
#else
|
||||
#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_RL_EXT_LEGACY)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* System IO Config
|
||||
*/
|
||||
@ -79,6 +93,10 @@
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xE0000000
|
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Arbiter Setup
|
||||
*/
|
||||
@ -161,12 +179,6 @@
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
|
||||
|
||||
@ -200,10 +212,10 @@
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
|
||||
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
|
||||
| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
|
||||
| BR_V ) /* valid */
|
||||
#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
|
||||
| OR_UPM_XAM \
|
||||
| OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 \
|
||||
@ -223,18 +235,31 @@
|
||||
/*
|
||||
* NAND Flash on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
|
||||
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_NAND_BASE 0xFFF00000
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE 0xE0600000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
|
||||
#define CONFIG_CMD_NAND 1
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
|
||||
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V ) /* valid */
|
||||
#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
@ -243,9 +268,31 @@
|
||||
| OR_FCM_EHTR )
|
||||
/* 0xFFFF8396 */
|
||||
|
||||
#ifdef CONFIG_NAND_U_BOOT
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
|
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
|
||||
#else
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
|
||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
|
||||
|
||||
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
|
||||
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
|
||||
|
||||
#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
|
||||
!defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Serial Port
|
||||
*/
|
||||
@ -254,7 +301,7 @@
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
@ -408,7 +455,16 @@
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
#if defined(CONFIG_NAND_U_BOOT)
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_OFFSET (512 * 1024)
|
||||
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
CONFIG_ENV_RANGE)
|
||||
#elif !defined(CONFIG_SYS_RAMBOOT)
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
|
||||
@ -442,7 +498,7 @@
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
|
||||
#undef CONFIG_CMD_SAVEENV
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#endif
|
||||
@ -504,7 +560,8 @@
|
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
|
||||
@ -71,6 +71,14 @@
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xE0000000
|
||||
|
||||
/*
|
||||
* Bus Arbitration Configuration Register (ACR)
|
||||
*/
|
||||
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
|
||||
#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
|
||||
#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
|
||||
#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
|
||||
@ -34,6 +34,13 @@
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* Top level Makefile configuration choices
|
||||
*/
|
||||
#ifdef CONFIG_MK_caddy2
|
||||
#define VME_CADDY2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
@ -43,6 +50,8 @@
|
||||
#define CONFIG_MPC8349 1 /* MPC8349 specific */
|
||||
#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_PCI
|
||||
/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
|
||||
#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
|
||||
@ -75,7 +84,9 @@
|
||||
*/
|
||||
#define CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
|
||||
#undef CONFIG_SPD_EEPROM /* dont use SPD EEPROM for DDR setup*/
|
||||
#define CONFIG_SPD_EEPROM
|
||||
#define SPD_EEPROM_ADDRESS 0x54
|
||||
#define CONFIG_SYS_READ_SPD vme8349_read_spd
|
||||
#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
|
||||
|
||||
/*
|
||||
@ -96,54 +107,40 @@
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
|
||||
#define CONFIG_DDR_2T_TIMING
|
||||
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_SIZE 512 /* MB */
|
||||
|
||||
#if (CONFIG_SYS_DDR_SIZE == 512)
|
||||
#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
|
||||
CSCONFIG_COL_BIT_10 | \
|
||||
CSCONFIG_BANK_BIT_3)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00220802
|
||||
#define CONFIG_SYS_DDR_TIMING_1 0x39377322
|
||||
#define CONFIG_SYS_DDR_TIMING_2 0x2f9848ca /* P9-45, tuning? */
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuf,no DYN_PWR */
|
||||
#define CONFIG_SYS_DDR_MODE 0x07940242
|
||||
#define CONFIG_SYS_DDR_MODE2 0x00000000
|
||||
/* autocharge,no open page */
|
||||
#define CONFIG_SYS_DDR_INTERVAL 0x04060100
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG 0x63000000
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x04061000
|
||||
#define CONFIG_SYS_DDRCDR 0x80080001
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
|
||||
#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
|
||||
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
|
||||
|
||||
#ifdef VME_CADDY2
|
||||
#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
|
||||
#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
(2 << BR_PS_SHIFT) | /* 32bit */ \
|
||||
BR_V) /* valid */
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xF8006FF7 /* 128 MB flash size */
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001A /* 128 MB window size */
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */
|
||||
#else
|
||||
#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
|
||||
#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
|
||||
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
|
||||
(2 << BR_PS_SHIFT) | /* 32bit */ \
|
||||
BR_V) /* valid */
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */
|
||||
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */
|
||||
#endif
|
||||
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801)
|
||||
#define CONFIG_SYS_OR1_PRELIM (0xffff8000 | 0x00000200)
|
||||
#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200)
|
||||
#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x0000000e)
|
||||
#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011)
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
|
||||
@ -157,7 +154,7 @@
|
||||
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
@ -174,11 +171,10 @@
|
||||
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs
|
||||
* LCRR: DLL bypass, Clock divider is 4
|
||||
* LCRR: no DLL bypass, Clock divider is 4
|
||||
* External Local Bus rate is
|
||||
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
|
||||
@ -268,10 +264,10 @@
|
||||
#undef PCI_ONE_PCI1
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
#ifndef VME_CADDY2
|
||||
#define CONFIG_NET_MULTI
|
||||
#endif
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
@ -282,19 +278,26 @@
|
||||
#define PCI_IDSEL_NUMBER 0xFIXME
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/*
|
||||
* TSEC configuration
|
||||
*/
|
||||
#ifdef VME_CADDY2
|
||||
#define CONFIG_E1000
|
||||
#else
|
||||
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI
|
||||
#endif
|
||||
|
||||
#define CONFIG_GMII /* MII PHY management */
|
||||
#define CONFIG_GMII /* MII PHY management */
|
||||
#define CONFIG_TSEC1
|
||||
#define CONFIG_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_TSEC2
|
||||
@ -312,6 +315,12 @@
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
#if defined(CONFIG_E1000)
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
@ -560,7 +569,7 @@
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
||||
#undef CONFIG_BOOTARGS /* boot command will set bootargs */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
@ -605,4 +614,9 @@
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
|
||||
unsigned char *buffer, int len);
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user