Improve configuration of FPGA subsystem
This patch removes the FPGA subsystem configuration through the CONFIG_FPGA bitmask configuration option. See README for the new options: CONFIG_FPGA, CONFIG_FPGA_<vendor>, CONFIG_FPGA_<family> Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This commit is contained in:
parent
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21
README
21
README
@ -1377,15 +1377,24 @@ The following options need to be configured:
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SPI configuration items (port pins to use, etc). For
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an example, see include/configs/sacsng.h.
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- FPGA Support: CONFIG_FPGA_COUNT
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- FPGA Support: CONFIG_FPGA
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Enables FPGA subsystem.
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CONFIG_FPGA_<vendor>
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Enables support for specific chip vendors.
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(ALTERA, XILINX)
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CONFIG_FPGA_<family>
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Enables support for FPGA family.
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(SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
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CONFIG_FPGA_COUNT
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Specify the number of FPGA devices to support.
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CONFIG_FPGA
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Used to specify the types of FPGA devices. For example,
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#define CONFIG_FPGA CFG_XILINX_VIRTEX2
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CFG_FPGA_PROG_FEEDBACK
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Enable printing of hash marks during FPGA configuration.
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@ -34,7 +34,7 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if (CONFIG_FPGA)
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#if defined(CONFIG_FPGA)
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#if 0
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#define GEN860T_FPGA_DEBUG
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@ -254,7 +254,7 @@ int misc_init_r (void)
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mii_init ();
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#endif
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#if (CONFIG_FPGA)
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#if defined(CONFIG_FPGA)
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gen860t_init_fpga ();
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#endif
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return 0;
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@ -28,7 +28,7 @@
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#include <common.h> /* core U-Boot definitions */
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#include <ACEX1K.h> /* ACEX device family */
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#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K)
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/* Define FPGA_DEBUG to get debug printf's */
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#ifdef FPGA_DEBUG
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@ -363,4 +363,4 @@ static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
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}
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#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */
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#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */
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@ -40,7 +40,7 @@
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#define PRINTF(fmt,args...)
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#endif
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#if (CONFIG_FPGA & CFG_FPGA_ALTERA)
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA)
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/* Local Static Functions */
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static int altera_validate (Altera_desc * desc, char *fn);
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@ -56,11 +56,11 @@ int altera_load( Altera_desc *desc, void *buf, size_t bsize )
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switch (desc->family) {
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case Altera_ACEX1K:
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case Altera_CYC2:
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#if (CONFIG_FPGA & CFG_ACEX1K)
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#if defined(CONFIG_FPGA_ACEX1K)
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PRINTF ("%s: Launching the ACEX1K Loader...\n",
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__FUNCTION__);
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ret_val = ACEX1K_load (desc, buf, bsize);
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#elif (CONFIG_FPGA & CFG_CYCLON2)
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#elif defined CONFIG_FPGA_CYCLON2
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PRINTF ("%s: Launching the CYCLON II Loader...\n",
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__FUNCTION__);
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ret_val = CYC2_load (desc, buf, bsize);
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@ -88,7 +88,7 @@ int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
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} else {
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switch (desc->family) {
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case Altera_ACEX1K:
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#if (CONFIG_FPGA & CFG_ACEX)
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#if defined(CONFIG_FPGA_ACEX)
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PRINTF ("%s: Launching the ACEX1K Reader...\n",
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__FUNCTION__);
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ret_val = ACEX1K_dump (desc, buf, bsize);
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@ -156,9 +156,9 @@ int altera_info( Altera_desc *desc )
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switch (desc->family) {
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case Altera_ACEX1K:
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case Altera_CYC2:
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#if (CONFIG_FPGA & CFG_ACEX1K)
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#if defined(CONFIG_FPGA_ACEX1K)
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ACEX1K_info (desc);
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#elif (CONFIG_FPGA & CFG_CYCLON2)
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#elif defined(CONFIG_FPGA_CYCLON2)
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CYC2_info (desc);
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#else
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/* just in case */
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@ -192,7 +192,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset)
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} else {
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switch (desc->family) {
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case Altera_ACEX1K:
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#if (CONFIG_FPGA & CFG_ACEX1K)
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#if defined(CONFIG_FPGA_ACEX1K)
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ret_val = ACEX1K_reloc (desc, reloc_offset);
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#else
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printf ("%s: No support for ACEX devices.\n",
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@ -200,7 +200,7 @@ int altera_reloc( Altera_desc *desc, ulong reloc_offset)
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#endif
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break;
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case Altera_CYC2:
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#if (CONFIG_FPGA & CFG_CYCLON2)
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#if defined(CONFIG_FPGA_CYCLON2)
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ret_val = CYC2_reloc (desc, reloc_offset);
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#else
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printf ("%s: No support for CYCLON II devices.\n",
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@ -249,4 +249,4 @@ static int altera_validate (Altera_desc * desc, char *fn)
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/* ------------------------------------------------------------------------- */
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#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */
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#endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */
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@ -58,7 +58,7 @@ static int fpga_get_op (char *opstr);
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/* Convert bitstream data and load into the fpga */
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int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
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{
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#if (CONFIG_FPGA & CFG_FPGA_XILINX)
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#if defined(CONFIG_FPGA_XILINX)
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unsigned int length;
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unsigned char* swapdata;
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unsigned int swapsize;
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@ -27,7 +27,7 @@
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#include <altera.h>
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#include <ACEX1K.h> /* ACEX device family */
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#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2))
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_CYCLON2)
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/* Define FPGA_DEBUG to get debug printf's */
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#ifdef FPGA_DEBUG
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@ -302,4 +302,4 @@ static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset)
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return ret_val;
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}
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#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */
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#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_CYCLON2 */
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@ -67,14 +67,11 @@ static int fpga_dev_info( int devnum );
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static void fpga_no_sup( char *fn, char *msg )
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{
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if ( fn && msg ) {
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printf( "%s: No support for %s. CONFIG_FPGA defined as 0x%x.\n",
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fn, msg, CONFIG_FPGA );
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printf( "%s: No support for %s.\n", fn, msg);
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} else if ( msg ) {
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printf( "No support for %s. CONFIG_FPGA defined as 0x%x.\n",
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msg, CONFIG_FPGA );
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printf( "No support for %s.\n", msg);
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} else {
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printf( "No FPGA suport! CONFIG_FPGA defined as 0x%x.\n",
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CONFIG_FPGA );
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printf( "No FPGA suport!\n");
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}
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}
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@ -112,11 +109,6 @@ static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_va
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printf( "%s: Null buffer.\n", fn );
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return (fpga_desc * const)NULL;
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}
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if ( !bsize ) {
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printf( "%s: Null buffer size.\n", fn );
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return (fpga_desc * const)NULL;
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}
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return desc;
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}
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@ -135,7 +127,7 @@ static int fpga_dev_info( int devnum )
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switch ( desc->devtype ) {
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case fpga_xilinx:
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#if CONFIG_FPGA & CFG_FPGA_XILINX
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#if defined(CONFIG_FPGA_XILINX)
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printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc );
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ret_val = xilinx_info( desc->devdesc );
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#else
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@ -143,7 +135,7 @@ static int fpga_dev_info( int devnum )
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#endif
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break;
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case fpga_altera:
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#if CONFIG_FPGA & CFG_FPGA_ALTERA
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#if defined(CONFIG_FPGA_ALTERA)
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printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
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ret_val = altera_info( desc->devdesc );
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#else
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@ -175,14 +167,14 @@ int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off )
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switch ( devtype ) {
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case fpga_xilinx:
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#if CONFIG_FPGA & CFG_FPGA_XILINX
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#if defined(CONFIG_FPGA_XILINX)
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ret_val = xilinx_reloc( desc, reloc_off );
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#else
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fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
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#endif
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break;
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case fpga_altera:
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#if CONFIG_FPGA & CFG_FPGA_ALTERA
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#if defined(CONFIG_FPGA_ALTERA)
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ret_val = altera_reloc( desc, reloc_off );
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#else
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fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
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@ -268,14 +260,14 @@ int fpga_load( int devnum, void *buf, size_t bsize )
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if ( desc ) {
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switch ( desc->devtype ) {
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case fpga_xilinx:
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#if CONFIG_FPGA & CFG_FPGA_XILINX
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#if defined(CONFIG_FPGA_XILINX)
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ret_val = xilinx_load( desc->devdesc, buf, bsize );
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#else
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fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
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#endif
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break;
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case fpga_altera:
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#if CONFIG_FPGA & CFG_FPGA_ALTERA
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#if defined(CONFIG_FPGA_ALTERA)
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ret_val = altera_load( desc->devdesc, buf, bsize );
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#else
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fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
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@ -301,14 +293,14 @@ int fpga_dump( int devnum, void *buf, size_t bsize )
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if ( desc ) {
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switch ( desc->devtype ) {
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case fpga_xilinx:
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#if CONFIG_FPGA & CFG_FPGA_XILINX
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#if defined(CONFIG_FPGA_XILINX)
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ret_val = xilinx_dump( desc->devdesc, buf, bsize );
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#else
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fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
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#endif
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break;
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case fpga_altera:
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#if CONFIG_FPGA & CFG_FPGA_ALTERA
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#if defined(CONFIG_FPGA_ALTERA)
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ret_val = altera_dump( desc->devdesc, buf, bsize );
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#else
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fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
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@ -25,7 +25,7 @@
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#include <common.h> /* core U-Boot definitions */
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#include <spartan2.h> /* Spartan-II device family */
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#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2))
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN2)
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/* Define FPGA_DEBUG to get debug printf's */
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#ifdef FPGA_DEBUG
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@ -30,7 +30,7 @@
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#include <common.h> /* core U-Boot definitions */
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#include <spartan3.h> /* Spartan-II device family */
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#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3))
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3)
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/* Define FPGA_DEBUG to get debug printf's */
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#ifdef FPGA_DEBUG
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@ -31,7 +31,7 @@
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#include <common.h>
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#include <virtex2.h>
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#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2))
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_VIRTEX2)
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#if 0
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#define FPGA_DEBUG
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@ -32,7 +32,7 @@
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#include <spartan2.h>
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#include <spartan3.h>
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#if (CONFIG_FPGA & CFG_FPGA_XILINX)
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#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
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#if 0
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#define FPGA_DEBUG
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@ -59,7 +59,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
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} else
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switch (desc->family) {
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case Xilinx_Spartan2:
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#if (CONFIG_FPGA & CFG_SPARTAN2)
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#if defined(CONFIG_FPGA_SPARTAN2)
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PRINTF ("%s: Launching the Spartan-II Loader...\n",
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__FUNCTION__);
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ret_val = Spartan2_load (desc, buf, bsize);
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@ -69,7 +69,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
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#endif
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break;
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case Xilinx_Spartan3:
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#if (CONFIG_FPGA & CFG_SPARTAN3)
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#if defined(CONFIG_FPGA_SPARTAN3)
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PRINTF ("%s: Launching the Spartan-III Loader...\n",
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__FUNCTION__);
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ret_val = Spartan3_load (desc, buf, bsize);
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@ -79,7 +79,7 @@ int xilinx_load (Xilinx_desc * desc, void *buf, size_t bsize)
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#endif
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break;
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case Xilinx_Virtex2:
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#if (CONFIG_FPGA & CFG_VIRTEX2)
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#if defined(CONFIG_FPGA_VIRTEX2)
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PRINTF ("%s: Launching the Virtex-II Loader...\n",
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__FUNCTION__);
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ret_val = Virtex2_load (desc, buf, bsize);
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@ -106,7 +106,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
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} else
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switch (desc->family) {
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case Xilinx_Spartan2:
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#if (CONFIG_FPGA & CFG_SPARTAN2)
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#if defined(CONFIG_FPGA_SPARTAN2)
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PRINTF ("%s: Launching the Spartan-II Reader...\n",
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__FUNCTION__);
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ret_val = Spartan2_dump (desc, buf, bsize);
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@ -116,7 +116,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
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#endif
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break;
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case Xilinx_Spartan3:
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#if (CONFIG_FPGA & CFG_SPARTAN3)
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#if defined(CONFIG_FPGA_SPARTAN3)
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PRINTF ("%s: Launching the Spartan-III Reader...\n",
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__FUNCTION__);
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ret_val = Spartan3_dump (desc, buf, bsize);
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@ -126,7 +126,7 @@ int xilinx_dump (Xilinx_desc * desc, void *buf, size_t bsize)
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#endif
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break;
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case Xilinx_Virtex2:
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#if (CONFIG_FPGA & CFG_VIRTEX2)
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#if defined( CONFIG_FPGA_VIRTEX2)
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PRINTF ("%s: Launching the Virtex-II Reader...\n",
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__FUNCTION__);
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ret_val = Virtex2_dump (desc, buf, bsize);
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@ -198,7 +198,7 @@ int xilinx_info (Xilinx_desc * desc)
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printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
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switch (desc->family) {
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case Xilinx_Spartan2:
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#if (CONFIG_FPGA & CFG_SPARTAN2)
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#if defined(CONFIG_FPGA_SPARTAN2)
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Spartan2_info (desc);
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#else
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/* just in case */
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@ -207,7 +207,7 @@ int xilinx_info (Xilinx_desc * desc)
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#endif
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break;
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case Xilinx_Spartan3:
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#if (CONFIG_FPGA & CFG_SPARTAN3)
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#if defined(CONFIG_FPGA_SPARTAN3)
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Spartan3_info (desc);
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#else
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/* just in case */
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@ -216,7 +216,7 @@ int xilinx_info (Xilinx_desc * desc)
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#endif
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break;
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case Xilinx_Virtex2:
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#if (CONFIG_FPGA & CFG_VIRTEX2)
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#if defined(CONFIG_FPGA_VIRTEX2)
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Virtex2_info (desc);
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#else
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/* just in case */
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@ -249,7 +249,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
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} else
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switch (desc->family) {
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case Xilinx_Spartan2:
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#if (CONFIG_FPGA & CFG_SPARTAN2)
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#if defined(CONFIG_FPGA_SPARTAN2)
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ret_val = Spartan2_reloc (desc, reloc_offset);
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#else
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printf ("%s: No support for Spartan-II devices.\n",
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@ -257,7 +257,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
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#endif
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break;
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case Xilinx_Spartan3:
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#if (CONFIG_FPGA & CFG_SPARTAN3)
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#if defined(CONFIG_FPGA_SPARTAN3)
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ret_val = Spartan3_reloc (desc, reloc_offset);
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#else
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printf ("%s: No support for Spartan-III devices.\n",
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@ -265,7 +265,7 @@ int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset)
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#endif
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break;
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case Xilinx_Virtex2:
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#if (CONFIG_FPGA & CFG_VIRTEX2)
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#if defined(CONFIG_FPGA_VIRTEX2)
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ret_val = Virtex2_reloc (desc, reloc_offset);
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#else
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printf ("%s: No support for Virtex-II devices.\n",
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@ -308,4 +308,4 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn)
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return ret_val;
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}
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||||
|
||||
#endif /* CONFIG_FPGA & CFG_FPGA_XILINX */
|
||||
#endif /* CONFIG_FPGA && CONFIG_FPGA_XILINX */
|
||||
|
@ -273,7 +273,9 @@
|
||||
* Virtex2 FPGA configuration support
|
||||
*/
|
||||
#define CONFIG_FPGA_COUNT 1
|
||||
#define CONFIG_FPGA CFG_XILINX_VIRTEX2
|
||||
#define CONFIG_FPGA
|
||||
#define CONFIG_FPGA_XILINX
|
||||
#define CONFIG_FPGA_VIRTEX2
|
||||
#define CFG_FPGA_PROG_FEEDBACK
|
||||
|
||||
|
||||
|
@ -192,7 +192,9 @@
|
||||
|
||||
/* FPGA - Spartan 2 */
|
||||
/* experiment
|
||||
#define CONFIG_FPGA CFG_SPARTAN3
|
||||
#define CONFIG_FPGA
|
||||
#define CONFIG_FPGA_XILINX
|
||||
#define CONFIG_FPGA_SPARTAN3
|
||||
#define CONFIG_FPGA_COUNT 1
|
||||
#define CFG_FPGA_PROG_FEEDBACK
|
||||
#define CFG_FPGA_CHECK_CTRLC
|
||||
|
@ -296,7 +296,9 @@
|
||||
/*-----------------------------------------------------------------------
|
||||
* FPGA stuff
|
||||
*-----------------------------------------------------------------------*/
|
||||
#define CONFIG_FPGA CFG_ALTERA_CYCLON2
|
||||
#define CONFIG_FPGA
|
||||
#define CONFIG_FPGA_ALTERA
|
||||
#define CONFIG_FPGA_CYCLON2
|
||||
#define CFG_FPGA_CHECK_CTRLC
|
||||
#define CFG_FPGA_PROG_FEEDBACK
|
||||
#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
|
||||
|
@ -31,11 +31,11 @@
|
||||
*********************************************************************/
|
||||
#define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 )
|
||||
#define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 )
|
||||
#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 )
|
||||
#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 )
|
||||
#define CFG_SPARTAN3 CFG_FPGA_DEV( 0x8 )
|
||||
#define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2)
|
||||
#define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E)
|
||||
#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2)
|
||||
#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2)
|
||||
#define CFG_XILINX_SPARTAN3 (CFG_FPGA_XILINX | CFG_SPARTAN3)
|
||||
/* XXX - Add new models here */
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user