i2c, fsl_i2c: switch to new multibus/multiadapter support
- added to fsl_i2c driver new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org>
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17
README
17
README
@ -1968,6 +1968,18 @@ CBFS (Coreboot Filesystem) support
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CONFIG_SYS_I2C_SOFT_SPEED_4 and CONFIG_SYS_I2C_SOFT_SLAVE_4
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for defining speed and slave address
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- drivers/i2c/fsl_i2c.c:
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- activate i2c driver with CONFIG_SYS_I2C_FSL
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define CONFIG_SYS_FSL_I2C_OFFSET for setting the register
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offset CONFIG_SYS_FSL_I2C_SPEED for the i2c speed and
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CONFIG_SYS_FSL_I2C_SLAVE for the slave addr of the first
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bus.
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- If your board supports a second fsl i2c bus, define
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CONFIG_SYS_FSL_I2C2_OFFSET for the register offset
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CONFIG_SYS_FSL_I2C2_SPEED for the speed and
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CONFIG_SYS_FSL_I2C2_SLAVE for the slave address of the
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second bus.
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additional defines:
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CONFIG_SYS_NUM_I2C_BUSES
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@ -2213,11 +2225,6 @@ CBFS (Coreboot Filesystem) support
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If not defined, then U-Boot uses predefined value for
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specified DTT device.
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CONFIG_FSL_I2C
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Define this option if you want to use Freescale's I2C driver in
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drivers/i2c/fsl_i2c.c.
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CONFIG_I2C_MUX
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Define this option if you have I2C devices reached over 1 .. n
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@ -105,7 +105,7 @@ void cpu_init_f(void)
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out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
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#endif
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
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#endif
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@ -134,7 +134,7 @@ int get_clocks(void)
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gd->bus_clk = gd->arch.flb_clk;
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}
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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gd->arch.i2c1_clk = gd->bus_clk;
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#endif
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@ -115,7 +115,7 @@ void cpu_init_f(void)
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out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
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#endif
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
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CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
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#endif
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@ -47,7 +47,7 @@ int get_clocks(void)
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gd->bus_clk = CONFIG_SYS_CLK;
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gd->cpu_clk = (gd->bus_clk * 2);
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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gd->arch.i2c1_clk = gd->bus_clk;
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#endif
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@ -228,7 +228,7 @@ void cpu_init_f(void)
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/* FlexBus Chipselect */
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init_fbcs();
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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CONFIG_SYS_I2C_PINMUX_REG =
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CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
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CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
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@ -498,7 +498,7 @@ void cpu_init_f(void)
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init_fbcs();
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#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
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CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
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#endif
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@ -90,9 +90,9 @@ int get_clocks (void)
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gd->bus_clk = gd->cpu_clk;
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#endif
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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gd->arch.i2c1_clk = gd->bus_clk;
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#ifdef CONFIG_SYS_I2C2_OFFSET
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#ifdef CONFIG_SYS_I2C2_FSL_OFFSET
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gd->arch.i2c2_clk = gd->bus_clk;
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#endif
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#endif
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@ -98,7 +98,7 @@ void cpu_init_f(void)
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out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
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#endif
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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out_8(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL);
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#endif
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@ -292,7 +292,7 @@ void cpu_init_f(void)
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out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
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#endif
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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out_8(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
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#endif
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@ -270,7 +270,7 @@ int get_clocks(void)
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gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000;
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gd->cpu_clk = (gd->bus_clk * 3);
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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gd->arch.i2c1_clk = gd->bus_clk;
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#endif
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@ -212,7 +212,7 @@ void cpu_init_f(void)
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GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
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GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_FSL_I2C
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out_be16(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
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#endif
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@ -273,7 +273,7 @@ void setup_5445x_clocks(void)
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#endif
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}
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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gd->arch.i2c1_clk = gd->bus_clk;
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#endif
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}
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@ -289,7 +289,7 @@ int get_clocks(void)
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setup_5445x_clocks();
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#endif
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_FSL_I2C
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gd->arch.i2c1_clk = gd->bus_clk;
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#endif
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@ -95,7 +95,7 @@ void cpu_init_f(void)
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out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
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#endif
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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out_be16(&gpio->par_feci2cirq,
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GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
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#endif
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@ -40,7 +40,7 @@ int get_clocks(void)
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gd->bus_clk = CONFIG_SYS_CLK;
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gd->cpu_clk = (gd->bus_clk * 2);
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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gd->arch.i2c1_clk = gd->bus_clk;
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#endif
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@ -26,7 +26,7 @@
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/* Architecture-specific global data */
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struct arch_global_data {
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#ifdef CONFIG_FSL_I2C
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#ifdef CONFIG_SYS_I2C_FSL
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unsigned long i2c1_clk;
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unsigned long i2c2_clk;
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#endif
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@ -186,11 +186,11 @@ static spd_eeprom_t default_spd_eeprom = {
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int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int old_bus = I2C_GET_BUS();
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int old_bus = i2c_get_bus_num();
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unsigned int l, sum;
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int valid = 0;
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I2C_SET_BUS(0);
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i2c_set_bus_num(0);
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if (i2c_read(chip, addr, alen, buffer, len) == 0)
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if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
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@ -215,7 +215,7 @@ int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
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buffer[63] = sum;
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}
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I2C_SET_BUS(old_bus);
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i2c_set_bus_num(old_bus);
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return 0;
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}
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@ -82,7 +82,7 @@ CONFIG_CMD_DATE -- enable to use date feature in u-boot
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CONFIG_MCFTMR -- define to use DMA timer
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CONFIG_MCFPIT -- define to use PIT timer
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CONFIG_FSL_I2C -- define to use FSL common I2C driver
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CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
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CONFIG_HARD_I2C -- define for I2C hardware support
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CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
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CONFIG_SYS_I2C_SPEED -- define for I2C speed
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@ -90,7 +90,7 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop
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CONFIG_MCFTMR -- define to use DMA timer
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CONFIG_MCFPIT -- define to use PIT timer
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CONFIG_FSL_I2C -- define to use FSL common I2C driver
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CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
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CONFIG_HARD_I2C -- define for I2C hardware support
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CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
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CONFIG_SYS_I2C_SPEED -- define for I2C speed
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@ -89,7 +89,7 @@ MCFFEC_TOUT_LOOP -- set FEC timeout loop
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CONFIG_MCFTMR -- define to use DMA timer
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CONFIG_MCFPIT -- define to use PIT timer
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CONFIG_FSL_I2C -- define to use FSL common I2C driver
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CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
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CONFIG_HARD_I2C -- define for I2C hardware support
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CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
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CONFIG_SYS_I2C_SPEED -- define for I2C speed
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@ -112,7 +112,7 @@ _IO_BASE -- define for IO base address
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CONFIG_MCFTMR -- define to use DMA timer
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CONFIG_MCFPIT -- define to use PIT timer
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CONFIG_FSL_I2C -- define to use FSL common I2C driver
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CONFIG_SYS_FSL_I2C -- define to use FSL common I2C driver
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CONFIG_HARD_I2C -- define for I2C hardware support
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CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
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CONFIG_SYS_I2C_SPEED -- define for I2C speed
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@ -97,7 +97,7 @@ CONFIG_DOS_PARTITION -- enable DOS read/write
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CONFIG_SLTTMR -- define to use SLT timer
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CONFIG_FSL_I2C -- define to use FSL common I2C driver
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CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
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CONFIG_HARD_I2C -- define for I2C hardware support
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CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
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CONFIG_SYS_I2C_SPEED -- define for I2C speed
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@ -263,8 +263,7 @@ int misc_init_r(void)
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{
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int rc = 0;
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#ifdef CONFIG_HARD_I2C
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#if defined(CONFIG_SYS_I2C)
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unsigned int orig_bus = i2c_get_bus_num();
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u8 i2c_data;
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@ -87,7 +87,7 @@ void pci_init_board(void)
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#endif
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u8 reg8;
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#ifdef CONFIG_HARD_I2C
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#if defined(CONFIG_SYS_I2C)
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i2c_set_bus_num(1);
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/* Read the PCI_M66EN jumper setting */
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if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
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@ -248,7 +248,7 @@ int checkboard(void)
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in_8(&cpld_data->pcba_rev) & 0x0F);
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/* Initialize i2c early for rom_loc and flash bank information */
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
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if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
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i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
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@ -314,29 +314,13 @@ int ivm_analyze_eeprom(unsigned char *buf, int len)
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int ivm_read_eeprom(void)
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{
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#if defined(CONFIG_I2C_MUX)
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I2C_MUX_DEVICE *dev = NULL;
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#endif
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uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
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char *buf;
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unsigned long dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
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int ret;
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#if defined(CONFIG_SYS_I2C)
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buf = getenv("EEprom_ivm");
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i2c_set_bus_num(buf ? (int)simple_strtol(buf, NULL, 10) : 0);
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#else
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#if defined(CONFIG_I2C_MUX)
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/* First init the Bus, select the Bus */
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buf = (unsigned char *) getenv("EEprom_ivm");
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if (buf != NULL)
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dev = i2c_mux_ident_muxstring(buf);
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if (dev == NULL) {
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printf("Error couldnt add Bus for IVM\n");
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return -1;
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}
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i2c_set_bus_num(dev->busid);
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#endif
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/* add deblocking here */
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i2c_make_abort();
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@ -95,19 +95,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
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{0, 0, 0, 0, QE_IOP_TAB_END},
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};
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static int board_init_i2c_busses(void)
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{
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I2C_MUX_DEVICE *dev = NULL;
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uchar *dtt_bus = (uchar *)"pca9547:70:a";
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/* Set up the Bus for the DTTs */
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dev = i2c_mux_ident_muxstring(dtt_bus);
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if (dev == NULL)
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printf("Error couldn't add Bus for DTT\n");
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return 0;
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}
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#if defined(CONFIG_SUVD3)
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const uint upma_table[] = {
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0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
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@ -206,8 +193,6 @@ int board_early_init_r(void)
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int misc_init_r(void)
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{
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/* add board specific i2c busses */
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board_init_i2c_busses();
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return 0;
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}
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@ -28,7 +28,6 @@ LIB := $(obj)libi2c.o
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COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
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COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
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COBJS-$(CONFIG_DW_I2C) += designware_i2c.o
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COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o
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COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
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COBJS-$(CONFIG_I2C_MV) += mv_i2c.o
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COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o
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@ -46,6 +45,7 @@ COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
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COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
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COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
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COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
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COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
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COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
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@ -1,6 +1,9 @@
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/*
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* Copyright 2006,2009 Freescale Semiconductor, Inc.
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*
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* 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
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* Changes for multibus/multiadapter I2C support.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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@ -17,12 +20,8 @@
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*/
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#include <common.h>
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#ifdef CONFIG_HARD_I2C
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#include <command.h>
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#include <i2c.h> /* Functional interface */
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#include <asm/io.h>
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#include <asm/fsl_i2c.h> /* HW definitions */
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@ -47,25 +46,10 @@
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DECLARE_GLOBAL_DATA_PTR;
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/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
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* Default is bus 0. This is necessary because the DDR initialization
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* runs from ROM, and we can't switch buses because we can't modify
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* the global variables.
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*/
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#ifndef CONFIG_SYS_SPD_BUS_NUM
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#endif
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static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
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#if defined(CONFIG_I2C_MUX)
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static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
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#endif
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static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED};
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static const struct fsl_i2c *i2c_dev[2] = {
|
||||
(struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET),
|
||||
#ifdef CONFIG_SYS_I2C2_OFFSET
|
||||
(struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET)
|
||||
(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
|
||||
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
|
||||
(struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET)
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -222,12 +206,9 @@ static unsigned int get_i2c_clock(int bus)
|
||||
return gd->arch.i2c1_clk; /* I2C1 clock */
|
||||
}
|
||||
|
||||
void
|
||||
i2c_init(int speed, int slaveadd)
|
||||
static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
|
||||
{
|
||||
const struct fsl_i2c *dev;
|
||||
unsigned int temp;
|
||||
int bus_num, i;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_INIT_BOARD
|
||||
/* Call board specific i2c bus reset routine before accessing the
|
||||
@ -236,23 +217,14 @@ i2c_init(int speed, int slaveadd)
|
||||
*/
|
||||
i2c_init_board();
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C2_OFFSET
|
||||
bus_num = 2;
|
||||
#else
|
||||
bus_num = 1;
|
||||
#endif
|
||||
for (i = 0; i < bus_num; i++) {
|
||||
dev = i2c_dev[i];
|
||||
dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
|
||||
|
||||
writeb(0, &dev->cr); /* stop I2C controller */
|
||||
udelay(5); /* let it shutdown in peace */
|
||||
temp = set_i2c_bus_speed(dev, get_i2c_clock(i), speed);
|
||||
if (gd->flags & GD_FLG_RELOC)
|
||||
i2c_bus_speed[i] = temp;
|
||||
writeb(slaveadd << 1, &dev->adr);/* write slave address */
|
||||
writeb(0x0, &dev->sr); /* clear status register */
|
||||
writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
|
||||
}
|
||||
writeb(0, &dev->cr); /* stop I2C controller */
|
||||
udelay(5); /* let it shutdown in peace */
|
||||
set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
|
||||
writeb(slaveadd << 1, &dev->adr);/* write slave address */
|
||||
writeb(0x0, &dev->sr); /* clear status register */
|
||||
writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
|
||||
|
||||
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
|
||||
/* Call board specific i2c bus reset routine AFTER the bus has been
|
||||
@ -265,12 +237,13 @@ i2c_init(int speed, int slaveadd)
|
||||
}
|
||||
|
||||
static int
|
||||
i2c_wait4bus(void)
|
||||
i2c_wait4bus(struct i2c_adapter *adap)
|
||||
{
|
||||
struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
|
||||
unsigned long long timeval = get_ticks();
|
||||
const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
|
||||
|
||||
while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
|
||||
while (readb(&dev->sr) & I2C_SR_MBB) {
|
||||
if ((get_ticks() - timeval) > timeout)
|
||||
return -1;
|
||||
}
|
||||
@ -279,20 +252,21 @@ i2c_wait4bus(void)
|
||||
}
|
||||
|
||||
static __inline__ int
|
||||
i2c_wait(int write)
|
||||
i2c_wait(struct i2c_adapter *adap, int write)
|
||||
{
|
||||
u32 csr;
|
||||
unsigned long long timeval = get_ticks();
|
||||
const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
|
||||
struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
|
||||
|
||||
do {
|
||||
csr = readb(&i2c_dev[i2c_bus_num]->sr);
|
||||
csr = readb(&dev->sr);
|
||||
if (!(csr & I2C_SR_MIF))
|
||||
continue;
|
||||
/* Read again to allow register to stabilise */
|
||||
csr = readb(&i2c_dev[i2c_bus_num]->sr);
|
||||
csr = readb(&dev->sr);
|
||||
|
||||
writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
|
||||
writeb(0x0, &dev->sr);
|
||||
|
||||
if (csr & I2C_SR_MAL) {
|
||||
debug("i2c_wait: MAL\n");
|
||||
@ -317,29 +291,32 @@ i2c_wait(int write)
|
||||
}
|
||||
|
||||
static __inline__ int
|
||||
i2c_write_addr (u8 dev, u8 dir, int rsta)
|
||||
i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
|
||||
{
|
||||
struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
|
||||
|
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
|
||||
| (rsta ? I2C_CR_RSTA : 0),
|
||||
&i2c_dev[i2c_bus_num]->cr);
|
||||
&device->cr);
|
||||
|
||||
writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
|
||||
writeb((dev << 1) | dir, &device->dr);
|
||||
|
||||
if (i2c_wait(I2C_WRITE_BIT) < 0)
|
||||
if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static __inline__ int
|
||||
__i2c_write(u8 *data, int length)
|
||||
__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
|
||||
{
|
||||
struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
|
||||
int i;
|
||||
|
||||
for (i = 0; i < length; i++) {
|
||||
writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
|
||||
writeb(data[i], &dev->dr);
|
||||
|
||||
if (i2c_wait(I2C_WRITE_BIT) < 0)
|
||||
if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
|
||||
break;
|
||||
}
|
||||
|
||||
@ -347,57 +324,60 @@ __i2c_write(u8 *data, int length)
|
||||
}
|
||||
|
||||
static __inline__ int
|
||||
__i2c_read(u8 *data, int length)
|
||||
__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
|
||||
{
|
||||
struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
|
||||
int i;
|
||||
|
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
|
||||
&i2c_dev[i2c_bus_num]->cr);
|
||||
&dev->cr);
|
||||
|
||||
/* dummy read */
|
||||
readb(&i2c_dev[i2c_bus_num]->dr);
|
||||
readb(&dev->dr);
|
||||
|
||||
for (i = 0; i < length; i++) {
|
||||
if (i2c_wait(I2C_READ_BIT) < 0)
|
||||
if (i2c_wait(adap, I2C_READ_BIT) < 0)
|
||||
break;
|
||||
|
||||
/* Generate ack on last next to last byte */
|
||||
if (i == length - 2)
|
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
|
||||
&i2c_dev[i2c_bus_num]->cr);
|
||||
&dev->cr);
|
||||
|
||||
/* Do not generate stop on last byte */
|
||||
if (i == length - 1)
|
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
|
||||
&i2c_dev[i2c_bus_num]->cr);
|
||||
&dev->cr);
|
||||
|
||||
data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
|
||||
data[i] = readb(&dev->dr);
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
int
|
||||
i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
|
||||
static int
|
||||
fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
|
||||
int length)
|
||||
{
|
||||
struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
|
||||
int i = -1; /* signal error */
|
||||
u8 *a = (u8*)&addr;
|
||||
|
||||
if (i2c_wait4bus() < 0)
|
||||
if (i2c_wait4bus(adap) < 0)
|
||||
return -1;
|
||||
|
||||
if ((!length || alen > 0)
|
||||
&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
|
||||
&& __i2c_write(&a[4 - alen], alen) == alen)
|
||||
&& i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
|
||||
&& __i2c_write(adap, &a[4 - alen], alen) == alen)
|
||||
i = 0; /* No error so far */
|
||||
|
||||
if (length &&
|
||||
i2c_write_addr(dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
|
||||
i = __i2c_read(data, length);
|
||||
i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
|
||||
i = __i2c_read(adap, data, length);
|
||||
|
||||
writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
|
||||
writeb(I2C_CR_MEN, &device->cr);
|
||||
|
||||
if (i2c_wait4bus()) /* Wait until STOP */
|
||||
if (i2c_wait4bus(adap)) /* Wait until STOP */
|
||||
debug("i2c_read: wait4bus timed out\n");
|
||||
|
||||
if (i == length)
|
||||
@ -406,20 +386,22 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
|
||||
return -1;
|
||||
}
|
||||
|
||||
int
|
||||
i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
|
||||
static int
|
||||
fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
|
||||
u8 *data, int length)
|
||||
{
|
||||
struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
|
||||
int i = -1; /* signal error */
|
||||
u8 *a = (u8*)&addr;
|
||||
|
||||
if (i2c_wait4bus() >= 0
|
||||
&& i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
|
||||
&& __i2c_write(&a[4 - alen], alen) == alen) {
|
||||
i = __i2c_write(data, length);
|
||||
if (i2c_wait4bus(adap) >= 0 &&
|
||||
i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
|
||||
__i2c_write(adap, &a[4 - alen], alen) == alen) {
|
||||
i = __i2c_write(adap, data, length);
|
||||
}
|
||||
|
||||
writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
|
||||
if (i2c_wait4bus()) /* Wait until STOP */
|
||||
writeb(I2C_CR_MEN, &device->cr);
|
||||
if (i2c_wait4bus(adap)) /* Wait until STOP */
|
||||
debug("i2c_write: wait4bus timed out\n");
|
||||
|
||||
if (i == length)
|
||||
@ -428,72 +410,42 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
|
||||
return -1;
|
||||
}
|
||||
|
||||
int
|
||||
i2c_probe(uchar chip)
|
||||
static int
|
||||
fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
|
||||
{
|
||||
struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
|
||||
/* For unknow reason the controller will ACK when
|
||||
* probing for a slave with the same address, so skip
|
||||
* it.
|
||||
*/
|
||||
if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
|
||||
if (chip == (readb(&dev->adr) >> 1))
|
||||
return -1;
|
||||
|
||||
return i2c_read(chip, 0, 0, NULL, 0);
|
||||
return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
|
||||
}
|
||||
|
||||
int i2c_set_bus_num(unsigned int bus)
|
||||
static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
|
||||
unsigned int speed)
|
||||
{
|
||||
#if defined(CONFIG_I2C_MUX)
|
||||
if (bus < CONFIG_SYS_MAX_I2C_BUS) {
|
||||
i2c_bus_num = bus;
|
||||
} else {
|
||||
int ret;
|
||||
struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
|
||||
|
||||
ret = i2x_mux_select_mux(bus);
|
||||
if (ret)
|
||||
return ret;
|
||||
i2c_bus_num = 0;
|
||||
}
|
||||
i2c_bus_num_mux = bus;
|
||||
#else
|
||||
#ifdef CONFIG_SYS_I2C2_OFFSET
|
||||
if (bus > 1) {
|
||||
#else
|
||||
if (bus > 0) {
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
|
||||
i2c_bus_num = bus;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_set_bus_speed(unsigned int speed)
|
||||
{
|
||||
unsigned int i2c_clk = (i2c_bus_num == 1)
|
||||
? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
|
||||
|
||||
writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
|
||||
i2c_bus_speed[i2c_bus_num] =
|
||||
set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed);
|
||||
writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */
|
||||
writeb(0, &dev->cr); /* stop controller */
|
||||
set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
|
||||
writeb(I2C_CR_MEN, &dev->cr); /* start controller */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int i2c_get_bus_num(void)
|
||||
{
|
||||
#if defined(CONFIG_I2C_MUX)
|
||||
return i2c_bus_num_mux;
|
||||
#else
|
||||
return i2c_bus_num;
|
||||
/*
|
||||
* Register fsl i2c adapters
|
||||
*/
|
||||
U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
|
||||
fsl_i2c_write, fsl_i2c_set_bus_speed,
|
||||
CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
|
||||
0)
|
||||
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
|
||||
U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
|
||||
fsl_i2c_write, fsl_i2c_set_bus_speed,
|
||||
CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
|
||||
1)
|
||||
#endif
|
||||
}
|
||||
|
||||
unsigned int i2c_get_bus_speed(void)
|
||||
{
|
||||
return i2c_bus_speed[i2c_bus_num];
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
|
@ -459,14 +459,14 @@ unsigned long get_board_ddr_clk(void);
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x119000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
|
@ -275,12 +275,11 @@ extern unsigned long get_sdram_size(void);
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
|
||||
/* I2C EEPROM */
|
||||
#define CONFIG_CMD_EEPROM
|
||||
|
@ -451,15 +451,14 @@ combinations. this should be removed later
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400800 /* I2C speed and slave address*/
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/* I2C EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
|
@ -218,16 +218,16 @@
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/* Generic FreeScale hardware I2C support */
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/* I2C bus configuration */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
|
@ -82,11 +82,11 @@
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
|
||||
|
@ -145,11 +145,11 @@
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2c */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
/* DSPI and Serial Flash */
|
||||
|
@ -99,11 +99,11 @@
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x00000300
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_i2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
|
||||
#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
|
||||
|
@ -114,11 +114,11 @@
|
||||
#define CONFIG_HOSTNAME M5253DEMO
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x00000280
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
|
||||
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
|
||||
|
@ -109,11 +109,11 @@
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x00000300
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
|
||||
|
@ -109,11 +109,11 @@
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x00000300
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
|
||||
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
|
||||
|
@ -101,11 +101,11 @@
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
|
||||
|
@ -95,11 +95,11 @@
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
|
||||
|
@ -95,11 +95,11 @@
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
|
||||
|
@ -213,7 +213,7 @@
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2c */
|
||||
#undef CONFIG_FSL_I2C
|
||||
#undef CONFIG_SYS_FSL_I2C
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
|
||||
/* I2C speed and slave address */
|
||||
|
@ -156,11 +156,11 @@
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2c */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
/* DSPI and Serial Flash */
|
||||
|
@ -189,11 +189,11 @@
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2c */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSLI2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
/* DSPI and Serial Flash */
|
||||
|
@ -120,11 +120,11 @@
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x00008F00
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
/* PCI */
|
||||
|
@ -117,11 +117,11 @@
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x00008F00
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
/* PCI */
|
||||
|
@ -224,13 +224,14 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 120000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
|
@ -350,14 +350,15 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
|
||||
|
||||
/*
|
||||
* SPI on header J8
|
||||
|
@ -403,14 +403,15 @@
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
|
@ -347,13 +347,12 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave addr */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
|
||||
|
||||
/*
|
||||
* Board info - revision and where boot from
|
||||
|
@ -233,12 +233,12 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
|
||||
|
||||
/*
|
||||
* Config on-board EEPROM
|
||||
|
@ -326,12 +326,12 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
|
||||
|
||||
/*
|
||||
* Config on-board RTC
|
||||
|
@ -354,14 +354,15 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/* SPI */
|
||||
#define CONFIG_MPC8XXX_SPI
|
||||
|
@ -90,7 +90,7 @@
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_RTC_DS1337
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
|
||||
|
||||
/*
|
||||
@ -98,12 +98,15 @@
|
||||
*/
|
||||
|
||||
/* I2C */
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
|
||||
|
||||
@ -115,9 +118,6 @@
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
/* Don't probe these addresses: */
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
|
||||
{1, CONFIG_SYS_I2C_8574_ADDR2}, \
|
||||
@ -197,7 +197,7 @@
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
|
||||
#endif
|
||||
|
||||
@ -543,7 +543,7 @@ boards, we say we have two, but don't display a message if we find only one. */
|
||||
#define CONFIG_CMD_PCI
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#endif
|
||||
|
||||
|
@ -423,13 +423,12 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
|
||||
|
||||
/*
|
||||
* Config on-board RTC
|
||||
|
@ -287,14 +287,15 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
|
@ -341,13 +341,12 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
|
||||
|
||||
/*
|
||||
* Config on-board RTC
|
||||
|
@ -367,13 +367,12 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
|
||||
|
||||
/*
|
||||
* Config on-board RTC
|
||||
|
@ -434,14 +434,15 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
|
@ -260,12 +260,12 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/* RapidIO MMU */
|
||||
#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
|
||||
|
@ -283,12 +283,12 @@ extern unsigned long get_clock_freq(void);
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
|
@ -232,13 +232,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
|
@ -358,12 +358,12 @@ extern unsigned long get_clock_freq(void);
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
|
@ -281,12 +281,12 @@ extern unsigned long get_clock_freq(void);
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
|
@ -254,12 +254,12 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/* RapidIO MMU */
|
||||
#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
|
||||
|
@ -266,15 +266,16 @@ extern unsigned long get_clock_freq(void);
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
|
@ -302,14 +302,15 @@ extern unsigned long get_clock_freq(void);
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
|
@ -431,15 +431,16 @@
|
||||
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
|
@ -252,12 +252,12 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
|
@ -298,12 +298,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/*
|
||||
* RapidIO MMU
|
||||
|
@ -44,7 +44,6 @@
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_PCI_SKIP_HOST_BRIDGE
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_TSEC_ENET
|
||||
#define CONFIG_MPC8XXX_SPI
|
||||
#define CONFIG_HARD_SPI
|
||||
@ -52,13 +51,14 @@
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 100000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
|
@ -489,14 +489,15 @@ extern unsigned long get_sdram_size(void);
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/* I2C EEPROM */
|
||||
#undef CONFIG_ID_EEPROM
|
||||
|
@ -361,15 +361,15 @@
|
||||
#define CONFIG_FIT_VERBOSE
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
|
@ -204,13 +204,14 @@ extern unsigned long get_clock_freq(void);
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
|
@ -313,14 +313,15 @@ extern unsigned long get_clock_freq(void);
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
|
@ -367,15 +367,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
|
@ -225,15 +225,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_FIT_VERBOSE 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
|
@ -387,15 +387,16 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
|
@ -367,14 +367,14 @@ unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x118100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* RapidIO
|
||||
|
@ -245,14 +245,15 @@
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
|
@ -187,11 +187,11 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
|
||||
/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
|
@ -116,11 +116,11 @@
|
||||
#undef CONFIG_MCFPIT
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_HARD_I2C /* I2C with hw support */
|
||||
#define CONFIG_SYS_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 80000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
/*
|
||||
|
@ -192,15 +192,14 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_CMD_I2C
|
||||
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
/* Probing DP501 I2C-Bridge will hang */
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x30}, {0, 0x37}, {0, 0x3a}, \
|
||||
{0, 0x3b}, {0, 0x50} }
|
||||
|
@ -362,14 +362,14 @@
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x118100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
|
||||
|
||||
/*
|
||||
* RapidIO
|
||||
|
@ -262,14 +262,14 @@
|
||||
* I2C
|
||||
*/
|
||||
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x00000300
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0
|
||||
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_DS1338
|
||||
|
@ -204,14 +204,21 @@
|
||||
#endif /* CFG_SYS_RAMBOOT */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_MAX_I2C_BUS 1
|
||||
#define CONFIG_I2C_MUX
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_NUM_I2C_BUSES 4
|
||||
#define CONFIG_SYS_I2C_MAX_HOPS 1
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 200000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 200000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
|
||||
{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
|
||||
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
|
||||
{1, {I2C_NULL_HOP} } }
|
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
||||
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
|
||||
@ -219,7 +226,7 @@
|
||||
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
||||
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
||||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
||||
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
|
||||
#define CONFIG_SYS_DTT_BUS_NUM 1
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#define CONFIG_NAND_KMETER1
|
||||
@ -315,7 +322,7 @@
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_KM_DEF_ENV \
|
||||
CONFIG_KM_DEF_ARCH \
|
||||
"EEprom_ivm=pca9547:70:9\0" \
|
||||
"EEprom_ivm=2\0" \
|
||||
"newenv=" \
|
||||
"prot off 0xF00C0000 +0x40000 && " \
|
||||
"era 0xF00C0000 +0x40000\0" \
|
||||
|
@ -327,13 +327,14 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
|
@ -221,13 +221,15 @@
|
||||
/*
|
||||
* I2C buses and peripherals
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7f
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/* I2C RTC - M41T81 */
|
||||
#define CONFIG_RTC_M41T62
|
||||
|
@ -534,16 +534,16 @@
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
|
||||
|
||||
/*
|
||||
|
@ -304,14 +304,15 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C1_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} }
|
||||
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
|
||||
|
||||
/* TSEC */
|
||||
|
@ -444,12 +444,12 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
|
@ -289,12 +289,12 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/*
|
||||
* RapidIO MMU
|
||||
|
@ -235,14 +235,14 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 102124 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 102124
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 102124
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
|
||||
|
@ -178,17 +178,18 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
|
||||
#if 0
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */
|
||||
#else
|
||||
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
|
||||
#undef CONFIG_SYS_I2C_NOPROBES
|
||||
#endif
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
|
||||
/* RapdIO Map configuration, mapped 1:1.
|
||||
*/
|
||||
|
@ -198,12 +198,12 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#undef CONFIG_SYS_I2C_NOPROBES
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
|
||||
|
@ -445,14 +445,15 @@ unsigned long get_board_ddr_clk(void);
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x118100
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 100000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
|
||||
|
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
|
||||
#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
|
||||
|
||||
|
@ -237,16 +237,15 @@
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/
|
||||
#define CONFIG_FSL_I2C
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C1_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
|
||||
|
||||
#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
|
||||
|
@ -258,13 +258,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 100000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/* PEX8518 slave I2C interface */
|
||||
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
|
||||
|
@ -220,13 +220,14 @@
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/* I2C EEPROM */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
|
@ -258,13 +258,15 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/* PEX8518 slave I2C interface */
|
||||
#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
|
||||
|
@ -249,13 +249,14 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
|
||||
/* I2C DS7505 temperature sensor */
|
||||
#define CONFIG_DTT_LM75
|
||||
|
Loading…
Reference in New Issue
Block a user