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imx: mx6: hdmi: handle overflow condition

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If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to
do TMDS software reset and write to clear fc_invidconf register.
We need minimum 3 times to write to clear the fc_invidconf
register, so choose 5 loops here.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Signed-off-by: Sandor Yu <sandor.yu@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
This commit is contained in:
Peng Fan 2016-03-09 16:07:23 +08:00 committed by Anatolij Gustschin
parent 5167498575
commit 00b1d2d317
1 changed files with 12 additions and 1 deletions
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13
arch/arm/cpu/armv7/mx6/soc.c
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@ -548,7 +548,8 @@ void imx_setup_hdmi(void)
{ {
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
int reg; int reg, count;
u8 val;
/* Turn on HDMI PHY clock */ /* Turn on HDMI PHY clock */
reg = readl(&mxc_ccm->CCGR2); reg = readl(&mxc_ccm->CCGR2);
@ -565,6 +566,16 @@ void imx_setup_hdmi(void)
|(CHSCCDR_IPU_PRE_CLK_540M_PFD |(CHSCCDR_IPU_PRE_CLK_540M_PFD
<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr); writel(reg, &mxc_ccm->chsccdr);
/* Clear the overflow condition */
if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
/* TMDS software reset */
writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz);
val = readb(&hdmi->fc_invidconf);
/* Need minimum 3 times to write to clear the register */
for (count = 0 ; count < 5 ; count++)
writeb(val, &hdmi->fc_invidconf);
}
} }
#endif #endif