Merge with /home/wd/git/u-boot/master

CHANGELOG

@@ -14,6 +14,56 @@ Changes since U-Boot 1.1.4:
     by default with the Adder87x U-Boot port.
   Patch by Bryan O'Donoghue <bodonoghue@codehermit.ie>, 29 May 2006
 
+* Fix IxEthDB.h to compile again
+  Patch by Stefan Roese, 14 Jun 2006
+
+* Minor cleanup for PCS440EP board
+  Patch by Stefan Roese, 13 Jun 2006
+
+* Add MCF5282 support (without preloader)
+  relocate ichache_State to ram
+  u-boot can run from internal flash
+  Add EB+MCF-EV123 board support.
+  Add m68k Boards to MAKEALL
+  Patch from Jens Scharsig, 08 Aug 2005
+
+* Nios II - Add Altera EP1C20, EP1S10 and EP1S40 boards
+  Patch by Scott McNutt, 08 Jun 2006
+
+* Nios II - Add EPCS Controller bootrom work-around
+  -When booting from an epcs controller, the epcs bootrom may leave the
+  slave select in an asserted state causing soft reset hang. This
+  patch ensures slave select is negated at reset.
+  Patch by Scott McNutt, 08 Jun 2006
+
+* Update PK1C20 board
+  -Update base addresses for standard configuration
+  -Eliminate use of CACHE_BYPASS in board code
+  Patch by Scott McNutt, 08 Jun 2006
+
+* Nios II - Fix I/O Macros and mini-app stubs
+  -Fix asm/io.h macros
+  -Eliminate use of CACHE_BYPASS in cpu code
+  -Eliminate assembler warnings
+  -Fix mini-app stubs and force no small data
+  Patch by Scott McNutt, 08 Jun 2006
+
+* Fix U-Boot environment sector protection on MCC200 board
+
+* Minor cleanup for PCS440EP board
+
+* Update PCS440EP port to fit into one flash device (incl. environment)
+  Patch by Stefan Roese, 06 Jun 2006
+
+* Add support for PCS440EP board
+  Patch by Stefan Roese, 02 Jun 2006
+
+* Fix examples/Makefile; some build targets were lost
+
+* Fix watchdog handling in CFI flash driver
+  Just use udelay() when waiting for status changes which will
+  implicitely trigger the watchdog.
+
 * Fix PCI to memory window size problems on PM82x boards
   We use the "automatic" mode that was used for  the  MPC8266ADS  and
   MPC8272 boards. Eventually this should be used on all boards?]

MAINTAINERS

@@ -283,6 +283,7 @@ Stefan Roese <sr@denx.de>
 	ebony			PPC440GP
 	ocotea			PPC440GX
 	p3p440			PPC440GP
+	pcs440ep		PPC440EP
 	sycamore		PPC405GPr
 	walnut			PPC405GP
 	yellowstone		PPC440GR
@@ -516,6 +517,9 @@ Scott McNutt <smcnutt@psyent.com>
 
 	PCI5441			Nios-II
 	PK1C20			Nios-II
+	EP1C20			Nios-II
+	EP1S10			Nios-II
+	EP1S40			Nios-II
 
 #########################################################################
 # MicroBlaze Systems:							#

MAKEALL

@@ -71,11 +71,11 @@ LIST_4xx="	\
 	HH405		HUB405		JSE		KAREF		\
 	luan		METROBOX	MIP405		MIP405T		\
 	ML2		ml300		ocotea		OCRTC		\
-	ORSG		p3p440		PCI405		PIP405		\
-	PLU405		PMC405	        PPChameleonEVB	sbc405		\
-	VOH405		VOM405          W7OLMC		W7OLMG		\
-	walnut		WUH405		XPEDITE1K	yellowstone	\
-	yosemite							\
+	ORSG		p3p440		PCI405		pcs440ep	\
+	PIP405		PLU405		PMC405	        PPChameleonEVB	\
+	sbc405		VOH405		VOM405          W7OLMC		\
+	W7OLMG		walnut		WUH405		XPEDITE1K	\
+	yellowstone	yosemite					\
 "
 
 #########################################################################
@@ -255,29 +255,38 @@ LIST_x86="${LIST_I486}"
 #########################################################################
 
 LIST_nios="	\
-	ADNPESC1 ADNPESC1_base_32					\
+	ADNPESC1		ADNPESC1_base_32			\
 	ADNPESC1_DNPEVA2_base_32					\
-	DK1C20 DK1C20_standard_32					\
-	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20			\
+	DK1C20			DK1C20_standard_32			\
+	DK1S10			DK1S10_standard_32 DK1S10_mtx_ldk_20	\
 "
 
 #########################################################################
 ## Nios-II Systems
 #########################################################################
 
-LIST_nios2="PCI5441 PK1C20"
+LIST_nios2="	\
+	EP1C20		EP1S10		EP1S40				\
+	PCI5441		PK1C20						\
+"
 
 #########################################################################
 ## MicroBlaze Systems
 #########################################################################
 
-LIST_microblaze="suzaku"
+LIST_microblaze="	\
+	suzaku
+"
 
 #########################################################################
 ## ColdFire Systems
 #########################################################################
 
-LIST_coldfire="cobra5272 M5272C3 M5282EVB TASREG r5200 M5271EVB"
+LIST_coldfire="	\
+	cobra5272	EB+MCF-EV123	EB+MCF-EV123_internal		\
+	M5271EVB	M5272C3		M5282EVB	TASREG		\
+	r5200		M5271EVB					\
+"
 
 #-----------------------------------------------------------------------
 
@@ -292,7 +301,7 @@ build_target() {
 	${MAKE} distclean >/dev/null
 	${MAKE} ${target}_config
 	${MAKE} ${JOBS} all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
-	${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
+#	${CROSS_COMPILE:-ppc_8xx-}size u-boot | tee -a LOG/$target.MAKELOG
 }
 
 #-----------------------------------------------------------------------

Makefile

@@ -922,6 +922,9 @@ p3p440_config:	unconfig
 PCI405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pci405 esd
 
+pcs440ep_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx pcs440ep
+
 PIP405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pip405 mpl
 
@@ -1300,9 +1303,6 @@ VoVPN-GW_100MHz_config:		unconfig
 ZPC1900_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
 
-#========================================================================
-# M68K
-#========================================================================
 #########################################################################
 ## Coldfire
 #########################################################################
@@ -1310,6 +1310,19 @@ ZPC1900_config: unconfig
 cobra5272_config :		unconfig
 	@./mkconfig $(@:_config=) m68k mcf52x2 cobra5272
 
+EB+MCF-EV123_config :		unconfig
+	@ >include/config.h
+	@echo "TEXT_BASE = 0xFFE00000"|tee board/BuS/EB+MCF-EV123/textbase.mk
+	@./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
+
+EB+MCF-EV123_internal_config :	unconfig
+	@ >include/config.h
+	@echo "TEXT_BASE = 0xF0000000"|tee board/BuS/EB+MCF-EV123/textbase.mk
+	@./mkconfig EB+MCF-EV123 m68k mcf52x2 EB+MCF-EV123 BuS
+
+M5271EVB_config :		unconfig
+	@./mkconfig $(@:_config=) m68k mcf52x2 m5271evb
+
 M5272C3_config :		unconfig
 	@./mkconfig $(@:_config=) m68k mcf52x2 m5272c3
 
@@ -1322,9 +1335,6 @@ TASREG_config :		unconfig
 r5200_config :		unconfig
 	@./mkconfig $(@:_config=) m68k mcf52x2 r5200
 
-M5271EVB_config :		unconfig
-	@./mkconfig $(@:_config=) m68k mcf52x2 m5271evb
-
 #########################################################################
 ## MPC83xx Systems
 #########################################################################
@@ -1903,6 +1913,15 @@ ADNPESC1_config: unconfig
 ## Nios-II
 #########################################################################
 
+EP1C20_config : unconfig
+	@./mkconfig  EP1C20 nios2 nios2 ep1c20 altera
+
+EP1S10_config : unconfig
+	@./mkconfig  EP1S10 nios2 nios2 ep1s10 altera
+
+EP1S40_config : unconfig
+	@./mkconfig  EP1S40 nios2 nios2 ep1s40 altera
+
 PK1C20_config : unconfig
 	@./mkconfig  PK1C20 nios2 nios2 pk1c20 psyent
 

README

@@ -322,6 +322,7 @@ The following options need to be configured:
 		------------------------
 
 		CONFIG_PCI5441 CONFIG_PK1C20
+		CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40
 
 
 - CPU Module Type: (if CONFIG_COGENT is defined)

board/BuS/EB+MCF-EV123/EB+MCF-EV123.c

@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include "asm/m5282.h"
+#include "VCxK.h"
+
+int checkboard (void)
+{
+	puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
+#if (TEXT_BASE ==  CFG_INT_FLASH_BASE)
+	puts ("       Boot from Internal FLASH\n");
+#endif
+
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	int size,i;
+
+	size = 0;
+	MCFSDRAMC_DCR =	MCFSDRAMC_DCR_RTIM_6
+			| MCFSDRAMC_DCR_RC((15 * CFG_CLK)>>4);
+	#ifdef CFG_SDRAM_BASE0
+
+		MCFSDRAMC_DACR0 =	MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0)
+					| MCFSDRAMC_DACR_CASL(1)
+ 					| MCFSDRAMC_DACR_CBM(3)
+					| MCFSDRAMC_DACR_PS_16);
+
+		MCFSDRAMC_DMR0 =	MCFSDRAMC_DMR_BAM_16M
+					| MCFSDRAMC_DMR_V;
+
+		MCFSDRAMC_DACR0 |= 	MCFSDRAMC_DACR_IP;
+
+		*(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5;
+		MCFSDRAMC_DACR0 |=	MCFSDRAMC_DACR_RE;
+		for (i=0; i < 2000; i++)
+			asm(" nop");
+		mbar_writeLong(MCFSDRAMC_DACR0, mbar_readLong(MCFSDRAMC_DACR0)
+								    | MCFSDRAMC_DACR_IMRS);
+		*(unsigned int *)(CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
+		size += CFG_SDRAM_SIZE * 1024 * 1024;
+	#endif
+	#ifdef CFG_SDRAM_BASE1
+		MCFSDRAMC_DACR1 =	MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1)
+					| MCFSDRAMC_DACR_CASL(1)
+ 					| MCFSDRAMC_DACR_CBM(3)
+					| MCFSDRAMC_DACR_PS_16;
+
+		MCFSDRAMC_DMR1 = 	MCFSDRAMC_DMR_BAM_16M
+					| MCFSDRAMC_DMR_V;
+
+		MCFSDRAMC_DACR1 |=	MCFSDRAMC_DACR_IP;
+
+		*(unsigned short *)(CFG_SDRAM_BASE1) = 0xA5A5;
+		MCFSDRAMC_DACR1 |=	MCFSDRAMC_DACR_RE;
+		for (i=0; i < 2000; i++)
+			asm(" nop");
+		MCFSDRAMC_DACR1 |= 	MCFSDRAMC_DACR_IMRS;
+		*(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
+		size += CFG_SDRAM_SIZE1 * 1024 * 1024;
+	#endif
+	return size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+	init_vcxk();
+	return 1;
+}
+
+/*---------------------------------------------------------------------------*/
+
+int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	int rcode = 0;
+	ulong source;
+
+	switch (argc) {
+	case 2:
+		source = simple_strtoul(argv[1],NULL,16);
+		vcxk_loadimage(source);
+		rcode = 0;
+		break;
+	default:
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		rcode = 1;
+		break;
+	}
+	return rcode;
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+	vcimage,	2,	0,	do_vcimage,
+	"vcimage - loads an image to Display\n",
+	"vcimage addr\n"
+);
+
+/* EOF EB+MCF-EV123c */

board/BuS/EB+MCF-EV123/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o cfm_flash.o flash.o VCxK.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/BuS/EB+MCF-EV123/VCxK.c

@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5282.h>
+#include "VCxK.h"
+
+vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
+#define VCXK_BWS vcxk_bws
+
+static ulong vcxk_driver;
+
+
+ulong search_vcxk_driver(void);
+void vcxk_cls(void);
+void vcxk_setbrightness(short brightness);
+int vcxk_request(void);
+int vcxk_acknowledge_wait(void);
+void vcxk_clear(void);
+
+int init_vcxk(void)
+{
+	VIDEO_Invert_CFG &= ~VIDEO_Invert_IO;
+	VIDEO_INVERT_PORT |= VIDEO_INVERT_PIN;
+	VIDEO_INVERT_DDR  |= VIDEO_INVERT_PIN;
+
+	VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
+	VIDEO_REQUEST_DDR |= VIDEO_REQUEST_PIN;
+
+	VIDEO_ACKNOWLEDGE_DDR &= ~VIDEO_ACKNOWLEDGE_PIN;
+
+	vcxk_driver = search_vcxk_driver();
+	if (vcxk_driver)
+	{
+		/* use flash resist driver */
+	}
+	else
+	{
+		vcxk_cls();
+		vcxk_cls();
+		vcxk_setbrightness(1000);
+	}
+	VIDEO_ENABLE_DDR |= VIDEO_ENABLE_PIN;
+	VIDEO_ENABLE_PORT |= VIDEO_ENABLE_PIN;
+	VIDEO_ENABLE_PORT &= ~VIDEO_ENABLE_PIN;
+	return 1;
+}
+
+void 	vcxk_loadimage(ulong source)
+{
+	int cnt;
+	vcxk_acknowledge_wait();
+	for (cnt=0; cnt<16384; cnt++)
+	{
+		VCXK_BWS[cnt*2] = (*(vu_char*) source);
+		source++;
+	}
+	vcxk_request();
+}
+
+void vcxk_cls(void)
+{
+	vcxk_acknowledge_wait();
+	vcxk_clear();
+	vcxk_request();
+}
+
+void vcxk_clear(void)
+{
+	int cnt;
+	for (cnt=0; cnt<16384; cnt++)
+	{
+		VCXK_BWS[cnt*2] = 0x00;
+	}
+}
+
+void vcxk_setbrightness(short brightness)
+{
+	VCXK_BWS[0x8000]=(brightness >> 4) +2;
+	VCXK_BWS[0xC000]= (brightness + 23) >> 8;
+	VCXK_BWS[0xC001]= (brightness + 23) & 0xFF;
+}
+
+int vcxk_request(void)
+{
+	if (vcxk_driver)
+	{
+		/* use flash resist driver */
+	}
+	else
+	{
+		VIDEO_REQUEST_PORT &= ~VIDEO_REQUEST_PIN;
+		VIDEO_REQUEST_PORT |= VIDEO_REQUEST_PIN;
+	}
+	return 1;
+}
+
+int vcxk_acknowledge_wait(void)
+{
+	if (vcxk_driver)
+	{
+		/* use flash resist driver */
+	}
+	else
+	{
+		while (!(VIDEO_ACKNOWLEDGE_PORT & VIDEO_ACKNOWLEDGE_PIN));
+	}
+	return 1;
+}
+
+ulong search_vcxk_driver(void)
+{
+	return 0;
+}
+
+/* eof */

board/BuS/EB+MCF-EV123/VCxK.h

@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __VCXK_H_
+#define __VCXK_H_
+
+extern int init_vcxk(void);
+void 	vcxk_loadimage(ulong source);
+
+#define VIDEO_ACKNOWLEDGE_PORT	MCFGPTB_GPTPORT
+#define VIDEO_ACKNOWLEDGE_DDR 	MCFGPTB_GPTDDR
+#define VIDEO_ACKNOWLEDGE_PIN	0x0001
+
+#define VIDEO_ENABLE_PORT    	MCFGPTB_GPTPORT
+#define VIDEO_ENABLE_DDR 	MCFGPTB_GPTDDR
+#define VIDEO_ENABLE_PIN	0x0002
+
+#define VIDEO_REQUEST_PORT   	MCFGPTB_GPTPORT
+#define VIDEO_REQUEST_DDR 	MCFGPTB_GPTDDR
+#define VIDEO_REQUEST_PIN	0x0004
+
+#define VIDEO_Invert_CFG	MCFGPIO_PEPAR
+#define VIDEO_Invert_IO		MCFGPIO_PEPAR_PEPA2
+#define VIDEO_INVERT_PORT   	MCFGPIO_PORTE
+#define VIDEO_INVERT_DDR 	MCFGPIO_DDRE
+#define VIDEO_INVERT_PIN	MCFGPIO_PORT2
+
+#endif

board/BuS/EB+MCF-EV123/cfm_flash.c

@@ -0,0 +1,212 @@
+/*
+ * Basic Flash Driver for Freescale MCF 5281/5282 internal FLASH
+ *
+ * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5282.h>
+#include  "cfm_flash.h"
+
+#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
+
+#if (CFG_CLK>20000000)
+	#define CFM_CLK  (((long) CFG_CLK / (400000 * 8) + 1) | 0x40)
+#else
+	#define CFM_CLK  ((long) CFG_CLK / 400000 + 1)
+#endif
+
+#define cmf_backdoor_address(addr)	(((addr) & 0x0007FFFF) | 0x04000000 | \
+					 (CFG_MBAR & 0xC0000000))
+
+void cfm_flash_print_info (flash_info_t * info)
+{
+	printf ("Freescale: ");
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FREESCALE_ID_MCF5281 & FLASH_TYPEMASK:
+		printf ("MCF5281 internal FLASH\n");
+		break;
+	case FREESCALE_ID_MCF5282 & FLASH_TYPEMASK:
+		printf ("MCF5282 internal FLASH\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+}
+
+void cfm_flash_init (flash_info_t * info)
+{
+	int sector;
+	ulong protection;
+	MCFCFM_MCR = 0;
+	MCFCFM_CLKD = CFM_CLK;
+	debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
+	 	CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
+		CFG_CLK);
+	MCFCFM_SACC = 0;
+	MCFCFM_DACC = 0;
+
+	if (MCFCFM_SEC & MCFCFM_SEC_KEYEN)
+		puts("CFM backdoor access is enabled\n");
+	if (MCFCFM_SEC & MCFCFM_SEC_SECSTAT)
+		puts("CFM securety is enabled\n");
+
+	#ifdef CONFIG_M5281
+		info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
+				 (FREESCALE_ID_MCF5281 & FLASH_TYPEMASK);
+		info->size = 256*1024;
+		info->sector_count = 16;
+	#else
+		info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
+				 (FREESCALE_ID_MCF5282 & FLASH_TYPEMASK);
+		info->size = 512*1024;
+		info->sector_count = 32;
+	#endif
+	protection = MCFCFM_PROT;
+	for (sector = 0; sector < info->sector_count; sector++)
+	{
+		if (sector == 0)
+		{
+			info->start[sector] = CFG_INT_FLASH_BASE;
+		}
+		else
+		{
+			info->start[sector] = info->start[sector-1] + 0x04000;
+		}
+		info->protect[sector] = protection & 1;
+		protection >>= 1;
+	}
+}
+
+int cfm_flash_readycheck(int checkblank)
+{
+	int	rc;
+	unsigned char state;
+
+	rc	= ERR_OK;
+	while (!(MCFCFM_USTAT & MCFCFM_USTAT_CCIF));
+	state = MCFCFM_USTAT;
+	if (state & MCFCFM_USTAT_ACCERR)
+	{
+		debug ("%s(): CFM access error",__FUNCTION__);
+		rc = ERR_PROG_ERROR;
+	}
+	if (state & MCFCFM_USTAT_PVIOL)
+	{
+		debug ("%s(): CFM protection violation",__FUNCTION__);
+		rc = ERR_PROTECTED;
+	}
+	if (checkblank)
+	{
+		if (!(state & MCFCFM_USTAT_BLANK))
+		{
+			debug ("%s(): CFM erras error",__FUNCTION__);
+			rc = ERR_NOT_ERASED;
+		}
+	}
+	MCFCFM_USTAT = state & 0x34; /* reset state */
+	return rc;
+}
+
+/* Erase 16KiB = 8 2KiB pages */
+
+int cfm_flash_erase_sector (flash_info_t * info, int sector)
+{
+	ulong address;
+	int page;
+	int rc;
+	rc= ERR_OK;
+	address = cmf_backdoor_address(info->start[sector]);
+	for (page=0; (page<8) && (rc==ERR_OK); page++)
+	{
+		*(volatile __u32*) address = 0;
+		MCFCFM_CMD = MCFCFM_CMD_PGERS;
+		MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
+		rc = cfm_flash_readycheck(0);
+		if (rc==ERR_OK)
+		{
+			*(volatile __u32*) address = 0;
+			MCFCFM_CMD = MCFCFM_CMD_PGERSVER;
+			MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
+			rc = cfm_flash_readycheck(1);
+		}
+		address += 0x800;
+	}
+	return rc;
+}
+
+int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+	ulong dest, data;
+
+	rc = ERR_OK;
+	if (addr & 3)
+	{
+		debug ("Byte and Word alignment not supported\n");
+		rc = ERR_ALIGN;
+	}
+	if (cnt & 3)
+	{
+		debug ("Byte and Word transfer not supported\n");
+		rc = ERR_ALIGN;
+	}
+	dest = cmf_backdoor_address(addr);
+	while ((cnt>=4) && (rc == ERR_OK))
+	{
+		data =*((volatile u32 *) src);
+		*(volatile u32*) dest = data;
+		MCFCFM_CMD = MCFCFM_CMD_PGM;
+		MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
+		rc = cfm_flash_readycheck(0);
+		if (*(volatile u32*) addr != data) rc = ERR_PROG_ERROR;
+		src +=4;
+		dest +=4;
+		addr +=4;
+		cnt -=4;
+	}
+	return rc;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+
+int cfm_flash_protect(flash_info_t * info,long sector,int prot)
+{
+	int rc;
+
+	rc= ERR_OK;
+	if (prot)
+	{
+		MCFCFM_PROT |= (1<<sector);
+		info->protect[sector]=1;
+	}
+	else
+	{
+		MCFCFM_PROT &= ~(1<<sector);
+		info->protect[sector]=0;
+	}
+	return rc;
+}
+
+#endif
+
+#endif

board/BuS/EB+MCF-EV123/cfm_flash.h

@@ -0,0 +1,40 @@
+/*
+ * Basic Flash Driver for Freescale MCF 5282 internal FLASH
+ *
+ * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CFM_FLASH_H_
+#define __CFM_FLASH_H_
+
+#define	FREESCALE_MANUFACT 0xFACFFACF
+#define	FREESCALE_ID_MCF5281 0x5281
+#define	FREESCALE_ID_MCF5282 0x5282
+
+extern void cfm_flash_print_info (flash_info_t * info);
+extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
+extern void cfm_flash_init (flash_info_t * info);
+extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
+#ifdef CFG_FLASH_PROTECTION
+extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
+#endif
+
+#endif

board/BuS/EB+MCF-EV123/config.mk

@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/textbase.mk
+ifndef TEXT_BASE
+TEXT_BASE = 0xFE000000
+endif

board/BuS/EB+MCF-EV123/flash.c

@@ -0,0 +1,413 @@
+/*
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * Based On
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include  "cfm_flash.h"
+
+#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		switch (info->flash_id & FLASH_TYPEMASK) {
+		case (AMD_ID_LV160B & FLASH_TYPEMASK):
+			printf ("AM29LV160B (16Bit)\n");
+			break;
+		default:
+			printf ("Unknown Chip Type\n");
+			break;
+		}
+		break;
+	case FREESCALE_MANUFACT & FLASH_VENDMASK:
+		cfm_flash_print_info (info);
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	puts ("  Size: ");
+	if ((info->size >> 20) > 0)
+	{
+		printf ("%ld MiB",info->size >> 20);
+	}
+	else
+	{
+		printf ("%ld KiB",info->size >> 10);
+	}
+	printf (" in %d Sectors\n", info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 4) == 0) {
+			printf ("\n    ");
+		}
+		printf ("%02d: %08lX%s  ", i,info->start[i],
+			info->protect[i] ? " P" : "  ");
+	}
+	printf ("\n\n");
+}
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		switch (i)
+		{
+		case 1:
+			flash_info[i].flash_id =
+				(AMD_MANUFACT & FLASH_VENDMASK) |
+				(AMD_ID_LV160B & FLASH_TYPEMASK);
+			flash_info[i].size = FLASH_BANK_SIZE;
+			flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+			flashbase = PHYS_FLASH_1;
+			for (j = 0; j < flash_info[i].sector_count; j++) {
+				if (j == 0) {
+					/* 1st is 16 KiB */
+					flash_info[i].start[j] = flashbase;
+				}
+				if ((j >= 1) && (j <= 2)) {
+				/* 2nd and 3rd are 8 KiB */
+					flash_info[i].start[j] =
+						flashbase + 0x4000 + 0x2000 * (j - 1);
+				}
+				if (j == 3) {
+					/* 4th is 32 KiB */
+					flash_info[i].start[j] = flashbase + 0x8000;
+				}
+				if ((j >= 4) && (j <= 34)) {
+					/* rest is 256 KiB */
+					flash_info[i].start[j] =
+						flashbase + 0x10000 + 0x10000 * (j - 4);
+				}
+			}
+			break;
+		case 0:
+			cfm_flash_init (&flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+		}
+
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + 0xffff, &flash_info[0]);
+
+	return size;
+}
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(info->start[0] + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(info->start[0] + (0x000002AA<<1)))
+
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define ERR_READY -1
+
+int amd_flash_erase_sector(flash_info_t * info, int sector)
+{
+	int state;
+	ulong result;
+
+	volatile u16 *addr =
+				(volatile u16 *) (info->start[sector]);
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	*addr = CMD_ERASE_CONFIRM;
+
+	/* wait until flash is ready */
+	state = 0;
+	set_timer (0);
+
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+			state = ERR_TIMOUT;
+		}
+
+		if (!state && (result & 0xFFFF) & BIT_ERASE_DONE)
+			state = ERR_READY;
+	}
+	while (!state);
+	if (state == ERR_READY)
+		state = ERR_OK;
+
+	MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+	return state;
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int iflag, cflag;
+	int sector;
+	int rc;
+
+	rc = ERR_OK;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+	{
+		rc = ERR_UNKNOWN_FLASH_TYPE;
+	} /* (info->flash_id == FLASH_UNKNOWN) */
+
+	if ((s_first < 0) || (s_first > s_last) || s_last >= info->sector_count)
+	{
+		rc = ERR_INVAL;
+	}
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	for (sector = s_first; (sector <= s_last) && (rc == ERR_OK); sector++) {
+
+		if (info->protect[sector])
+		{
+			putc('P'); /*  protected sector will not erase */
+		}
+		else
+		{
+			/* erase on unprotected sector */
+			puts("E\b");
+			switch (info->flash_id & FLASH_VENDMASK)
+			{
+			case (AMD_MANUFACT & FLASH_VENDMASK):
+				rc = amd_flash_erase_sector(info,sector);
+				break;
+			case (FREESCALE_MANUFACT & FLASH_VENDMASK):
+				rc = cfm_flash_erase_sector(info,sector);
+				break;
+			default:
+				return ERR_UNKNOWN_FLASH_VENDOR;
+			}
+			putc('.');
+		}
+	}
+	if (rc!=ERR_OK)
+	{
+		printf ("\n   ");
+		flash_perror (rc);
+	}
+	else
+	{
+		printf (" done\n");
+	}
+
+	udelay (10000);	/* allow flash to settle - wait 10 ms */
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+  		icache_enable ();
+
+	return rc;
+}
+
+volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
+{
+	volatile u16 *addr;
+	ulong result;
+	int cflag, iflag;
+	int state;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	addr = (volatile u16 *) dest;
+
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	state = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+				state = ERR_TIMOUT;
+		}
+		if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
+			state = ERR_READY;
+
+	} while (!state);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (state == ERR_READY)
+		state = ERR_OK;
+	if ((*addr != data) && (state != ERR_TIMOUT))
+		state = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return state;
+}
+
+int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+	ulong dest;
+	u16 data;
+
+	rc = ERR_OK;
+	if (addr & 1)
+	{
+		debug ("Byte alignment not supported\n");
+		rc = ERR_ALIGN;
+	}
+	if (cnt & 1)
+	{
+		debug ("Byte transfer not supported\n");
+		rc = ERR_ALIGN;
+	}
+
+	dest = addr;
+	while ((cnt>=2) && (rc == ERR_OK))
+	{
+		data =*((volatile u16 *) src);
+		rc=amd_write_word (info,dest,data);
+		src +=2;
+		dest +=2;
+		cnt -=2;
+	}
+	return rc;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case (AMD_MANUFACT & FLASH_VENDMASK):
+			rc = amd_flash_write_buff(info,src,addr,cnt);
+			break;
+		case (FREESCALE_MANUFACT & FLASH_VENDMASK):
+			rc = cfm_flash_write_buff(info,src,addr,cnt);
+			break;
+		default:
+			rc = ERR_UNKNOWN_FLASH_VENDOR;
+	}
+	return rc;
+
+}
+int amd_flash_protect(flash_info_t * info,long sector,int prot)
+{
+	int rc;
+	rc= ERR_OK;
+	if (prot)
+	{
+		info->protect[sector]=1;
+	}
+	else
+	{
+		info->protect[sector]=0;
+	}
+	return rc;
+}
+
+#ifdef CFG_FLASH_PROTECTION
+
+int flash_real_protect(flash_info_t * info,long sector,int prot)
+{
+	int rc;
+
+	switch (info->flash_id & FLASH_VENDMASK)
+	{
+		case (AMD_MANUFACT & FLASH_VENDMASK):
+			rc = amd_flash_protect(info,sector,prot);
+			break;
+		case (FREESCALE_MANUFACT & FLASH_VENDMASK):
+			rc = cfm_flash_protect(info,sector,prot);
+			break;
+		default:
+			rc = ERR_UNKNOWN_FLASH_VENDOR;
+	}
+	return rc;
+}
+
+#endif

board/BuS/EB+MCF-EV123/textbase.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0xF0000000

board/BuS/EB+MCF-EV123/u-boot.lds

@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf52x2/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/string.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o	(.text)
+    lib_generic/zlib.o	(.text)
+
+/*    . = env_offset; */
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+    .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/altera/common/AMDLV065D.c

@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#if defined(CONFIG_NIOS)
+#include <nios.h>
+#else
+#include <asm/io.h>
+#endif
+
+#define SECTSZ		(64 * 1024)
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*----------------------------------------------------------------------*/
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = CFG_FLASH_SIZE;
+	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
+
+	addr = CFG_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+		fli->protect[i] = 1;
+	}
+
+	return (CFG_FLASH_SIZE);
+}
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+	int i, k;
+	int erased;
+	unsigned long *addr;
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+
+		/* Check if whole sector is erased */
+		erased = 1;
+		addr = (unsigned long *) info->start[i];
+		for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
+			if ( readl(addr++) != (unsigned long)-1) {
+				erased = 0;
+				break;
+			}
+		}
+
+		/* Print the info */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	unsigned char *addr = (unsigned char *) info->start[0];
+	unsigned char *addr2;
+	int prot, sect;
+	ulong start;
+
+	/* Some sanity checking */
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* It's ok to erase multiple sectors provided we don't delay more
+	 * than 50 usec between cmds ... at which point the erase time-out
+	 * occurs. So don't go and put printf() calls in the loop ... it
+	 * won't be very helpful ;-)
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (unsigned char *) info->start[sect];
+			writeb (addr, 0xaa);
+			writeb (addr,  0x55);
+			writeb (addr,  0x80);
+			writeb (addr,  0xaa);
+			writeb (addr,  0x55);
+			writeb (addr2, 0x30);
+			/* Now just wait for 0xff & provide some user
+			 * feedback while we wait.
+			 */
+			start = get_timer (0);
+			while ( readb (addr2) != 0xff) {
+				udelay (1000 * 1000);
+				putc ('.');
+				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+					printf ("timeout\n");
+					return 1;
+				}
+			}
+		}
+	}
+	printf ("\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+
+	vu_char *cmd = (vu_char *) info->start[0];
+	vu_char *dst = (vu_char *) addr;
+	unsigned char b;
+	ulong start;
+
+	while (cnt) {
+		/* Check for sufficient erase */
+		b = *src;
+		if ((readb (dst) & b) != b) {
+			printf ("%02x : %02x\n", readb (dst), b);
+			return (2);
+		}
+
+		writeb (cmd,  0xaa);
+		writeb (cmd,  0x55);
+		writeb (cmd,  0xa0);
+		writeb (dst, b);
+
+		/* Verify write */
+		start = get_timer (0);
+		while (readb (dst) != b) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				return 1;
+			}
+		}
+		dst++;
+		src++;
+		cnt--;
+	}
+
+	return (0);
+}

board/altera/common/epled.c

@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <nios2-io.h>
+#include <status_led.h>
+
+/* The LED port is configured as output only, so we
+ * must track the state manually.
+ */
+static led_id_t val = 0;
+
+void __led_init (led_id_t mask, int state)
+{
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+
+	if (state == STATUS_LED_ON)
+		val &= ~mask;
+	else
+		val |= mask;
+	writel (&pio->data, val);
+}
+
+void __led_set (led_id_t mask, int state)
+{
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+
+	if (state == STATUS_LED_ON)
+		val &= ~mask;
+	else
+		val |= mask;
+	writel (&pio->data, val);
+}
+
+void __led_toggle (led_id_t mask)
+{
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+
+	val ^= mask;
+	writel (&pio->data, val);
+}

board/altera/ep1c20/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+COMOBJS := ../common/AMDLV065D.o ../common/epled.o
+
+OBJS	:= $(BOARD).o $(COMOBJS)
+
+SOBJS	=
+
+$(LIB): $(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/altera/ep1c20/config.mk

@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01fc0000
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif

board/altera/ep1c20/ep1c20.c

@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("BOARD : Altera EP-1C20\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}

board/altera/ep1c20/u-boot.lds

@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios2/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(.rodata)
+	  *(.rodata.*)
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}

board/altera/ep1s10/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+COMOBJS := ../common/AMDLV065D.o ../common/epled.o
+
+OBJS	:= $(BOARD).o $(COMOBJS)
+
+SOBJS	=
+
+$(LIB): $(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/altera/ep1s10/config.mk

@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01fc0000
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif

board/altera/ep1s10/ep1s10.c

@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("BOARD : Altera EP-1S10\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}

board/altera/ep1s10/u-boot.lds

@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios2/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(.rodata)
+	  *(.rodata.*)
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}

board/altera/ep1s40/Makefile

@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+COMOBJS := ../common/AMDLV065D.o ../common/epled.o
+
+OBJS	:= $(BOARD).o $(COMOBJS)
+
+SOBJS	=
+
+$(LIB): $(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/altera/ep1s40/config.mk

@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01fc0000
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif

board/altera/ep1s40/ep1s40.c

@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int checkboard (void)
+{
+	puts ("BOARD : Altera EP-1S40\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}

board/altera/ep1s40/u-boot.lds

@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-littlenios2")
+OUTPUT_ARCH(nios2)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios2/start.o (.text)
+	  *(.text)
+	  *(.text.*)
+	  *(.gnu.linkonce.t*)
+	  *(.rodata)
+	  *(.rodata.*)
+	  *(.gnu.linkonce.r*)
+	}
+	. = ALIGN (4);
+	_etext = .;
+	PROVIDE (etext = .);
+
+	/* CMD TABLE - sandwich this in between text and data so
+	 * the initialization code relocates the command table as
+	 * well -- admittedly, this is just pure laziness ;-)
+	 */
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+	  *(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	/* INIT DATA sections - "Small" data (see the gcc -G option)
+	 * is always gp-relative. Here we make all init data sections
+	 * adjacent to simplify the startup code -- and provide
+	 * the global pointer for gp-relative access.
+	 */
+	_data = .;
+	.data :
+	{
+	  *(.data)
+	  *(.data.*)
+	  *(.gnu.linkonce.d*)
+	}
+
+	. = ALIGN(16);
+	_gp = .;			/* Global pointer addr */
+	PROVIDE (gp = .);
+
+	.sdata :
+	{
+	  *(.sdata)
+	  *(.sdata.*)
+	  *(.gnu.linkonce.s.*)
+	}
+	. = ALIGN(4);
+
+	_edata = .;
+	PROVIDE (edata = .);
+
+	/* UNINIT DATA - Small uninitialized data is first so it's
+	 * adjacent to sdata and can be referenced via gp. The normal
+	 * bss follows. We keep it adjacent to simplify init code.
+	 */
+	__bss_start = .;
+	.sbss :
+	{
+	  *(.sbss)
+	  *(.sbss.*)
+	  *(.gnu.linkonce.sb.*)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	.bss :
+	{
+	  *(.bss)
+	  *(.bss.*)
+	  *(.dynbss)
+	  *(COMMON)
+	  *(.scommon)
+	}
+	. = ALIGN(4);
+	_end = .;
+	PROVIDE (end = .);
+
+	/* DEBUG -- symbol table, string table, etc. etc.
+	 */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug		0 : { *(.debug) }
+	.line		0 : { *(.line) }
+	.debug_srcinfo	0 : { *(.debug_srcinfo) }
+	.debug_sfnames	0 : { *(.debug_sfnames) }
+	.debug_aranges	0 : { *(.debug_aranges) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_info	0 : { *(.debug_info) }
+	.debug_abbrev	0 : { *(.debug_abbrev) }
+	.debug_line	0 : { *(.debug_line) }
+	.debug_frame	0 : { *(.debug_frame) }
+	.debug_str	0 : { *(.debug_str) }
+	.debug_loc	0 : { *(.debug_loc) }
+	.debug_macinfo	0 : { *(.debug_macinfo) }
+	.debug_weaknames 0 : { *(.debug_weaknames) }
+	.debug_funcnames 0 : { *(.debug_funcnames) }
+	.debug_typenames 0 : { *(.debug_typenames) }
+	.debug_varnames	 0 : { *(.debug_varnames) }
+}

board/mcc200/mcc200.c

@@ -242,7 +242,7 @@ int misc_init_r (void)
 		/* Unprotect the upper bank of the Flash */
 		*(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
 		flash_protect (FLAG_PROTECT_CLEAR,
-			       flash_info[0].start[0],
+			       flash_info[0].start[0] + flash_info[0].size / 2,
 			       (flash_info[0].start[0] + flash_info[0].size) / 2 - 1,
 			       &flash_info[0]);
 		*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);

board/pcs440ep/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/pcs440ep/config.mk

@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# PCS440EP board
+#
+
+#TEXT_BASE = 0x00001000
+
+ifeq ($(ramsym),1)
+TEXT_BASE = 0xFBD00000
+else
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+endif

board/pcs440ep/flash.c

@@ -0,0 +1,608 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#ifndef CFG_FLASH_READ0
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#endif
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*
+ * Functions
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data);
+static ulong flash_get_size(vu_long *addr, flash_info_t *info);
+
+unsigned long flash_init(void)
+{
+	unsigned long size_b0, size_b1;
+	int i;
+	unsigned long base_b0, base_b1;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	base_b0 = FLASH_BASE0_PRELIM;
+	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+				size_b0, size_b0 << 20);
+	}
+
+	base_b1 = FLASH_BASE1_PRELIM;
+	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
+
+	return (size_b0 + size_b1);
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	case FLASH_MAN_SST:	printf ("SST ");		break;
+	case FLASH_MAN_EXCEL:	printf ("Excel Semiconductor "); break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM040:	printf ("AM29LV040B (4 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 M, top sector)\n");
+		break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL322T:	printf ("AM29DL322T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL322B:	printf ("AM29DL322B (32 M, bottom sector)\n");
+		break;
+	case FLASH_AMDL323T:	printf ("AM29DL323T (32 M, top sector)\n");
+		break;
+	case FLASH_AMDL323B:	printf ("AM29DL323B (32 M, bottom sector)\n");
+		break;
+	case FLASH_SST020:	printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
+		break;
+	case FLASH_SST040:	printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
+		break;
+	default:		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+#ifdef CFG_FLASH_EMPTY_INFO
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+			size = info->start[i+1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+		for (k=0; k<size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		/* print empty and read-only info */
+		printf (" %08lX%s%s",
+			info->start[i],
+			erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+#endif
+
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size(vu_long *addr, flash_info_t *info)
+{
+	short i;
+	short n;
+	volatile CFG_FLASH_WORD_SIZE value;
+	ulong base = (ulong)addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (volatile CFG_FLASH_WORD_SIZE *)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+
+	value = addr2[CFG_FLASH_READ0];
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+		info->flash_id = FLASH_MAN_SST;
+		break;
+	case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+		info->flash_id = FLASH_MAN_EXCEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr2[CFG_FLASH_READ1];		/* device ID	*/
+
+	switch (value) {
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;				/* => 0.5 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV040B:
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000;		/* => 0.5 MB	*/
+		break;
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;				/* => 1 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;				/* => 2 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+		info->flash_id += FLASH_AMDL322B;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+		info->flash_id += FLASH_AMDL323T;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x00400000;
+		break;				/* => 4 MB	*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF020:
+		info->flash_id += FLASH_SST020;
+		info->sector_count = 64;
+		info->size = 0x00040000;
+		break;				/* => 256 kB	*/
+
+	case (CFG_FLASH_WORD_SIZE)SST_ID_xF040:
+		info->flash_id += FLASH_SST040;
+		info->sector_count = 128;
+		info->size = 0x00080000;
+		break;				/* => 512 kB	*/
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00001000);
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000);
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
+		/* set sector offsets for bottom boot block type	*/
+		for (i=0; i<8; ++i) {		/*  8 x 8k boot sectors	*/
+			info->start[i] = base;
+			base += 8 << 10;
+		}
+		while (i < info->sector_count) {	/* 64k regular sectors	*/
+			info->start[i] = base;
+			base += 64 << 10;
+			++i;
+		}
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
+		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
+		/* set sector offsets for top boot block type		*/
+		base += info->size;
+		i = info->sector_count;
+		for (n=0; n<8; ++n) {		/*  8 x 8k boot sectors	*/
+			base -= 8 << 10;
+			--i;
+			info->start[i] = base;
+		}
+		while (i > 0) {			/* 64k regular sectors	*/
+			base -= 64 << 10;
+			--i;
+			info->start[i] = base;
+		}
+	} else {
+		if (info->flash_id & FLASH_BTYPE) {
+			/* set sector offsets for bottom boot block type	*/
+			info->start[0] = base + 0x00000000;
+			info->start[1] = base + 0x00004000;
+			info->start[2] = base + 0x00006000;
+			info->start[3] = base + 0x00008000;
+			for (i = 4; i < info->sector_count; i++) {
+				info->start[i] = base + (i * 0x00010000) - 0x00030000;
+			}
+		} else {
+			/* set sector offsets for top boot block type		*/
+			i = info->sector_count - 1;
+			info->start[i--] = base + info->size - 0x00004000;
+			info->start[i--] = base + info->size - 0x00006000;
+			info->start[i--] = base + info->size - 0x00008000;
+			for (; i >= 0; i--) {
+				info->start[i] = base + i * 0x00010000;
+			}
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
+			info->protect[i] = 0;
+		else
+			info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect)
+		if (info->protect[sect])
+			prot++;
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+
+				/* re-enable interrupts if necessary */
+				if (flag) {
+					enable_interrupts();
+					flag = 0;
+				}
+
+				/* data polling for D7 */
+				start = get_timer (0);
+				while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+				       (CFG_FLASH_WORD_SIZE)0x00800080) {
+					if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+						return (1);
+				}
+			} else {
+				if (sect == s_first) {
+					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+				}
+				addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+			}
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i)
+			data = (data << 8) | *src++;
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0)
+		return (0);
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp)
+		data = (data << 8) | (*(uchar *)cp);
+
+	return (write_word(info, wp, data));
+}
+
+/*
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word(flash_info_t *info, ulong dest, ulong data)
+{
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	ulong start;
+	int flag;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) {
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer (0);
+		while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+		       (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
+			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}

board/pcs440ep/init.S

@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+
+/* General */
+#define TLB_VALID   0x00000200
+
+/* Supported page sizes */
+
+#define SZ_1K	    0x00000000
+#define SZ_4K	    0x00000010
+#define SZ_16K	    0x00000020
+#define SZ_64K	    0x00000030
+#define SZ_256K	    0x00000040
+#define SZ_1M	    0x00000050
+#define SZ_8M       0x00000060
+#define SZ_16M	    0x00000070
+#define SZ_256M	    0x00000090
+
+/* Storage attributes */
+#define SA_W	    0x00000800	    /* Write-through */
+#define SA_I	    0x00000400	    /* Caching inhibited */
+#define SA_M	    0x00000200	    /* Memory coherence */
+#define SA_G	    0x00000100	    /* Guarded */
+#define SA_E	    0x00000080	    /* Endian */
+
+/* Access control */
+#define AC_X	    0x00000024	    /* Execute */
+#define AC_W	    0x00000012	    /* Write */
+#define AC_R	    0x00000009	    /* Read */
+
+/* Some handy macros */
+
+#define EPN(e)		((e) & 0xfffffc00)
+#define TLB0(epn,sz)	( (EPN((epn)) | (sz) | TLB_VALID ) )
+#define TLB1(rpn,erpn)	( ((rpn)&0xfffffc00) | (erpn) )
+#define TLB2(a)		( (a)&0x00000fbf )
+
+#define tlbtab_start\
+	mflr    r1  ;\
+	bl 0f	    ;
+
+#define tlbtab_end\
+	.long 0, 0, 0	;   \
+0:	mflr    r0	;   \
+	mtlr    r1	;   \
+	blr		;
+
+#define tlbentry(epn,sz,rpn,erpn,attr)\
+	.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+
+    .section .bootpg,"ax"
+    .globl tlbtab
+
+tlbtab:
+    tlbtab_start
+
+    /*
+     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+     * speed up boot process. It is patched after relocation to enable SA_I
+     */
+    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+
+    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+
+    /* PCI */
+    tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+
+    /* USB 2.0 Device */
+    tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+
+    tlbtab_end

board/pcs440ep/pcs440ep.c

@@ -0,0 +1,379 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+static void set_leds(int val)
+{
+	unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
+				 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
+	out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27));
+}
+
+int board_early_init_f(void)
+{
+	register uint reg;
+
+	set_leds(0);			/* display boot info counter */
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(ebccfga, xbcfg);
+	reg = mfdcr(ebccfgd);
+	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
+
+	/*--------------------------------------------------------------------
+	 * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
+	 * via define from board config file.
+	 *-------------------------------------------------------------------*/
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000001);	/* UIC1 crit is critical */
+	mtdcr(uic0pr, 0xfffffe1f);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x01c00000);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	/*--------------------------------------------------------------------
+	 * Setup other serial configuration
+	 *-------------------------------------------------------------------*/
+	mfsdr(sdr_pci0, reg);
+	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
+	mtsdr(sdr_pfc0, 0x00000100);	/* Pin function: enable GPIO49-63 */
+	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins, select IRQ5 */
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	uint pbcr;
+	int size_val = 0;
+
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	switch (gd->bd->bi_flashsize) {
+	case 1 << 20:
+		size_val = 0;
+		break;
+	case 2 << 20:
+		size_val = 1;
+		break;
+	case 4 << 20:
+		size_val = 2;
+		break;
+	case 8 << 20:
+		size_val = 3;
+		break;
+	case 16 << 20:
+		size_val = 4;
+		break;
+	case 32 << 20:
+		size_val = 5;
+		break;
+	case 64 << 20:
+		size_val = 6;
+		break;
+	case 128 << 20:
+		size_val = 7;
+		break;
+	}
+	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
+	mtdcr(ebccfga, pb0cr);
+	mtdcr(ebccfgd, pbcr);
+
+	/* adjust flash start and offset */
+	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+	gd->bd->bi_flashoffset = 0;
+
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[1]);
+
+	/* Env protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    CFG_ENV_ADDR_REDUND,
+			    CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+			    &flash_info[1]);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	printf("Board: PCS440EP");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+
+	set_leds(1);			/* display boot info counter */
+	dram_size = spd_sdram();
+	set_leds(2);			/* display boot info counter */
+
+	return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int testdram(void)
+{
+	unsigned long *mem = (unsigned long *)0;
+	const unsigned long kend = (1024 / sizeof(unsigned long));
+	unsigned long k, n;
+
+	mtmsr(0);
+
+	for (k = 0; k < CFG_KBYTES_SDRAM;
+	     ++k, mem += (1024 / sizeof(unsigned long))) {
+		if ((k & 1023) == 0) {
+			printf("%3d MB\r", k / 1024);
+		}
+
+		memset(mem, 0xaaaaaaaa, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0xaaaaaaaa) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+
+		memset(mem, 0x55555555, 1024);
+		for (n = 0; n < kend; ++n) {
+			if (mem[n] != 0x55555555) {
+				printf("SDRAM test fails at: %08x\n",
+				       (uint) & mem[n]);
+				return 1;
+			}
+		}
+	}
+	printf("SDRAM test passes\n");
+	return 0;
+}
+#endif
+
+/*************************************************************************
+ *  pci_pre_init
+ *
+ *  This routine is called just prior to registering the hose and gives
+ *  the board the opportunity to check things. Returning a value of zero
+ *  indicates that things are bad & PCI initialization should be aborted.
+ *
+ *	Different boards may wish to customize the pci controller structure
+ *	(add regions, override default access routines, etc) or perform
+ *	certain pre-initialization actions.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+int pci_pre_init(struct pci_controller *hose)
+{
+	unsigned long addr;
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB3 devices to 0.
+	  | Set PLB3 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp1, addr);
+	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb3_acr);
+	mtdcr(plb3_acr, addr | 0x80000000);
+
+	/*-------------------------------------------------------------------------+
+	  | Set priority for all PLB4 devices to 0.
+	  +-------------------------------------------------------------------------*/
+	mfsdr(sdr_amp0, addr);
+	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
+	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
+	mtdcr(plb4_acr, addr);
+
+	/*-------------------------------------------------------------------------+
+	  | Set Nebula PLB4 arbiter to fair mode.
+	  +-------------------------------------------------------------------------*/
+	/* Segment0 */
+	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
+	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
+	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
+	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
+	mtdcr(plb0_acr, addr);
+
+	/* Segment1 */
+	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
+	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
+	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
+	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
+	mtdcr(plb1_acr, addr);
+
+	return 1;
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+/*************************************************************************
+ *  pci_target_init
+ *
+ *	The bootstrap configuration provides default settings for the pci
+ *	inbound map (PIM). But the bootstrap config choices are limited and
+ *	may not be sufficient for a given board.
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+void pci_target_init(struct pci_controller *hose)
+{
+	/*--------------------------------------------------------------------------+
+	 * Set up Direct MMIO registers
+	 *--------------------------------------------------------------------------*/
+	/*--------------------------------------------------------------------------+
+	  | PowerPC440 EP PCI Master configuration.
+	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
+	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
+	  |   Use byte reversed out routines to handle endianess.
+	  | Make this region non-prefetchable.
+	  +--------------------------------------------------------------------------*/
+	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
+	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
+	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
+
+	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
+	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
+	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */
+
+	/*--------------------------------------------------------------------------+
+	 * Set up Configuration registers
+	 *--------------------------------------------------------------------------*/
+
+	/* Program the board's subsystem id/vendor id */
+	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
+			      CFG_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+
+	/* Configure command register as bus master */
+	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
+
+	/* 240nS PCI clock */
+	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+
+	/* No error reporting */
+	pci_write_config_word(0, PCI_ERREN, 0);
+
+	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+
+/*************************************************************************
+ *  pci_master_init
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+void pci_master_init(struct pci_controller *hose)
+{
+	unsigned short temp_short;
+
+	/*--------------------------------------------------------------------------+
+	  | Write the PowerPC440 EP PCI Configuration regs.
+	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
+	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
+	  +--------------------------------------------------------------------------*/
+	pci_read_config_word(0, PCI_COMMAND, &temp_short);
+	pci_write_config_word(0, PCI_COMMAND,
+			      temp_short | PCI_COMMAND_MASTER |
+			      PCI_COMMAND_MEMORY);
+}
+#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+
+/*************************************************************************
+ *  is_pci_host
+ *
+ *	This routine is called to determine if a pci scan should be
+ *	performed. With various hardware environments (especially cPCI and
+ *	PPMC) it's insufficient to depend on the state of the arbiter enable
+ *	bit in the strap register, or generic host/adapter assumptions.
+ *
+ *	Rather than hard-code a bad assumption in the general 440 code, the
+ *	440 pci code requires the board to decide at runtime.
+ *
+ *	Return 0 for adapter mode, non-zero for host (monarch) mode.
+ *
+ *
+ ************************************************************************/
+#if defined(CONFIG_PCI)
+int is_pci_host(struct pci_controller *hose)
+{
+	/* PCS440EP is always configured as host. */
+	return (1);
+}
+#endif				/* defined(CONFIG_PCI) */
+
+/*************************************************************************
+ *  hw_watchdog_reset
+ *
+ *	This routine is called to reset (keep alive) the watchdog timer
+ *
+ ************************************************************************/
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+
+}
+#endif

board/pcs440ep/u-boot.lds

@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/ppc4xx/start.o	(.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/ppc4xx/start.o	(.text)
+    board/pcs440ep/init.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}

board/psyent/common/AMDLV065D.c

@@ -26,7 +26,7 @@
 #if defined(CONFIG_NIOS)
 #include <nios.h>
 #else
-#include <nios2.h>
+#include <asm/io.h>
 #endif
 
 #define SECTSZ		(64 * 1024)
@@ -56,9 +56,8 @@ unsigned long flash_init (void)
 void flash_print_info (flash_info_t * info)
 {
 	int i, k;
-	unsigned long size;
 	int erased;
-	volatile unsigned char *flash;
+	unsigned long *addr;
 
 	printf ("  Size: %ld KB in %d Sectors\n",
 		info->size >> 10, info->sector_count);
@@ -66,14 +65,10 @@ void flash_print_info (flash_info_t * info)
 	for (i = 0; i < info->sector_count; ++i) {
 
 		/* Check if whole sector is erased */
-		if (i != (info->sector_count - 1))
-			size = info->start[i + 1] - info->start[i];
-		else
-			size = info->start[0] + info->size - info->start[i];
 		erased = 1;
-		flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]);
-		for (k = 0; k < size; k++) {
-			if (*flash++ != 0xff) {
+		addr = (unsigned long *) info->start[i];
+		for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
+			if ( readl(addr++) != (unsigned long)-1) {
 				erased = 0;
 				break;
 			}
@@ -83,7 +78,7 @@ void flash_print_info (flash_info_t * info)
 		if ((i % 5) == 0)
 			printf ("\n   ");
 		printf (" %08lX%s%s",
-			CACHE_NO_BYPASS(info->start[i]),
+			info->start[i],
 			erased ? " E" : "  ",
 			info->protect[i] ? "RO " : "   ");
 	}
@@ -95,9 +90,8 @@ void flash_print_info (flash_info_t * info)
 
 int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)
-		CACHE_BYPASS(info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	unsigned char *addr = (unsigned char *) info->start[0];
+	unsigned char *addr2;
 	int prot, sect;
 	ulong start;
 
@@ -127,19 +121,18 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	 */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *)
-				CACHE_BYPASS((info->start[sect]));
-			*addr = 0xaa;
-			*addr = 0x55;
-			*addr = 0x80;
-			*addr = 0xaa;
-			*addr = 0x55;
-			*addr2 = 0x30;
+			addr2 = (unsigned char *) info->start[sect];
+			writeb (addr, 0xaa);
+			writeb (addr,  0x55);
+			writeb (addr,  0x80);
+			writeb (addr,  0xaa);
+			writeb (addr,  0x55);
+			writeb (addr2, 0x30);
 			/* Now just wait for 0xff & provide some user
 			 * feedback while we wait.
 			 */
 			start = get_timer (0);
-			while (*addr2 != 0xff) {
+			while ( readb (addr2) != 0xff) {
 				udelay (1000 * 1000);
 				putc ('.');
 				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
@@ -163,27 +156,27 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 
-	vu_char *cmd = (vu_char *) CACHE_BYPASS(info->start[0]);
-	vu_char *dst = (vu_char *) CACHE_BYPASS(addr);
+	vu_char *cmd = (vu_char *) info->start[0];
+	vu_char *dst = (vu_char *) addr;
 	unsigned char b;
 	ulong start;
 
 	while (cnt) {
 		/* Check for sufficient erase */
 		b = *src;
-		if ((*dst & b) != b) {
-			printf ("%02x : %02x\n", *dst, b);
+		if ((readb (dst) & b) != b) {
+			printf ("%02x : %02x\n", readb (dst), b);
 			return (2);
 		}
 
-		*cmd = 0xaa;
-		*cmd = 0x55;
-		*cmd = 0xa0;
-		*dst = b;
+		writeb (cmd,  0xaa);
+		writeb (cmd,  0x55);
+		writeb (cmd,  0xa0);
+		writeb (dst, b);
 
 		/* Verify write */
 		start = get_timer (0);
-		while (*dst != b) {
+		while (readb (dst) != b) {
 			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
 				return 1;
 			}

board/psyent/pk1c20/config.mk

@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-TEXT_BASE = 0x018e0000
+TEXT_BASE = 0x01fc0000
 
 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
 PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include

board/psyent/pk1c20/led.c

@@ -22,7 +22,7 @@
  */
 
 #include <common.h>
-#include <nios2.h>
+#include <asm/io.h>
 #include <nios2-io.h>
 #include <status_led.h>
 
@@ -33,30 +33,30 @@ static led_id_t val = 0;
 
 void __led_init (led_id_t mask, int state)
 {
-	nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
 
 	if (state == STATUS_LED_ON)
 		val &= ~mask;
 	else
 		val |= mask;
-	pio->data = val;
+	writel (&pio->data, val);
 }
 
 void __led_set (led_id_t mask, int state)
 {
-	nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
 
 	if (state == STATUS_LED_ON)
 		val &= ~mask;
 	else
 		val |= mask;
-	pio->data = val;
+	writel (&pio->data, val);
 }
 
 void __led_toggle (led_id_t mask)
 {
-	nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
 
 	val ^= mask;
-	pio->data = val;
+	writel (&pio->data, val);
 }

config.mk

@@ -112,7 +112,7 @@ OBJDUMP = $(CROSS_COMPILE)objdump
 RANLIB	= $(CROSS_COMPILE)RANLIB
 
 RELFLAGS= $(PLATFORM_RELFLAGS)
-DBGFLAGS= -g #-DDEBUG
+DBGFLAGS= -g # -DDEBUG
 OPTFLAGS= -Os #-fomit-frame-pointer
 ifndef LDSCRIPT
 #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug

cpu/ixp/npe/include/IxEthDB.h

@@ -799,10 +799,10 @@ IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBR
  * @verbatim
     IxEthDBPortMap portMap;
     
-    /* clear all ports from port map */
+    // clear all ports from port map
     memset(portMap, 0, sizeof (portMap)); 
     
-    /* include portID in port map  */
+    // include portID in port map 
     portMap[portID / 8] = 1 << (portID % 8);
    @endverbatim
  *

cpu/mcf52x2/cpu.c

@@ -2,6 +2,10 @@
  * (C) Copyright 2003
  * Josef Baumgartner <josef.baumgartner@telex.de>
  *
+ * MCF5282 additionals
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -36,7 +40,8 @@
 #endif
 
 #ifdef	CONFIG_M5282
-
+#include <asm/m5282.h>
+#include <asm/immap_5282.h>
 #endif
 
 #ifdef	CONFIG_M5249
@@ -116,7 +121,6 @@ int checkcpu(void) {
 	return 0;
 };
 
-
 #if defined(CONFIG_WATCHDOG)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset (void)
@@ -158,11 +162,25 @@ int watchdog_init (void)
 #ifdef	CONFIG_M5282
 int checkcpu (void)
 {
-	puts ("CPU:   Freescale Coldfire MCF5282\n");
+	unsigned char resetsource = MCFRESET_RSR;
+
+	printf ("CPU:   Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
+		MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
+	printf ("Reset:%s%s%s%s%s%s%s\n",
+		(resetsource & MCFRESET_RSR_LOL)  ? " Loss of Lock"	: "",
+		(resetsource & MCFRESET_RSR_LOC)  ? " Loss of Clock"	: "",
+		(resetsource & MCFRESET_RSR_EXT)  ? " External"		: "",
+		(resetsource & MCFRESET_RSR_POR)  ? " Power On"		: "",
+		(resetsource & MCFRESET_RSR_WDR)  ? " Watchdog"		: "",
+		(resetsource & MCFRESET_RSR_SOFT) ? " Software"		: "",
+		(resetsource & MCFRESET_RSR_LVD)  ? " Low Voltage"	: ""
+	);
 	return 0;
 }
 
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
+int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+	MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
 	return 0;
 };
 #endif

cpu/mcf52x2/cpu_init.c

@@ -2,6 +2,10 @@
  * (C) Copyright 2003
  * Josef Baumgartner <josef.baumgartner@telex.de>
  *
+ * MCF5282 additionals
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -172,7 +176,180 @@ int cpu_init_r	(void)
  */
 void cpu_init_f (void)
 {
+#ifndef CONFIG_WATCHDOG
+	/* disable watchdog if we aren't using it */
+	MCFWTM_WCR = 0;
+#endif
 
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+	/* Set speed /PLL */
+	MCFCLOCK_SYNCR =  MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
+
+	/* Set up the GPIO ports */
+#ifdef CFG_PEPAR
+	MCFGPIO_PEPAR = CFG_PEPAR;
+#endif
+#ifdef	CFG_PFPAR
+	MCFGPIO_PFPAR = CFG_PFPAR;
+#endif
+#ifdef CFG_PJPAR
+	MCFGPIO_PJPAR = CFG_PJPAR;
+#endif
+#ifdef CFG_PSDPAR
+	MCFGPIO_PSDPAR = CFG_PSDPAR;
+#endif
+#ifdef CFG_PASPAR
+	MCFGPIO_PASPAR = CFG_PASPAR;
+#endif
+#ifdef CFG_PEHLPAR
+	MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+#endif
+#ifdef CFG_PQSPAR
+	MCFGPIO_PQSPAR = CFG_PQSPAR;
+#endif
+#ifdef CFG_PTCPAR
+	MCFGPIO_PTCPAR = CFG_PTCPAR;
+#endif
+#ifdef CFG_PTDPAR
+	MCFGPIO_PTDPAR = CFG_PTDPAR;
+#endif
+#ifdef CFG_PUAPAR
+	MCFGPIO_PUAPAR = CFG_PUAPAR;
+#endif
+
+#ifdef CFG_DDRUA
+	MCFGPIO_DDRUA = CFG_DDRUA;
+#endif
+
+	/* This is probably a bad place to setup chip selects, but everyone
+	   else is doing it! */
+
+#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
+    defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
+	defined(CFG_CS0_WS)
+
+	MCFCSM_CSAR0 =	(CFG_CS0_BASE >> 16) & 0xFFFF;
+
+	#if (CFG_CS0_WIDTH == 8)
+		#define	 CFG_CS0_PS  MCFCSM_CSCR_PS_8
+	#elif (CFG_CS0_WIDTH == 16)
+		#define	 CFG_CS0_PS  MCFCSM_CSCR_PS_16
+	#elif (CFG_CS0_WIDTH == 32)
+		#define	 CFG_CS0_PS  MCFCSM_CSCR_PS_32
+	#else
+		#error	"CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
+	#endif
+	MCFCSM_CSCR0 =	MCFCSM_CSCR_WS(CFG_CS0_WS)
+			|CFG_CS0_PS
+			|MCFCSM_CSCR_AA;
+
+	#if (CFG_CS0_RO != 0)
+		MCFCSM_CSMR0 =	MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
+				|MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
+ 	#else
+		MCFCSM_CSMR0 =	MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
+	#endif
+#else
+	#waring "Chip Select 0 are not initialized/used"
+#endif
+
+#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
+    defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
+	defined(CFG_CS1_WS)
+
+	MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
+
+	#if (CFG_CS1_WIDTH == 8)
+		#define	 CFG_CS1_PS  MCFCSM_CSCR_PS_8
+	#elif (CFG_CS1_WIDTH == 16)
+		#define	 CFG_CS1_PS  MCFCSM_CSCR_PS_16
+	#elif (CFG_CS1_WIDTH == 32)
+		#define	 CFG_CS1_PS  MCFCSM_CSCR_PS_32
+	#else
+		#error	"CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
+	#endif
+	MCFCSM_CSCR1 =	MCFCSM_CSCR_WS(CFG_CS1_WS)
+			|CFG_CS1_PS
+			|MCFCSM_CSCR_AA;
+
+	#if (CFG_CS1_RO != 0)
+		MCFCSM_CSMR1 =	MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
+				|MCFCSM_CSMR_WP
+				|MCFCSM_CSMR_V;
+ 	#else
+		MCFCSM_CSMR1 =	MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
+				|MCFCSM_CSMR_V;
+	#endif
+#else
+	#warning "Chip Select 1 are not initialized/used"
+#endif
+
+#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
+    defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
+	defined(CFG_CS2_WS)
+
+	MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
+
+	#if (CFG_CS2_WIDTH == 8)
+		#define	 CFG_CS2_PS  MCFCSM_CSCR_PS_8
+	#elif (CFG_CS2_WIDTH == 16)
+		#define	 CFG_CS2_PS  MCFCSM_CSCR_PS_16
+	#elif (CFG_CS2_WIDTH == 32)
+		#define	 CFG_CS2_PS  MCFCSM_CSCR_PS_32
+	#else
+		#error	"CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
+	#endif
+	MCFCSM_CSCR2 =	MCFCSM_CSCR_WS(CFG_CS2_WS)
+			|CFG_CS2_PS
+			|MCFCSM_CSCR_AA;
+
+	#if (CFG_CS2_RO != 0)
+		MCFCSM_CSMR2 =	MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
+				|MCFCSM_CSMR_WP
+				|MCFCSM_CSMR_V;
+ 	#else
+		MCFCSM_CSMR2 =	MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
+				|MCFCSM_CSMR_V;
+	#endif
+#else
+	#warning "Chip Select 2 are not initialized/used"
+#endif
+
+#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
+    defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
+	defined(CFG_CS3_WS)
+
+	MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
+
+	#if (CFG_CS3_WIDTH == 8)
+		#define	 CFG_CS3_PS  MCFCSM_CSCR_PS_8
+	#elif (CFG_CS3_WIDTH == 16)
+		#define	 CFG_CS3_PS  MCFCSM_CSCR_PS_16
+	#elif (CFG_CS3_WIDTH == 32)
+		#define	 CFG_CS3_PS  MCFCSM_CSCR_PS_32
+	#else
+		#error	"CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
+	#endif
+	MCFCSM_CSCR3 =	MCFCSM_CSCR_WS(CFG_CS3_WS)
+			|CFG_CS3_PS
+			|MCFCSM_CSCR_AA;
+
+	#if (CFG_CS3_RO != 0)
+		MCFCSM_CSMR3 =	MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
+				|MCFCSM_CSMR_WP
+				|MCFCSM_CSMR_V;
+ 	#else
+		MCFCSM_CSMR3 =	MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
+				|MCFCSM_CSMR_V;
+	#endif
+#else
+	#warning "Chip Select 3 are not initialized/used"
+#endif
+
+#endif /* CONFIG_MONITOR_IS_IN_RAM */
+
+	/* defer enabling cache until boot (see do_go) */
+	/* icache_enable(); */
 }
 
 /*

cpu/mcf52x2/fec.c

@@ -205,7 +205,9 @@ int eth_rx (void)
 
 int eth_init (bd_t * bd)
 {
-
+#ifndef CFG_ENET_BD_BASE
+	DECLARE_GLOBAL_DATA_PTR;
+#endif
 	int i;
 	volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
 
@@ -258,6 +260,10 @@ int eth_init (bd_t * bd)
 #else
 	/* Clear multicast address hash table
 	 */
+#ifdef	CONFIG_M5282
+	fecp->fec_ihash_table_high = 0;
+	fecp->fec_ihash_table_low = 0;
+#else
 	fecp->fec_hash_table_high = 0;
 	fecp->fec_hash_table_low = 0;
 #endif
@@ -273,7 +279,16 @@ int eth_init (bd_t * bd)
 	txIdx = 0;
 
 	if (!rtx) {
+#ifdef CFG_ENET_BD_BASE
 		rtx = (RTXBD *) CFG_ENET_BD_BASE;
+#else
+		rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off -
+				 (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t)
+				  +0xFF)
+				  & ~0xFF)
+				);
+		debug("set ENET_DB_BASE to %lX\n",(long) rtx);
+#endif
 	}
 
 	/*
@@ -307,18 +322,18 @@ int eth_init (bd_t * bd)
 
 	/* Enable MII mode
 	 */
-#if 0				/* Full duplex mode */
+
+#if 0	/* Full duplex mode */
 	fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
 	fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
-#else  /* Half duplex mode */
-	fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
-#ifdef	CONFIG_M5271
-	fecp->fec_r_cntrl |= (PKT_MAXBUF_SIZE << 16); /* set max frame length */
-#endif
+#else	/* Half duplex mode */
+	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */
+	fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
 	fecp->fec_x_cntrl = 0;
 #endif
 	/* Set MII speed */
-	fecp->fec_mii_speed = 0x0e;
+	fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10;
+	fecp->fec_mii_speed *= 2;
 
 	/* Configure port B for MII.
 	 */
@@ -422,7 +437,7 @@ static void mii_discover_phy (void)
 			 */
 			udelay (10000);	/* wait 10ms */
 		}
-		for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+		for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) {
 			phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
 #ifdef ET_DEBUG
 			printf ("PHY type 0x%x pass %d type ", phytype, pass);

cpu/mcf52x2/serial.c

@@ -55,45 +55,75 @@ void rs_serial_setbaudrate(int port,int baudrate)
 {
 #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5271)
 	volatile unsigned char	*uartp;
-#ifndef CONFIG_M5271
+# ifndef CONFIG_M5271
 	double fraction;
-#endif
+# endif
 	double clock;
 
-	if (port == 0)
-	  uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
-	else
-	  uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
-
-	clock = DoubleClock(baudrate);      /* Set baud above */
-
-	uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff);  /* set msb baud */
-	uartp[MCFUART_UBG2] = ((int)clock & 0xff);  /* set lsb baud */
-
-#ifndef CONFIG_M5271
-	fraction = ((clock - (int)clock) * 16.0) + 0.5;
-	uartp[MCFUART_UFPD] = ((int)fraction & 0xf);  /* set baud fraction adjust */
-#endif
-#endif
-};
-
-void rs_serial_init(int port,int baudrate)
-{
-	volatile unsigned char	*uartp;
-
-	/*
-	 *	Reset UART, get it into known state...
-	 */
 	if (port == 0)
 		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
 	else
 		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
 
-	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX;  /* reset TX */
-	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX;  /* reset RX */
+	clock = DoubleClock(baudrate);	/* Set baud above */
 
-	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR;  /* reset MR pointer */
-	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR;  /* reset Error pointer */
+	uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff);	/* set msb baud */
+	uartp[MCFUART_UBG2] = ((int)clock & 0xff);		/* set lsb baud */
+
+# ifndef CONFIG_M5271
+	fraction = ((clock - (int)clock) * 16.0) + 0.5;
+	uartp[MCFUART_UFPD] = ((int)fraction & 0xf);	/* set baud fraction adjust */
+# endif
+#endif
+
+#if  defined(CONFIG_M5282)
+	volatile unsigned char	*uartp;
+	long clock;
+
+	switch (port) {
+	case 1:
+		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
+		break;
+	case 2:
+		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
+		break;
+	default:
+		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
+	}
+
+	clock = (long) CFG_CLK / ((long) 32 * baudrate);	/* Set baud above */
+
+	uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff);	/* set msb baud */
+	uartp[MCFUART_UBG2] = ((int) clock & 0xff);		/* set lsb baud */
+
+#endif
+};
+
+void rs_serial_init (int port, int baudrate)
+{
+	volatile unsigned char *uartp;
+
+	/*
+	 *      Reset UART, get it into known state...
+	 */
+	switch (port) {
+	case 1:
+		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
+		break;
+#if  defined(CONFIG_M5282)
+	case 2:
+		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
+		break;
+#endif
+	default:
+		uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
+	}
+
+	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX;	/* reset TX */
+	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX;	/* reset RX */
+
+	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETMRPTR;	/* reset MR pointer */
+	uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETERR;	/* reset Error pointer */
 
 	/*
 	 * Set port for CONSOLE_BAUD_RATE, 8 data bits, 1 stop bit, no parity.
@@ -107,7 +137,7 @@ void rs_serial_init(int port,int baudrate)
 	/* Set clock Select Register: Tx/Rx clock is timer */
 	uartp[MCFUART_UCSR] = MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER;
 
-	rs_serial_setbaudrate(port,baudrate);
+	rs_serial_setbaudrate (port, baudrate);
 
 	/* Enable Tx/Rx */
 	uartp[MCFUART_UCR] = MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE;
@@ -169,9 +199,8 @@ void serial_putc(const char c) {
 }
 
 void serial_puts (const char *s) {
-	while (*s) {
+	while (*s)
 		serial_putc(*s++);
-	}
 }
 
 int serial_getc(void) {

cpu/mcf52x2/start.S

@@ -55,11 +55,15 @@
  */
 _vectors:
 
-#ifndef	CONFIG_R5200
-.long	0x00000000, _START
+.long	0x00000000		/* Flash offset is 0 until we setup CS0 */
+#if defined(CONFIG_R5200)
+.long	0x400
+#elif defined(CONFIG_M5282)
+.long	_start - TEXT_BASE
 #else
-.long	0x00000000, 0x400	/* Flash offset is 0 until we setup CS0 */
+.long	_START
 #endif
+
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
@@ -100,20 +104,23 @@ _vectors:
 
 	.text
 
+
+#if defined(CFG_INT_FLASH_BASE) && \
+    (defined(CONFIG_M5282) || defined(CONFIG_M5281))
+	#if (TEXT_BASE == CFG_INT_FLASH_BASE)
+		.long	0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
+		.long	0xFFFFFFFF /* all sectors protected */
+		.long	0x00000000 /* supervisor/User restriction */
+		.long	0x00000000 /* programm/data space restriction */
+		.long	0x00000000 /* Flash security */
+	#endif
+#endif
 	.globl	_start
 _start:
 	nop
 	nop
 	move.w #0x2700,%sr
 
-	/* if we come from a pre-loader we have no exception table and
-	 * therefore no VBR to set
-	 */
-#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-	move.l	#CFG_FLASH_BASE, %d0
-	movec	%d0, %VBR
-#endif
-
 #if defined(CONFIG_M5272) || defined(CONFIG_M5249)
 	move.l	#(CFG_MBAR + 1), %d0		/* set MBAR address + valid flag */
 	move.c	%d0, %MBAR
@@ -128,20 +135,48 @@ _start:
 	movec	%d0, %RAMBAR0
 #endif /* #if defined(CONFIG_M5272) || defined(CONFIG_M5249) */
 
-#if	defined(CONFIG_M5282) || defined(CONFIG_M5271)
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
 	/* Initialize IPSBAR */
 	move.l	#(CFG_MBAR + 1), %d0		/* set IPSBAR address + valid flag */
 	move.l	%d0, 0x40000000
 
-#ifdef	CONFIG_M5282
-	/* Initialize FLASHBAR: locate internal Flash and validate it */
-	move.l	#(CFG_INT_FLASH_BASE + 0x21), %d0
-	movec	%d0, %RAMBAR0
-#endif
-
 	/* Initialize RAMBAR1: locate SRAM and validate it */
 	move.l	#(CFG_INIT_RAM_ADDR + 0x21), %d0
 	movec	%d0, %RAMBAR1
+
+#if (TEXT_BASE == CFG_INT_FLASH_BASE)
+	/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
+
+	move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
+	move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
+	move.l #(CFG_INIT_RAM_ADDR), %a2
+_copy_flash:
+	move.l (%a0)+, (%a2)+
+	cmp.l %a0, %a1
+	bgt.s _copy_flash
+	jmp CFG_INIT_RAM_ADDR
+
+_flashbar_setup:
+	/* Initialize FLASHBAR: locate internal Flash and validate it */
+	move.l	#(CFG_INT_FLASH_BASE + 0x21), %d0
+	movec	%d0, %RAMBAR0
+	jmp _after_flashbar_copy.L	/* Force jump to absolute address */
+_flashbar_setup_end:
+	nop
+_after_flashbar_copy:
+#else
+	/* Setup code to initialize FLASHBAR, if start from external Memory */
+	move.l	#(CFG_INT_FLASH_BASE + 0x21), %d0
+	movec	%d0, %RAMBAR0
+#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
+
+#endif
+	/* if we come from a pre-loader we have no exception table and
+	 * therefore no VBR to set
+	 */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+	move.l	#CFG_FLASH_BASE, %d0
+	movec	%d0, %VBR
 #endif
 
 #ifdef	CONFIG_R5200
@@ -218,7 +253,6 @@ relocate_code:
 	move.l #CFG_MONITOR_BASE, %a1
 	move.l #__init_end, %a2
 	move.l %a0, %a3
-
 	/* copy the code to RAM */
 1:
 	move.l (%a1)+, (%a3)+
@@ -229,14 +263,14 @@ relocate_code:
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
-	move.l	%a0, %a1
+ 	move.l	%a0, %a1
 	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
 	jmp	(%a1)
 
 in_ram:
 
 clear_bss:
-	/*
+ 	/*
 	 * Now clear BSS segment
 	 */
 	move.l	%a0, %a1
@@ -266,6 +300,23 @@ clear_bss:
 	cmp.l	%a2, %a1
 	bne	7b
 
+#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
+	/* patch the 3 accesspoints to 3 ichache_state */
+	/* quick and dirty */
+
+	move.l	%a0,%d1
+	add.l	#(icache_state - CFG_MONITOR_BASE),%d1
+	move.l	%a0,%a1
+	add.l	#(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
+	move.l  %d1,(%a1)
+	move.l	%a0,%a1
+	add.l	#(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
+	move.l  %d1,(%a1)
+	move.l	%a0,%a1
+	add.l	#(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
+	move.l  %d1,(%a1)
+#endif
+
 	/* calculate relative jump to board_init_r in ram */
 	move.l %a0, %a1
 	add.l #(board_init_r - CFG_MONITOR_BASE), %a1
@@ -273,6 +324,10 @@ clear_bss:
 	/* set parameters for board_init_r */
 	move.l %a0,-(%sp)		/* dest_addr */
 	move.l %d0,-(%sp)		/* gd */
+	#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
+	    defined(CFG_HALT_BEFOR_RAM_JUMP)
+ 		halt
+	#endif
 	jsr	(%a1)
 
 /*------------------------------------------------------------------------------*/
@@ -327,6 +382,7 @@ icache_enable:
 	move.l	#0x80400100, %d0		/* Setup cache mask, data cache disabel*/
 	movec	%d0, %CACR			/* Enable cache */
 	moveq	#1, %d0
+icache_state_access_1:
 	move.l	%d0, icache_state
 	rts
 #endif
@@ -361,18 +417,19 @@ icache_disable:
 	movec	%d0, %ACR0			/* Enable cache */
 	movec	%d0, %ACR1			/* Enable cache */
 	moveq	#0, %d0
+icache_state_access_2:
 	move.l	%d0, icache_state
 	rts
 
 	.globl	icache_status
 icache_status:
+icache_state_access_3:
 	move.l	icache_state, %d0
 	rts
 
 	.data
 icache_state:
-	.long	1
-
+	.long	0	/* cache is diabled on inirialization */
 
 /*------------------------------------------------------------------------------*/
 

cpu/nios2/epcs.c

@@ -25,7 +25,7 @@
 
 #if defined(CFG_NIOS_EPCSBASE)
 #include <command.h>
-#include <nios2.h>
+#include <asm/io.h>
 #include <nios2-io.h>
 #include <nios2-epcs.h>
 
@@ -72,8 +72,7 @@
  */
 #define EPCS_TIMEOUT		100	/* 100 msec timeout */
 
-static nios_spi_t *epcs =
-	(nios_spi_t *)CACHE_BYPASS(CFG_NIOS_EPCSBASE);
+static nios_spi_t *epcs = (nios_spi_t *)CFG_NIOS_EPCSBASE;
 
 /***********************************************************************
  * Device access
@@ -81,16 +80,20 @@ static nios_spi_t *epcs =
 static int epcs_cs (int assert)
 {
 	ulong start;
+	unsigned tmp;
+
 
 	if (assert) {
-		epcs->control |= NIOS_SPI_SSO;
+		tmp = readl (&epcs->control);
+		writel (&epcs->control, tmp | NIOS_SPI_SSO);
 	} else {
 		/* Let all bits shift out */
 		start = get_timer (0);
-		while ((epcs->status & NIOS_SPI_TMT) == 0)
+		while ((readl (&epcs->status) & NIOS_SPI_TMT) == 0)
 			if (get_timer (start) > EPCS_TIMEOUT)
 				return (-1);
-		epcs->control &= ~NIOS_SPI_SSO;
+		tmp = readl (&epcs->control);
+		writel (&epcs->control, tmp & ~NIOS_SPI_SSO);
 	}
 	return (0);
 }
@@ -100,10 +103,10 @@ static int epcs_tx (unsigned char c)
 	ulong start;
 
 	start = get_timer (0);
-	while ((epcs->status & NIOS_SPI_TRDY) == 0)
+	while ((readl (&epcs->status) & NIOS_SPI_TRDY) == 0)
 		if (get_timer (start) > EPCS_TIMEOUT)
 			return (-1);
-	epcs->txdata = c;
+	writel (&epcs->txdata, c);
 	return (0);
 }
 
@@ -112,10 +115,10 @@ static int epcs_rx (void)
 	ulong start;
 
 	start = get_timer (0);
-	while ((epcs->status & NIOS_SPI_RRDY) == 0)
+	while ((readl (&epcs->status) & NIOS_SPI_RRDY) == 0)
 		if (get_timer (start) > EPCS_TIMEOUT)
 			return (-1);
-	return (epcs->rxdata);
+	return (readl (&epcs->rxdata));
 }
 
 static unsigned char bitrev[] = {
@@ -207,6 +210,21 @@ static struct epcs_devinfo_t devinfo[] = {
 	{ 0, 0, 0, 0, 0, 0 }
 };
 
+int epcs_reset (void)
+{
+	/* When booting from an epcs controller, the epcs bootrom
+	 * code may leave the slave select in an asserted state.
+	 * This causes two problems: (1) The initial epcs access
+	 * will fail -- not a big deal, and (2) a software reset
+	 * will cause the bootrom code to hang since it does not
+	 * ensure the select is negated prior to first access -- a
+	 * big deal. Here we just negate chip select and everything
+	 * gets better :-)
+	 */
+	epcs_cs (0); /* Negate chip select */
+	return (0);
+}
+
 epcs_devinfo_t *epcs_dev_find (void)
 {
 	unsigned char buf[4];

cpu/nios2/exceptions.S

@@ -30,6 +30,9 @@
 
 	.global _exception
 
+	.set noat
+	.set nobreak
+
 _exception:
 	/* SAVE ALL REGS -- this allows trap and unimplemented
 	 * instruction handlers to be coded conveniently in C

cpu/nios2/interrupts.c

@@ -27,6 +27,7 @@
 
 #include <nios2.h>
 #include <nios2-io.h>
+#include <asm/io.h>
 #include <asm/ptrace.h>
 #include <common.h>
 #include <command.h>
@@ -79,7 +80,7 @@ void tmr_isr (void *arg)
 	/* Interrupt is cleared by writing anything to the
 	 * status register.
 	 */
-	tmr->status = 0;
+	writel (&tmr->status, 0);
 	timestamp += CFG_NIOS_TMRMS;
 #ifdef CONFIG_STATUS_LED
 	status_led_tick(timestamp);
@@ -88,16 +89,17 @@ void tmr_isr (void *arg)
 
 static void tmr_init (void)
 {
-	nios_timer_t *tmr =(nios_timer_t *)CACHE_BYPASS(CFG_NIOS_TMRBASE);
+	nios_timer_t *tmr =(nios_timer_t *)CFG_NIOS_TMRBASE;
+
+	writel (&tmr->status, 0);
+	writel (&tmr->control, 0);
+	writel (&tmr->control, NIOS_TIMER_STOP);
 
-	tmr->control &= ~(NIOS_TIMER_START | NIOS_TIMER_ITO);
-	tmr->control |= NIOS_TIMER_STOP;
 #if defined(CFG_NIOS_TMRCNT)
-	tmr->periodl = CFG_NIOS_TMRCNT & 0xffff;
-	tmr->periodh = (CFG_NIOS_TMRCNT >> 16) & 0xffff;
+	writel (&tmr->periodl, CFG_NIOS_TMRCNT & 0xffff);
+	writel (&tmr->periodh, (CFG_NIOS_TMRCNT >> 16) & 0xffff);
 #endif
-	tmr->control |= ( NIOS_TIMER_ITO |
-			  NIOS_TIMER_CONT |
+	writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT |
 			  NIOS_TIMER_START );
 	irq_install_handler (CFG_NIOS_TMRIRQ, tmr_isr, (void *)tmr);
 }

cpu/nios2/serial.c

@@ -24,7 +24,7 @@
 
 #include <common.h>
 #include <watchdog.h>
-#include <nios2.h>
+#include <asm/io.h>
 #include <nios2-io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -34,8 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
  *-----------------------------------------------------------------*/
 #if defined(CONFIG_CONSOLE_JTAG)
 
-static nios_jtag_t *jtag =
-	(nios_jtag_t *)CACHE_BYPASS(CFG_NIOS_CONSOLE);
+static nios_jtag_t *jtag = (nios_jtag_t *)CFG_NIOS_CONSOLE;
 
 void serial_setbrg( void ){ return; }
 int serial_init( void ) { return(0);}
@@ -44,9 +43,9 @@ void serial_putc (char c)
 {
 	unsigned val;
 
-	while (NIOS_JTAG_WSPACE (jtag->control) == 0)
+	while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
 		WATCHDOG_RESET ();
-	jtag->data = (unsigned char)c;
+	writel (&jtag->data, (unsigned char)c);
 }
 
 void serial_puts (const char *s)
@@ -57,7 +56,7 @@ void serial_puts (const char *s)
 
 int serial_tstc (void)
 {
-	return (jtag->control & NIOS_JTAG_RRDY);
+	return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
 }
 
 int serial_getc (void)
@@ -67,7 +66,7 @@ int serial_getc (void)
 
 	while (1) {
 		WATCHDOG_RESET ();
-		val = jtag->data;
+		val = readl (&jtag->data);
 		if (val & NIOS_JTAG_RVALID)
 			break;
 	}
@@ -80,8 +79,7 @@ int serial_getc (void)
  *-----------------------------------------------------------------*/
 #else
 
-static nios_uart_t *uart = (nios_uart_t *)
-	CACHE_BYPASS(CFG_NIOS_CONSOLE);
+static nios_uart_t *uart = (nios_uart_t *) CFG_NIOS_CONSOLE;
 
 #if defined(CFG_NIOS_FIXEDBAUD)
 
@@ -98,7 +96,7 @@ void serial_setbrg (void)
 	unsigned div;
 
 	div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
-	uart->divisor = div;
+	writel (&uart->divisor,div);
 	return;
 }
 
@@ -118,9 +116,9 @@ void serial_putc (char c)
 {
 	if (c == '\n')
 		serial_putc ('\r');
-	while ((uart->status & NIOS_UART_TRDY) == 0)
+	while ((readl (&uart->status) & NIOS_UART_TRDY) == 0)
 		WATCHDOG_RESET ();
-	uart->txdata = (unsigned char)c;
+	writel (&uart->txdata,(unsigned char)c);
 }
 
 void serial_puts (const char *s)
@@ -132,14 +130,14 @@ void serial_puts (const char *s)
 
 int serial_tstc (void)
 {
-	return (uart->status & NIOS_UART_RRDY);
+	return (readl (&uart->status) & NIOS_UART_RRDY);
 }
 
 int serial_getc (void)
 {
 	while (serial_tstc () == 0)
 		WATCHDOG_RESET ();
-	return( uart->rxdata & 0x00ff );
+	return (readl (&uart->rxdata) & 0x00ff );
 }
 
 #endif /* CONFIG_JTAG_CONSOLE */

cpu/nios2/sysid.c

@@ -26,20 +26,21 @@
 #if defined (CFG_NIOS_SYSID_BASE)
 
 #include <command.h>
-#include <nios2.h>
+#include <asm/io.h>
 #include <nios2-io.h>
 #include <linux/time.h>
 
 void display_sysid (void)
 {
-	struct nios_sysid_t *sysid =
-		(struct nios_sysid_t *)CACHE_BYPASS(CFG_NIOS_SYSID_BASE);
+	struct nios_sysid_t *sysid = (struct nios_sysid_t *)CFG_NIOS_SYSID_BASE;
 	struct tm t;
 	char asc[32];
+	time_t stamp;
 
-	localtime_r ((time_t *)&sysid->timestamp, &t);
+	stamp = readl (&sysid->timestamp);
+	localtime_r (&stamp, &t);
 	asctime_r (&t, asc);
-	printf ("SYSID : %08x, %s", sysid->id, asc);
+	printf ("SYSID : %08x, %s", readl (&sysid->id), asc);
 
 }
 

cpu/ppc4xx/cpu_init.c

@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -101,6 +101,117 @@ DECLARE_GLOBAL_DATA_PTR;
 # endif
 #endif /* CFG_INIT_DCACHE_CS */
 
+#if defined(CFG_440_GPIO_TABLE)
+gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
+
+void set_chip_gpio_configuration(gpio_param_s (*gpio_tab)[GPIO_GROUP_MAX][GPIO_MAX])
+{
+	unsigned char i=0, j=0, reg_offset = 0, gpio_core;
+	unsigned long gpio_reg, gpio_core_add;
+
+	for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
+		j = 0;
+		reg_offset = 0;
+		/* GPIO config of the GPIOs 0 to 31 */
+		for (i=0; i<GPIO_MAX; i++, j++) {
+			if (i == GPIO_MAX/2) {
+				reg_offset = 4;
+				j = i-16;
+			}
+
+			gpio_core_add = (*gpio_tab)[gpio_core][i].add;
+
+			if (((*gpio_tab)[gpio_core][i].in_out == GPIO_IN) ||
+			     ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
+
+				switch ((*gpio_tab)[gpio_core][i].alt_nb) {
+				case GPIO_SEL:
+					break;
+
+				case GPIO_ALT1:
+					gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+					out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
+					break;
+
+				case GPIO_ALT2:
+					gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+					out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
+					break;
+
+				case GPIO_ALT3:
+					gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
+					out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
+					break;
+				}
+			}
+
+			if (((*gpio_tab)[gpio_core][i].in_out == GPIO_OUT) ||
+			     ((*gpio_tab)[gpio_core][i].in_out == GPIO_BI)) {
+
+				switch ((*gpio_tab)[gpio_core][i].alt_nb) {
+				case GPIO_SEL:
+					if (gpio_core == GPIO0) {
+						gpio_reg = in32(GPIO0_TCR) | (0x80000000 >> (j));
+						out32(GPIO0_TCR, gpio_reg);
+					}
+
+					if (gpio_core == GPIO1) {
+						gpio_reg = in32(GPIO1_TCR) | (0x80000000 >> (j));
+						out32(GPIO1_TCR, gpio_reg);
+					}
+
+					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+					break;
+
+				case GPIO_ALT1:
+					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
+					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+					break;
+
+				case GPIO_ALT2:
+					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
+					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+					break;
+
+				case GPIO_ALT3:
+					gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+					out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
+					gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset))
+						& ~(GPIO_MASK >> (j*2));
+					gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
+					out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
+					break;
+				}
+			}
+		}
+	}
+}
+#endif /* CFG_440_GPIO_TABLE */
 
 /*
  * Breath some life into the CPU...
@@ -129,10 +240,16 @@ cpu_init_f (void)
 	mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
 #endif /* CONFIG_405EP */
 
+#if defined(CFG_440_GPIO_TABLE)
+	set_chip_gpio_configuration(&gpio_tab);
+#endif /* CFG_440_GPIO_TABLE */
+
 	/*
 	 * External Bus Controller (EBC) Setup
 	 */
 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
+#if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+     defined(CONFIG_405EP) || defined(CONFIG_405))
 	/*
 	 * Move the next instructions into icache, since these modify the flash
 	 * we are running from!
@@ -148,6 +265,7 @@ cpu_init_f (void)
 	asm volatile("	ori	3, 3, 0xA000"	::: "r3");
 	asm volatile("	mtctr	3"		::: "ctr");
 	asm volatile("2:	bdnz	2b"		::: "ctr", "cr0");
+#endif
 
 	mtebc(pb0ap, CFG_EBC_PB0AP);
 	mtebc(pb0cr, CFG_EBC_PB0CR);

cpu/ppc4xx/spd_sdram.c

@@ -745,7 +745,7 @@ long int spd_sdram(void) {
 	 */
 	check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 
-#if defined(CONFIG_440GX)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
 	/*
 	 * Soft-reset SDRAM controller.
 	 */

cpu/ppc4xx/start.S

@@ -1198,12 +1198,19 @@ ppcSync:
 	.globl	relocate_code
 relocate_code:
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-	dccci	0,0			    /* Invalidate data cache, now no longer our stack */
+	/*
+	 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
+	 * to speed up the boot process. Now this cache needs to be disabled.
+	 */
+	iccci	0,0			/* Invalidate inst cache */
+	dccci	0,0			/* Invalidate data cache, now no longer our stack */
 	sync
+	isync
 	addi	r1,r0,0x0000		/* TLB entry #0 */
 	tlbre	r0,r1,0x0002		/* Read contents */
 	ori	r0,r0,0x0c00		/* Or in the inhibit, write through bit */
 	tlbwe	r0,r1,0x0002		/* Save it out */
+	sync
 	isync
 #endif
 	mr	r1,  r3		/* Set new stack pointer		*/

doc/README.m68k

@@ -1,7 +1,12 @@
 
 U-Boot for Motorola M68K
 
-Last Update: January 12, 2004
+====================================================================
+History
+
+August 08,2005; 	Jens Scharsig <esw@bus-elektronik.de>
+			MCF5282 implementation without preloader
+January 12, 2004; 	<josef.baumgartner@telex.de>
 ====================================================================
 
 This file contains status information for the port of U-Boot to the
@@ -33,16 +38,8 @@ CPU specific code is located in: cpu/mcf52x2
 -----------------------------
 CPU specific code is located in: cpu/mcf52x2
 
-At the moment the code isn't fully implemented and still needs a pre-loader!
-The preloader must initialize the processor and then start u-boot. The board
-must be configured for a pre-loader (see 4.1)
-
-For the preloader, please see
-http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html
-
-U-boot is configured to run at 0x20000 at default. This can be configured by
-change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in
-include/configs/M5282EVB.h.
+The MCF5282 Port no longer needs a preloader and can place in external or
+internal FLASH.
 
 
 3. SUPPORTED BOARDs
@@ -67,6 +64,27 @@ Board specific code is located in: board/m5282evb
 
 To configure the board, type: make M5272C3_config
 
+At the moment the code isn't fully implemented and still needs a pre-loader!
+The preloader must initialize the processor and then start u-boot. The board
+must be configured for a pre-loader (see 4.1)
+
+For the preloader, please see
+http://mailman.uclinux.org/pipermail/uclinux-dev/2003-December/023384.html
+
+U-boot is configured to run at 0x20000 at default. This can be configured by
+change TEXT_BASE in board/m5282evb/config.mk and CFG_MONITOR_BASE in
+include/configs/M5282EVB.h.
+
+3.2 BuS EB+MCF-EV123
+---------------------
+
+Board specific code is located in: board/bus/EB+MCF-EV123
+
+To configure the board, type:
+
+make EB+MCF-EV123_config 		for external FLASH
+make EB+MCF-EV123_internal_config 	for internal FLASH
+
 
 4. CONFIGURATION OPTIONS/SETTINGS
 ----------------------------------
@@ -80,7 +98,6 @@ be compiled in. The start address of u-boot must be adjusted in
 the boards config header file (CFG_MONITOR_BASE) and Makefile
 (TEXT_BASE) to the load address.
 
-
 4.1 MCF5272 specific Options/Settings
 -------------------------------------
 
@@ -123,14 +140,27 @@ CFG_INT_FLASH_BASE
 CFG_ENET_BD_BASE
 		-- defines the base addres of the FEC buffer descriptors
 
+CFG_MFD
+		-- defines the PLL Multiplication Factor Devider
+		   (see table 9-4 of MCF user manual)
+CFG_RFD		-- defines the PLL Reduce Frecuency Devider
+		   (see table 9-4 of MCF user manual)
+
+CFG_CSx_BASE	-- defines the base address of chip select x
+CFG_CSx_SIZE	-- defines the memory size (address range) of chip select x
+CFG_CSx_WIDTH	-- defines the bus with of chip select x
+CFG_CSx_RO 	-- if set to 0 chip select x is read/wirte
+			else chipselct is read only
+CFG_CSx_WS	-- defines the number of wait states  of chip select x
+
+CFG_PxDDR	-- defines the contents of the Data Direction Registers
+CFG_PxDAT	-- defines the contents of the Data Registers
+CFG_PXCNT	-- defines the contents of the Port Configuration Registers
+
+CFG_PxPAR	-- defines the function of ports
+
 
 5. COMPILER
 -----------
 To create U-Boot the gcc-2.95.3 compiler set (m68k-elf-20030314) from uClinux.org was used.
 You can download it from: http://www.uclinux.org/pub/uClinux/m68k-elf-tools/
-
-
-Regards,
-
-Josef
-<josef.baumgartner@telex.de>

drivers/cfi_flash.c

@@ -45,7 +45,6 @@
 /* #define DEBUG	*/
 
 #include <common.h>
-#include <watchdog.h>
 #include <asm/processor.h>
 #include <asm/byteorder.h>
 #include <environment.h>
@@ -794,6 +793,7 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector,
 			flash_write_cmd (info, sector, 0, info->cmd_reset);
 			return ERR_TIMOUT;
 		}
+		udelay (1);		/* also triggers watchdog */
 	}
 	return ERR_OK;
 }
@@ -1308,10 +1308,6 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest,
 	if (flag)
 		enable_interrupts ();
 
-#if defined(CONFIG_MCF52x2)
-	WATCHDOG_RESET();
-#endif
-
 	return flash_full_status_check (info, find_sector (info, dest),
 					info->write_tout, "write");
 }

examples/Makefile

@@ -42,7 +42,7 @@ LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds
 endif
 
 ifeq ($(ARCH),nios2)
-LOAD_ADDR = 0x00800000 -L $(gcclibdir) -T nios2.lds
+LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds
 endif
 
 ifeq ($(ARCH),m68k)
@@ -122,7 +122,7 @@ clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`)
 
 CPPFLAGS += -I..
 
-all:	.depend $(OBJS) $(LIB) #$(SREC) $(BIN)
+all:	.depend $(OBJS) $(LIB) $(SREC) $(BIN)
 
 #########################################################################
 $(LIB): .depend $(LIBOBJS)

examples/stubs.c

@@ -92,7 +92,7 @@ gd_t *global_data;
 #x ":\n"				\
 "	movhi	r8, %%hi(%0)\n"		\
 "	ori	r8, r0, %%lo(%0)\n"	\
-"	add	r8, r0, r15\n"		\
+"	add	r8, r8, r15\n"		\
 "	ldw	r8, 0(r8)\n"		\
 "	ldw	r8, %1(r8)\n"		\
 "	jmp	r8\n"			\

include/asm-m68k/immap_5282.h

@@ -13,7 +13,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -25,39 +25,61 @@
 #ifndef __IMMAP_5282__
 #define __IMMAP_5282__
 
+struct sys_ctrl {
+	uint ipsbar;
+	char res1[4];
+	uint rambar;
+	char res2[4];
+	uchar crsr;
+	uchar cwcr;
+	uchar lpicr;
+	uchar cwsr;
+	uint dmareqc;
+	char res3[4];
+	uint mpark;
+
+    /* TODO: finish these */
+};
 
 /* Fast ethernet controller registers
  */
 typedef struct fec {
-	uint	fec_ecntrl;		/* ethernet control register		*/
-	uint	fec_ievent;		/* interrupt event register		*/
-	uint	fec_imask;		/* interrupt mask register		*/
-	uint	fec_ivec;		/* interrupt level and vector status	*/
-	uint	fec_r_des_active;	/* Rx ring updated flag			*/
-	uint	fec_x_des_active;	/* Tx ring updated flag			*/
-	uint	res3[10];		/* reserved				*/
-	uint	fec_mii_data;		/* MII data register			*/
-	uint	fec_mii_speed;		/* MII speed control register		*/
-	uint	res4[17];		/* reserved				*/
-	uint	fec_r_bound;		/* end of RAM (read-only)		*/
-	uint	fec_r_fstart;		/* Rx FIFO start address		*/
-	uint	res5[6];		/* reserved				*/
-	uint	fec_x_fstart;		/* Tx FIFO start address		*/
-	uint	res7[21];		/* reserved				*/
-	uint	fec_r_cntrl;		/* Rx control register			*/
-	uint	fec_r_hash;		/* Rx hash register			*/
-	uint	res8[14];		/* reserved				*/
-	uint	fec_x_cntrl;		/* Tx control register			*/
-	uint	res9[0x9e];		/* reserved				*/
-	uint	fec_addr_low;		/* lower 32 bits of station address	*/
-	uint	fec_addr_high;		/* upper 16 bits of station address	*/
-	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
-	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
-	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
-	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
-	uint	fec_r_buff_size;	/* Rx buffer size			*/
-	uint	res2[9];		/* reserved				*/
-	uchar	fec_fifo[960];		/* fifo RAM				*/
+	uint	res1;		/* reserved			1000*/
+	uint	fec_ievent;	/* interrupt event register	1004*/	/* EIR */
+	uint	fec_imask;	/* interrupt mask register	1008*/	/* EIMR */
+	uint	res2;		/* reserved			100c*/
+	uint	fec_r_des_active;    /* Rx ring updated flag	1010*/	/* RDAR */
+	uint	fec_x_des_active;    /* Tx ring updated flag	1014*/	/* XDAR */
+	uint	res3[3];	/* reserved			1018*/
+	uint	fec_ecntrl;	/* ethernet control register	1024*/	/* ECR */
+	uint	res4[6];	/* reserved			1028*/
+	uint	fec_mii_data;	/* MII data register		1040*/	/* MDATA */
+	uint	fec_mii_speed;	/* MII speed control register	1044*/	/* MSCR */
+				      /*1044*/
+	uint	res5[7];	/* reserved			1048*/
+	uint	fec_mibc;	/* MIB Control/Status register	1064*/ /* MIBC */
+	uint	res6[7];	/* reserved			1068*/
+	uint	fec_r_cntrl;	/* Rx control register		1084*/	/* RCR */
+	uint	res7[15];	/* reserved			1088*/
+	uint	fec_x_cntrl;	/* Tx control register		10C4*/	/* TCR */
+	uint	res8[7];	/* reserved			10C8*/
+	uint	fec_addr_low;	/* lower 32 bits of station address */	/* PALR */
+	uint	fec_addr_high;	/* upper 16 bits of station address  */ /* PAUR */
+	uint	fec_opd;	/* opcode + pause duration	10EC*/	/* OPD */
+	uint	res9[10];	/* reserved			10F0*/
+	uint	fec_ihash_table_high;	/* upper 32-bits of individual hash */ /* IAUR */
+	uint	fec_ihash_table_low;	/* lower 32-bits of individual hash */ /* IALR */
+	uint	fec_ghash_table_high;	/* upper 32-bits of group hash	*/ /* GAUR */
+	uint	fec_ghash_table_low;	/* lower 32-bits of group hash	*/ /* GALR */
+	uint	res10[7];	/* reserved			1128*/
+	uint	fec_tfwr;	/* Transmit FIFO watermark	1144*/	/* TFWR */
+	uint	res11;		/* reserved			1148*/
+	uint	fec_r_bound;	/* FIFO Receive Bound Register = end of */ /* FRBR */
+	uint	fec_r_fstart;	/* FIFO Receive FIfo Start Registers =	*/ /* FRSR */
+	uint	res12[11];	/* reserved			1154*/
+	uint	fec_r_des_start;/* beginning of Rx descriptor ring    1180*/ /* ERDSR */
+	uint	fec_x_des_start;/* beginning of Tx descriptor ring    1184*/ /* ETDSR */
+	uint	fec_r_buff_size;/* Rx buffer size		1188*/	/* EMRBR */
 } fec_t;
 
 #endif /* __IMMAP_5282__ */

include/asm-m68k/m5282.h

@@ -1,9 +1,6 @@
 /*
  * mcf5282.h -- Definitions for Motorola Coldfire 5282
  *
- * Based on mcf5282sim.h of uCLinux distribution:
- *      (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
- *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -34,27 +31,515 @@
 
 #define INT_RAM_SIZE	65536
 
+/* General Purpose I/O Module GPIO */
 
-/*
- *	Define the 5282 SIM register set addresses.
- */
-#define	MCFICM_INTC0		0x0c00		/* Base for Interrupt Ctrl 0 */
-#define	MCFICM_INTC1		0x0d00		/* Base for Interrupt Ctrl 0 */
-#define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
-#define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
-#define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
-#define	MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
-#define	MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
-#define	MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
-#define	MCFINTC_IRLR		0x18		/* */
-#define	MCFINTC_IACKL		0x19		/* */
-#define	MCFINTC_ICR0		0x40		/* Base ICR register */
+#define MCFGPIO_PORTA		(*(vu_char *) (CFG_MBAR+0x100000))
+#define MCFGPIO_PORTB		(*(vu_char *) (CFG_MBAR+0x100001))
+#define MCFGPIO_PORTC		(*(vu_char *) (CFG_MBAR+0x100002))
+#define MCFGPIO_PORTD		(*(vu_char *) (CFG_MBAR+0x100003))
+#define MCFGPIO_PORTE		(*(vu_char *) (CFG_MBAR+0x100004))
+#define MCFGPIO_PORTF		(*(vu_char *) (CFG_MBAR+0x100005))
+#define MCFGPIO_PORTG		(*(vu_char *) (CFG_MBAR+0x100006))
+#define MCFGPIO_PORTH		(*(vu_char *) (CFG_MBAR+0x100007))
+#define MCFGPIO_PORTJ		(*(vu_char *) (CFG_MBAR+0x100008))
+#define MCFGPIO_PORTDD		(*(vu_char *) (CFG_MBAR+0x100009))
+#define MCFGPIO_PORTEH		(*(vu_char *) (CFG_MBAR+0x10000A))
+#define MCFGPIO_PORTEL		(*(vu_char *) (CFG_MBAR+0x10000B))
+#define MCFGPIO_PORTAS		(*(vu_char *) (CFG_MBAR+0x10000C))
+#define MCFGPIO_PORTQS		(*(vu_char *) (CFG_MBAR+0x10000D))
+#define MCFGPIO_PORTSD		(*(vu_char *) (CFG_MBAR+0x10000E))
+#define MCFGPIO_PORTTC		(*(vu_char *) (CFG_MBAR+0x10000F))
+#define MCFGPIO_PORTTD		(*(vu_char *) (CFG_MBAR+0x100010))
+#define MCFGPIO_PORTUA		(*(vu_char *) (CFG_MBAR+0x100011))
 
-#define	MCFINT_UART0		13		/* Interrupt number for UART0 */
-#define	MCFINT_PIT1		55		/* Interrupt number for PIT1 */
+#define MCFGPIO_DDRA		(*(vu_char *) (CFG_MBAR+0x100014))
+#define MCFGPIO_DDRB		(*(vu_char *) (CFG_MBAR+0x100015))
+#define MCFGPIO_DDRC		(*(vu_char *) (CFG_MBAR+0x100016))
+#define MCFGPIO_DDRD		(*(vu_char *) (CFG_MBAR+0x100017))
+#define MCFGPIO_DDRE		(*(vu_char *) (CFG_MBAR+0x100018))
+#define MCFGPIO_DDRF		(*(vu_char *) (CFG_MBAR+0x100019))
+#define MCFGPIO_DDRG		(*(vu_char *) (CFG_MBAR+0x10001A))
+#define MCFGPIO_DDRH		(*(vu_char *) (CFG_MBAR+0x10001B))
+#define MCFGPIO_DDRJ		(*(vu_char *) (CFG_MBAR+0x10001C))
+#define MCFGPIO_DDRDD		(*(vu_char *) (CFG_MBAR+0x10001D))
+#define MCFGPIO_DDREH		(*(vu_char *) (CFG_MBAR+0x10001E))
+#define MCFGPIO_DDREL		(*(vu_char *) (CFG_MBAR+0x10001F))
+#define MCFGPIO_DDRAS		(*(vu_char *) (CFG_MBAR+0x100020))
+#define MCFGPIO_DDRQS		(*(vu_char *) (CFG_MBAR+0x100021))
+#define MCFGPIO_DDRSD		(*(vu_char *) (CFG_MBAR+0x100022))
+#define MCFGPIO_DDRTC		(*(vu_char *) (CFG_MBAR+0x100023))
+#define MCFGPIO_DDRTD		(*(vu_char *) (CFG_MBAR+0x100024))
+#define MCFGPIO_DDRUA		(*(vu_char *) (CFG_MBAR+0x100025))
 
-#define	MCF5282_GPIO_PUAPAR	0x10005C
+#define MCFGPIO_PORTAP		(*(vu_char *) (CFG_MBAR+0x100028))
+#define MCFGPIO_PORTBP		(*(vu_char *) (CFG_MBAR+0x100029))
+#define MCFGPIO_PORTCP		(*(vu_char *) (CFG_MBAR+0x10002A))
+#define MCFGPIO_PORTDP		(*(vu_char *) (CFG_MBAR+0x10002B))
+#define MCFGPIO_PORTEP		(*(vu_char *) (CFG_MBAR+0x10002C))
+#define MCFGPIO_PORTFP		(*(vu_char *) (CFG_MBAR+0x10002D))
+#define MCFGPIO_PORTGP		(*(vu_char *) (CFG_MBAR+0x10002E))
+#define MCFGPIO_PORTHP		(*(vu_char *) (CFG_MBAR+0x10002F))
+#define MCFGPIO_PORTJP		(*(vu_char *) (CFG_MBAR+0x100030))
+#define MCFGPIO_PORTDDP		(*(vu_char *) (CFG_MBAR+0x100031))
+#define MCFGPIO_PORTEHP		(*(vu_char *) (CFG_MBAR+0x100032))
+#define MCFGPIO_PORTELP		(*(vu_char *) (CFG_MBAR+0x100033))
+#define MCFGPIO_PORTASP		(*(vu_char *) (CFG_MBAR+0x100034))
+#define MCFGPIO_PORTQSP		(*(vu_char *) (CFG_MBAR+0x100035))
+#define MCFGPIO_PORTSDP		(*(vu_char *) (CFG_MBAR+0x100036))
+#define MCFGPIO_PORTTCP		(*(vu_char *) (CFG_MBAR+0x100037))
+#define MCFGPIO_PORTTDP		(*(vu_char *) (CFG_MBAR+0x100038))
+#define MCFGPIO_PORTUAP		(*(vu_char *) (CFG_MBAR+0x100039))
 
+#define MCFGPIO_SETA		(*(vu_char *) (CFG_MBAR+0x100028))
+#define MCFGPIO_SETB		(*(vu_char *) (CFG_MBAR+0x100029))
+#define MCFGPIO_SETC		(*(vu_char *) (CFG_MBAR+0x10002A))
+#define MCFGPIO_SETD		(*(vu_char *) (CFG_MBAR+0x10002B))
+#define MCFGPIO_SETE		(*(vu_char *) (CFG_MBAR+0x10002C))
+#define MCFGPIO_SETF		(*(vu_char *) (CFG_MBAR+0x10002D))
+#define MCFGPIO_SETG   		(*(vu_char *) (CFG_MBAR+0x10002E))
+#define MCFGPIO_SETH   		(*(vu_char *) (CFG_MBAR+0x10002F))
+#define MCFGPIO_SETJ   		(*(vu_char *) (CFG_MBAR+0x100030))
+#define MCFGPIO_SETDD  		(*(vu_char *) (CFG_MBAR+0x100031))
+#define MCFGPIO_SETEH  		(*(vu_char *) (CFG_MBAR+0x100032))
+#define MCFGPIO_SETEL  		(*(vu_char *) (CFG_MBAR+0x100033))
+#define MCFGPIO_SETAS  		(*(vu_char *) (CFG_MBAR+0x100034))
+#define MCFGPIO_SETQS  		(*(vu_char *) (CFG_MBAR+0x100035))
+#define MCFGPIO_SETSD  		(*(vu_char *) (CFG_MBAR+0x100036))
+#define MCFGPIO_SETTC  		(*(vu_char *) (CFG_MBAR+0x100037))
+#define MCFGPIO_SETTD  		(*(vu_char *) (CFG_MBAR+0x100038))
+#define MCFGPIO_SETUA  		(*(vu_char *) (CFG_MBAR+0x100039))
+
+#define MCFGPIO_CLRA  		(*(vu_char *) (CFG_MBAR+0x10003C))
+#define MCFGPIO_CLRB  		(*(vu_char *) (CFG_MBAR+0x10003D))
+#define MCFGPIO_CLRC  		(*(vu_char *) (CFG_MBAR+0x10003E))
+#define MCFGPIO_CLRD  		(*(vu_char *) (CFG_MBAR+0x10003F))
+#define MCFGPIO_CLRE  		(*(vu_char *) (CFG_MBAR+0x100040))
+#define MCFGPIO_CLRF  		(*(vu_char *) (CFG_MBAR+0x100041))
+#define MCFGPIO_CLRG  		(*(vu_char *) (CFG_MBAR+0x100042))
+#define MCFGPIO_CLRH  		(*(vu_char *) (CFG_MBAR+0x100043))
+#define MCFGPIO_CLRJ  		(*(vu_char *) (CFG_MBAR+0x100044))
+#define MCFGPIO_CLRDD  		(*(vu_char *) (CFG_MBAR+0x100045))
+#define MCFGPIO_CLREH  		(*(vu_char *) (CFG_MBAR+0x100046))
+#define MCFGPIO_CLREL  		(*(vu_char *) (CFG_MBAR+0x100047))
+#define MCFGPIO_CLRAS  		(*(vu_char *) (CFG_MBAR+0x100048))
+#define MCFGPIO_CLRQS  		(*(vu_char *) (CFG_MBAR+0x100049))
+#define MCFGPIO_CLRSD  		(*(vu_char *) (CFG_MBAR+0x10004A))
+#define MCFGPIO_CLRTC  		(*(vu_char *) (CFG_MBAR+0x10004B))
+#define MCFGPIO_CLRTD  		(*(vu_char *) (CFG_MBAR+0x10004C))
+#define MCFGPIO_CLRUA  		(*(vu_char *) (CFG_MBAR+0x10004D))
+
+#define MCFGPIO_PBCDPAR  	(*(vu_char *) (CFG_MBAR+0x100050))
+#define MCFGPIO_PFPAR  		(*(vu_char *) (CFG_MBAR+0x100051))
+#define MCFGPIO_PEPAR  		(*(vu_short *)(CFG_MBAR+0x100052))
+#define MCFGPIO_PJPAR  		(*(vu_char *) (CFG_MBAR+0x100054))
+#define MCFGPIO_PSDPAR  	(*(vu_char *) (CFG_MBAR+0x100055))
+#define MCFGPIO_PASPAR  	(*(vu_short *)(CFG_MBAR+0x100056))
+#define MCFGPIO_PEHLPAR  	(*(vu_char *) (CFG_MBAR+0x100058))
+#define MCFGPIO_PQSPAR  	(*(vu_char *) (CFG_MBAR+0x100059))
+#define MCFGPIO_PTCPAR  	(*(vu_char *) (CFG_MBAR+0x10005A))
+#define MCFGPIO_PTDPAR  	(*(vu_char *) (CFG_MBAR+0x10005B))
+#define MCFGPIO_PUAPAR  	(*(vu_char *) (CFG_MBAR+0x10005C))
+
+/* Bit level definitions and macros */
+#define MCFGPIO_PORT7			(0x80)
+#define MCFGPIO_PORT6			(0x40)
+#define MCFGPIO_PORT5			(0x20)
+#define MCFGPIO_PORT4			(0x10)
+#define MCFGPIO_PORT3			(0x08)
+#define MCFGPIO_PORT2			(0x04)
+#define MCFGPIO_PORT1			(0x02)
+#define MCFGPIO_PORT0			(0x01)
+#define MCFGPIO_PORT(x)			(0x01<<x)
+
+#define MCFGPIO_DDR7			(0x80)
+#define MCFGPIO_DDR6			(0x40)
+#define MCFGPIO_DDR5			(0x20)
+#define MCFGPIO_DDR4			(0x10)
+#define MCFGPIO_DDR3			(0x08)
+#define MCFGPIO_DDR2			(0x04)
+#define MCFGPIO_DDR1			(0x02)
+#define MCFGPIO_DDR0			(0x01)
+#define MCFGPIO_DDR(x)			(0x01<<x)
+
+#define MCFGPIO_Px7			(0x80)
+#define MCFGPIO_Px6			(0x40)
+#define MCFGPIO_Px5			(0x20)
+#define MCFGPIO_Px4			(0x10)
+#define MCFGPIO_Px3			(0x08)
+#define MCFGPIO_Px2			(0x04)
+#define MCFGPIO_Px1			(0x02)
+#define MCFGPIO_Px0			(0x01)
+#define MCFGPIO_Px(x)			(0x01<<x)
+
+
+#define MCFGPIO_PBCDPAR_PBPA		(0x80)
+#define MCFGPIO_PBCDPAR_PCDPA		(0x40)
+
+#define MCFGPIO_PEPAR_PEPA7		(0x4000)
+#define MCFGPIO_PEPAR_PEPA6		(0x1000)
+#define MCFGPIO_PEPAR_PEPA5		(0x0400)
+#define MCFGPIO_PEPAR_PEPA4		(0x0100)
+#define MCFGPIO_PEPAR_PEPA3		(0x0040)
+#define MCFGPIO_PEPAR_PEPA2		(0x0010)
+#define MCFGPIO_PEPAR_PEPA1(x)		(((x)&0x3)<<2)
+#define MCFGPIO_PEPAR_PEPA0(x)		(((x)&0x3))
+
+#define MCFGPIO_PFPAR_PFPA7		(0x80)
+#define MCFGPIO_PFPAR_PFPA6		(0x40)
+#define MCFGPIO_PFPAR_PFPA5		(0x20)
+
+#define MCFGPIO_PJPAR_PJPA7		(0x80)
+#define MCFGPIO_PJPAR_PJPA6		(0x40)
+#define MCFGPIO_PJPAR_PJPA5		(0x20)
+#define MCFGPIO_PJPAR_PJPA4		(0x10)
+#define MCFGPIO_PJPAR_PJPA3		(0x08)
+#define MCFGPIO_PJPAR_PJPA2		(0x04)
+#define MCFGPIO_PJPAR_PJPA1		(0x02)
+#define MCFGPIO_PJPAR_PJPA0		(0x01)
+#define MCFGPIO_PJPAR_PJPA(x)		(0x01<<x)
+
+#define MCFGPIO_PSDPAR_PSDPA		(0x80)
+
+#define MCFGPIO_PASPAR_PASPA5(x)	(((x)&0x3)<<10)
+#define MCFGPIO_PASPAR_PASPA4(x)	(((x)&0x3)<<8)
+#define MCFGPIO_PASPAR_PASPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PASPAR_PASPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PASPAR_PASPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PASPAR_PASPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PEHLPAR_PEHPA		(0x80)
+#define MCFGPIO_PEHLPAR_PELPA		(0x40)
+
+#define MCFGPIO_PQSPAR_PQSPA6		(0x40)
+#define MCFGPIO_PQSPAR_PQSPA5		(0x20)
+#define MCFGPIO_PQSPAR_PQSPA4		(0x10)
+#define MCFGPIO_PQSPAR_PQSPA3		(0x08)
+#define MCFGPIO_PQSPAR_PQSPA2		(0x04)
+#define MCFGPIO_PQSPAR_PQSPA1		(0x02)
+#define MCFGPIO_PQSPAR_PQSPA0		(0x01)
+#define MCFGPIO_PQSPAR_PQSPA(x)		(0x01<<x)
+
+#define MCFGPIO_PTCPAR_PTCPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PTCPAR_PTCPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PTCPAR_PTCPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PTCPAR_PTCPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PTDPAR_PTDPA3(x)	(((x)&0x3)<<6)
+#define MCFGPIO_PTDPAR_PTDPA2(x)	(((x)&0x3)<<4)
+#define MCFGPIO_PTDPAR_PTDPA1(x)	(((x)&0x3)<<2)
+#define MCFGPIO_PTDPAR_PTDPA0(x)	(((x)&0x3))
+
+#define MCFGPIO_PUAPAR_PUAPA3		(0x08)
+#define MCFGPIO_PUAPAR_PUAPA2		(0x04)
+#define MCFGPIO_PUAPAR_PUAPA1		(0x02)
+#define MCFGPIO_PUAPAR_PUAPA0		(0x01)
+
+/* System Conrol Module SCM */
+
+#define MCFSCM_RAMBAR           (*(vu_long *) (CFG_MBAR+0x00000008))
+#define MCFSCM_CRSR		(*(vu_char *) (CFG_MBAR+0x00000010))
+#define MCFSCM_CWCR		(*(vu_char *) (CFG_MBAR+0x00000011))
+#define MCFSCM_LPICR		(*(vu_char *) (CFG_MBAR+0x00000012))
+#define MCFSCM_CWSR		(*(vu_char *) (CFG_MBAR+0x00000013))
+
+#define MCFSCM_MPARK		(*(vu_long *) (CFG_MBAR+0x0000001C))
+#define MCFSCM_MPR		(*(vu_char *) (CFG_MBAR+0x00000020))
+#define MCFSCM_PACR0		(*(vu_char *) (CFG_MBAR+0x00000024))
+#define MCFSCM_PACR1		(*(vu_char *) (CFG_MBAR+0x00000025))
+#define MCFSCM_PACR2		(*(vu_char *) (CFG_MBAR+0x00000026))
+#define MCFSCM_PACR3		(*(vu_char *) (CFG_MBAR+0x00000027))
+#define MCFSCM_PACR4		(*(vu_char *) (CFG_MBAR+0x00000028))
+#define MCFSCM_PACR5		(*(vu_char *) (CFG_MBAR+0x0000002A))
+#define MCFSCM_PACR6		(*(vu_char *) (CFG_MBAR+0x0000002B))
+#define MCFSCM_PACR7		(*(vu_char *) (CFG_MBAR+0x0000002C))
+#define MCFSCM_PACR8		(*(vu_char *) (CFG_MBAR+0x0000002E))
+#define MCFSCM_GPACR0		(*(vu_char *) (CFG_MBAR+0x00000030))
+#define MCFSCM_GPACR1		(*(vu_char *) (CFG_MBAR+0x00000031))
+
+
+#define MCFSCM_CRSR_EXT		(0x80)
+#define MCFSCM_CRSR_CWDR	(0x20)
+#define MCFSCM_RAMBAR_BA(x)     ((x)&0xFFFF0000)
+#define MCFSCM_RAMBAR_BDE       (0x00000200)
+
+/* Reset Controller Module RCM */
+
+#define MCFRESET_RCR		(*(vu_char *) (CFG_MBAR+0x00110000))
+#define MCFRESET_RSR		(*(vu_char *) (CFG_MBAR+0x00110001))
+
+#define MCFRESET_RCR_SOFTRST    (0x80)
+#define MCFRESET_RCR_FRCRSTOUT  (0x40)
+#define MCFRESET_RCR_LVDF       (0x10)
+#define MCFRESET_RCR_LVDIE      (0x08)
+#define MCFRESET_RCR_LVDRE      (0x04)
+#define MCFRESET_RCR_LVDE       (0x01)
+
+#define MCFRESET_RSR_LVD        (0x40)
+#define MCFRESET_RSR_SOFT       (0x20)
+#define MCFRESET_RSR_WDR        (0x10)
+#define MCFRESET_RSR_POR        (0x08)
+#define MCFRESET_RSR_EXT        (0x04)
+#define MCFRESET_RSR_LOC        (0x02)
+#define MCFRESET_RSR_LOL        (0x01)
+#define MCFRESET_RSR_ALL        (0x7F)
+#define MCFRESET_RCR_SOFTRST    (0x80)
+#define MCFRESET_RCR_FRCRSTOUT  (0x40)
+
+/* Chip Configuration Module CCM */
+
+#define MCFCCM_CCR		(*(vu_short *)(CFG_MBAR+0x00110004))
+#define MCFCCM_RCON		(*(vu_short *)(CFG_MBAR+0x00110008))
+#define MCFCCM_CIR		(*(vu_short *)(CFG_MBAR+0x0011000A))
+
+
+/* Bit level definitions and macros */
+#define MCFCCM_CCR_LOAD			(0x8000)
+#define MCFCCM_CCR_MODE(x) 		(((x)&0x0007)<<8)
+#define MCFCCM_CCR_SZEN    		(0x0040)
+#define MCFCCM_CCR_PSTEN   		(0x0020)
+#define MCFCCM_CCR_BME			(0x0008)
+#define MCFCCM_CCR_BMT(x)  		(((x)&0x0007))
+
+#define MCFCCM_CIR_PIN_MASK		(0xFF00)
+#define MCFCCM_CIR_PRN_MASK		(0x00FF)
+
+/* Clock Module */
+
+#define MCFCLOCK_SYNCR          (*(vu_short *)(CFG_MBAR+0x120000))
+#define MCFCLOCK_SYNSR          (*(vu_char *) (CFG_MBAR+0x120002))
+
+#define MCFCLOCK_SYNCR_MFD(x)   (((x)&0x0007)<<12)
+#define MCFCLOCK_SYNCR_RFD(x)   (((x)&0x0007)<<8)
+#define MCFCLOCK_SYNSR_LOCK     0x08
+
+#define MCFSDRAMC_DCR		(*(vu_short *)(CFG_MBAR+0x00000040))
+#define MCFSDRAMC_DACR0		(*(vu_long *) (CFG_MBAR+0x00000048))
+#define MCFSDRAMC_DMR0		(*(vu_long *) (CFG_MBAR+0x0000004c))
+#define MCFSDRAMC_DACR1		(*(vu_long *) (CFG_MBAR+0x00000050))
+#define MCFSDRAMC_DMR1		(*(vu_long *) (CFG_MBAR+0x00000054))
+
+#define MCFSDRAMC_DCR_NAM	(0x2000)
+#define MCFSDRAMC_DCR_COC	(0x1000)
+#define MCFSDRAMC_DCR_IS	(0x0800)
+#define MCFSDRAMC_DCR_RTIM_3	(0x0000)
+#define MCFSDRAMC_DCR_RTIM_6	(0x0200)
+#define MCFSDRAMC_DCR_RTIM_9	(0x0400)
+#define MCFSDRAMC_DCR_RC(x)	((x)&0x01FF)
+
+#define MCFSDRAMC_DACR_BASE(x)	((x)&0xFFFC0000)
+#define MCFSDRAMC_DACR_RE	(0x00008000)
+#define MCFSDRAMC_DACR_CASL(x)	(((x)&0x03)<<12)
+#define MCFSDRAMC_DACR_CBM(x)	(((x)&0x07)<<8)
+#define MCFSDRAMC_DACR_PS_32	(0x00000000)
+#define MCFSDRAMC_DACR_PS_16	(0x00000020)
+#define MCFSDRAMC_DACR_PS_8	(0x00000010)
+#define MCFSDRAMC_DACR_IP	(0x00000008)
+#define MCFSDRAMC_DACR_IMRS	(0x00000040)
+
+#define MCFSDRAMC_DMR_BAM_16M	(0x00FC0000)
+#define MCFSDRAMC_DMR_WP        (0x00000100)
+#define MCFSDRAMC_DMR_CI        (0x00000040)
+#define MCFSDRAMC_DMR_AM        (0x00000020)
+#define MCFSDRAMC_DMR_SC        (0x00000010)
+#define MCFSDRAMC_DMR_SD        (0x00000008)
+#define MCFSDRAMC_DMR_UC        (0x00000004)
+#define MCFSDRAMC_DMR_UD        (0x00000002)
+#define MCFSDRAMC_DMR_V         (0x00000001)
+
+#define MCFWTM_WCR              (*(vu_short *)(CFG_MBAR+0x00140000))
+#define MCFWTM_WMR              (*(vu_short *)(CFG_MBAR+0x00140002))
+#define MCFWTM_WCNTR            (*(vu_short *)(CFG_MBAR+0x00140004))
+#define MCFWTM_WSR              (*(vu_short *)(CFG_MBAR+0x00140006))
+
+/*  Chip SELECT Module CSM */
+#define MCFCSM_CSAR0		(*(vu_short *)(CFG_MBAR+0x00000080))
+#define MCFCSM_CSMR0		(*(vu_long *) (CFG_MBAR+0x00000084))
+#define MCFCSM_CSCR0		(*(vu_short *)(CFG_MBAR+0x0000008a))
+#define MCFCSM_CSAR1		(*(vu_short *)(CFG_MBAR+0x0000008C))
+#define MCFCSM_CSMR1		(*(vu_long *) (CFG_MBAR+0x00000090))
+#define MCFCSM_CSCR1		(*(vu_short *)(CFG_MBAR+0x00000096))
+#define MCFCSM_CSAR2		(*(vu_short *)(CFG_MBAR+0x00000098))
+#define MCFCSM_CSMR2		(*(vu_long *) (CFG_MBAR+0x0000009C))
+#define MCFCSM_CSCR2		(*(vu_short *)(CFG_MBAR+0x000000A2))
+#define MCFCSM_CSAR3		(*(vu_short *)(CFG_MBAR+0x000000A4))
+#define MCFCSM_CSMR3		(*(vu_long *) (CFG_MBAR+0x000000A8))
+#define MCFCSM_CSCR3		(*(vu_short *)(CFG_MBAR+0x000000AE))
+
+#define MCFCSM_CSMR_BAM(x)	((x) & 0xFFFF0000)
+#define MCFCSM_CSMR_WP		(1<<8)
+#define MCFCSM_CSMR_V		(0x01)
+#define MCFCSM_CSCR_WS(x)	((x & 0x0F)<<10)
+#define MCFCSM_CSCR_AA		(0x0100)
+#define MCFCSM_CSCR_PS_32	(0x0000)
+#define MCFCSM_CSCR_PS_8	(0x0040)
+#define MCFCSM_CSCR_PS_16	(0x0080)
+
+/*********************************************************************
+*
+* General Purpose Timer (GPT) Module
+*
+*********************************************************************/
+
+#define MCFGPTA_GPTIOS		(*(vu_char *)(CFG_MBAR+0x1A0000))
+#define MCFGPTA_GPTCFORC	(*(vu_char *)(CFG_MBAR+0x1A0001))
+#define MCFGPTA_GPTOC3M		(*(vu_char *)(CFG_MBAR+0x1A0002))
+#define MCFGPTA_GPTOC3D		(*(vu_char *)(CFG_MBAR+0x1A0003))
+#define MCFGPTA_GPTCNT		(*(vu_short *)(CFG_MBAR+0x1A0004))
+#define MCFGPTA_GPTSCR1		(*(vu_char *)(CFG_MBAR+0x1A0006))
+#define MCFGPTA_GPTTOV		(*(vu_char *)(CFG_MBAR+0x1A0008))
+#define MCFGPTA_GPTCTL1		(*(vu_char *)(CFG_MBAR+0x1A0009))
+#define MCFGPTA_GPTCTL2		(*(vu_char *)(CFG_MBAR+0x1A000B))
+#define MCFGPTA_GPTIE		(*(vu_char *)(CFG_MBAR+0x1A000C))
+#define MCFGPTA_GPTSCR2		(*(vu_char *)(CFG_MBAR+0x1A000D))
+#define MCFGPTA_GPTFLG1		(*(vu_char *)(CFG_MBAR+0x1A000E))
+#define MCFGPTA_GPTFLG2		(*(vu_char *)(CFG_MBAR+0x1A000F))
+#define MCFGPTA_GPTC0		(*(vu_short *)(CFG_MBAR+0x1A0010))
+#define MCFGPTA_GPTC1		(*(vu_short *)(CFG_MBAR+0x1A0012))
+#define MCFGPTA_GPTC2		(*(vu_short *)(CFG_MBAR+0x1A0014))
+#define MCFGPTA_GPTC3		(*(vu_short *)(CFG_MBAR+0x1A0016))
+#define MCFGPTA_GPTPACTL	(*(vu_char *)(CFG_MBAR+0x1A0018))
+#define MCFGPTA_GPTPAFLG	(*(vu_char *)(CFG_MBAR+0x1A0019))
+#define MCFGPTA_GPTPACNT	(*(vu_short *)(CFG_MBAR+0x1A001A))
+#define MCFGPTA_GPTPORT		(*(vu_char *)(CFG_MBAR+0x1A001D))
+#define MCFGPTA_GPTDDR		(*(vu_char *)(CFG_MBAR+0x1A001E))
+
+
+#define MCFGPTB_GPTIOS		(*(vu_char *)(CFG_MBAR+0x1B0000))
+#define MCFGPTB_GPTCFORC	(*(vu_char *)(CFG_MBAR+0x1B0001))
+#define MCFGPTB_GPTOC3M		(*(vu_char *)(CFG_MBAR+0x1B0002))
+#define MCFGPTB_GPTOC3D		(*(vu_char *)(CFG_MBAR+0x1B0003))
+#define MCFGPTB_GPTCNT		(*(vu_short *)(CFG_MBAR+0x1B0004))
+#define MCFGPTB_GPTSCR1		(*(vu_char *)(CFG_MBAR+0x1B0006))
+#define MCFGPTB_GPTTOV		(*(vu_char *)(CFG_MBAR+0x1B0008))
+#define MCFGPTB_GPTCTL1		(*(vu_char *)(CFG_MBAR+0x1B0009))
+#define MCFGPTB_GPTCTL2		(*(vu_char *)(CFG_MBAR+0x1B000B))
+#define MCFGPTB_GPTIE		(*(vu_char *)(CFG_MBAR+0x1B000C))
+#define MCFGPTB_GPTSCR2		(*(vu_char *)(CFG_MBAR+0x1B000D))
+#define MCFGPTB_GPTFLG1		(*(vu_char *)(CFG_MBAR+0x1B000E))
+#define MCFGPTB_GPTFLG2		(*(vu_char *)(CFG_MBAR+0x1B000F))
+#define MCFGPTB_GPTC0		(*(vu_short *)(CFG_MBAR+0x1B0010))
+#define MCFGPTB_GPTC1		(*(vu_short *)(CFG_MBAR+0x1B0012))
+#define MCFGPTB_GPTC2		(*(vu_short *)(CFG_MBAR+0x1B0014))
+#define MCFGPTB_GPTC3		(*(vu_short *)(CFG_MBAR+0x1B0016))
+#define MCFGPTB_GPTPACTL	(*(vu_char *)(CFG_MBAR+0x1B0018))
+#define MCFGPTB_GPTPAFLG	(*(vu_char *)(CFG_MBAR+0x1B0019))
+#define MCFGPTB_GPTPACNT	(*(vu_short *)(CFG_MBAR+0x1B001A))
+#define MCFGPTB_GPTPORT		(*(vu_char *)(CFG_MBAR+0x1B001D))
+#define MCFGPTB_GPTDDR		(*(vu_char *)(CFG_MBAR+0x1B001E))
+
+/* Bit level definitions and macros */
+#define MCFGPT_GPTIOS_IOS3		(0x08)
+#define MCFGPT_GPTIOS_IOS2		(0x04)
+#define MCFGPT_GPTIOS_IOS1		(0x02)
+#define MCFGPT_GPTIOS_IOS0		(0x01)
+
+#define MCFGPT_GPTCFORC_FOC3		(0x08)
+#define MCFGPT_GPTCFORC_FOC2		(0x04)
+#define MCFGPT_GPTCFORC_FOC1		(0x02)
+#define MCFGPT_GPTCFORC_FOC0		(0x01)
+
+#define MCFGPT_GPTOC3M_OC3M3		(0x08)
+#define MCFGPT_GPTOC3M_OC3M2		(0x04)
+#define MCFGPT_GPTOC3M_OC3M1		(0x02)
+#define MCFGPT_GPTOC3M_OC3M0		(0x01)
+
+#define MCFGPT_GPTOC3M_OC3D(x)		(((x)&0x04))
+
+#define MCFGPT_GPTSCR1_GPTEN		(0x80)
+#define MCFGPT_GPTSCR1_TFFCA		(0x10)
+
+#define MCFGPT_GPTTOV3			(0x08)
+#define MCFGPT_GPTTOV2			(0x04)
+#define MCFGPT_GPTTOV1			(0x02)
+#define MCFGPT_GPTTOV0			(0x01)
+
+#define MCFGPT_GPTCTL_OMOL3(x)		(((x)&0x03)<<6)
+#define MCFGPT_GPTCTL_OMOL2(x)		(((x)&0x03)<<4)
+#define MCFGPT_GPTCTL_OMOL1(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTCTL_OMOL0(x)		(((x)&0x03))
+
+#define MCFGPT_GPTCTL2_EDG3(x)		(((x)&0x03)<<6)
+#define MCFGPT_GPTCTL2_EDG2(x)		(((x)&0x03)<<4)
+#define MCFGPT_GPTCTL2_EDG1(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTCTL2_EDG0(x)		(((x)&0x03))
+
+#define MCFGPT_GPTIE_C3I		(0x08)
+#define MCFGPT_GPTIE_C2I		(0x04)
+#define MCFGPT_GPTIE_C1I		(0x02)
+#define MCFGPT_GPTIE_C0I		(0x01)
+
+#define MCFGPT_GPTSCR2_TOI 		(0x80)
+#define MCFGPT_GPTSCR2_PUPT		(0x20)
+#define MCFGPT_GPTSCR2_RDPT		(0x10)
+#define MCFGPT_GPTSCR2_TCRE		(0x08)
+#define MCFGPT_GPTSCR2_PR(x)		(((x)&0x07))
+
+#define MCFGPT_GPTFLG1_C3F		(0x08)
+#define MCFGPT_GPTFLG1_C2F		(0x04)
+#define MCFGPT_GPTFLG1_C1F		(0x02)
+#define MCFGPT_GPTFLG1_C0F		(0x01)
+
+#define MCFGPT_GPTFLG2_TOF		(0x80)
+#define MCFGPT_GPTFLG2_C3F		(0x08)
+#define MCFGPT_GPTFLG2_C2F		(0x04)
+#define MCFGPT_GPTFLG2_C1F		(0x02)
+#define MCFGPT_GPTFLG2_C0F		(0x01)
+
+#define MCFGPT_GPTPACTL_PAE		(0x40)
+#define MCFGPT_GPTPACTL_PAMOD		(0x20)
+#define MCFGPT_GPTPACTL_PEDGE		(0x10)
+#define MCFGPT_GPTPACTL_CLK_PACLK	(0x04)
+#define MCFGPT_GPTPACTL_CLK_PACLK256	(0x08)
+#define MCFGPT_GPTPACTL_CLK_PACLK65536	(0x0C)
+#define MCFGPT_GPTPACTL_CLK(x)		(((x)&0x03)<<2)
+#define MCFGPT_GPTPACTL_PAOVI		(0x02)
+#define MCFGPT_GPTPACTL_PAI		(0x01)
+
+#define MCFGPT_GPTPAFLG_PAOVF		(0x02)
+#define MCFGPT_GPTPAFLG_PAIF		(0x01)
+
+#define MCFGPT_GPTPORT_PORTT3		(0x08)
+#define MCFGPT_GPTPORT_PORTT2		(0x04)
+#define MCFGPT_GPTPORT_PORTT1		(0x02)
+#define MCFGPT_GPTPORT_PORTT0		(0x01)
+
+#define MCFGPT_GPTDDR_DDRT3		(0x08)
+#define MCFGPT_GPTDDR_DDRT2		(0x04)
+#define MCFGPT_GPTDDR_DDRT1		(0x02)
+#define MCFGPT_GPTDDR_DDRT0		(0x01)
+
+/* Coldfire Flash Module CFM */
+
+#define MCFCFM_MCR			(*(vu_short *)(CFG_MBAR+0x1D0000))
+#define MCFCFM_MCR_LOCK			(0x0400)
+#define MCFCFM_MCR_PVIE			(0x0200)
+#define MCFCFM_MCR_AEIE			(0x0100)
+#define MCFCFM_MCR_CBEIE		(0x0080)
+#define MCFCFM_MCR_CCIE			(0x0040)
+#define MCFCFM_MCR_KEYACC		(0x0020)
+
+#define MCFCFM_CLKD			(*(vu_char *)(CFG_MBAR+0x1D0002))
+
+#define MCFCFM_SEC			(*(vu_long*) (CFG_MBAR+0x1D0008))
+#define MCFCFM_SEC_KEYEN		(0x80000000)
+#define MCFCFM_SEC_SECSTAT		(0x40000000)
+
+#define MCFCFM_PROT			(*(vu_long*) (CFG_MBAR+0x1D0010))
+#define MCFCFM_SACC			(*(vu_long*) (CFG_MBAR+0x1D0014))
+#define MCFCFM_DACC			(*(vu_long*) (CFG_MBAR+0x1D0018))
+#define MCFCFM_USTAT			(*(vu_char*) (CFG_MBAR+0x1D0020))
+#define MCFCFM_USTAT_CBEIF		0x80
+#define MCFCFM_USTAT_CCIF		0x40
+#define MCFCFM_USTAT_PVIOL		0x20
+#define MCFCFM_USTAT_ACCERR		0x10
+#define MCFCFM_USTAT_BLANK		0x04
+
+#define MCFCFM_CMD			(*(vu_char*) (CFG_MBAR+0x1D0024))
+#define MCFCFM_CMD_ERSVER		0x05
+#define MCFCFM_CMD_PGERSVER		0x06
+#define MCFCFM_CMD_PGM			0x20
+#define MCFCFM_CMD_PGERS		0x40
+#define MCFCFM_CMD_MASERS		0x41
 
 /****************************************************************************/
 #endif	/* m5282_h */

include/asm-nios2/io.h

@@ -39,12 +39,13 @@ extern unsigned inl (unsigned port);
 #define readl(addr)\
 	({unsigned long val;\
 	 asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
+
 #define writeb(addr,val)\
-	asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val))
+	asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val))
 #define writew(addr,val)\
-	asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val))
+	asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val))
 #define writel(addr,val)\
-	asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val))
+	asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val))
 
 #define inb(addr)	readb(addr)
 #define inw(addr)	readw(addr)

include/configs/EB+MCF-EV123.h

@@ -0,0 +1,223 @@
+/*
+ * Configuation settings for the BuS EB+MCF-EV123 boards.
+ *
+ * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CONFIG_EB_MCF_EV123_H_
+#define _CONFIG_EB_MCF_EV123_H_
+
+#define  CONFIG_EB_MCF_EV123
+
+#undef DEBUG
+#undef CFG_HALT_BEFOR_RAM_JUMP
+#undef ET_DEBUG
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define	CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5282			/* define processor type */
+
+#define CONFIG_MISC_INIT_R
+
+#define FEC_ENET
+#define CONFIG_ETHADDR 00:CF:52:82:EB:01
+
+#define CONFIG_BAUDRATE 9600
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
+
+#define CONFIG_BOOTCOMMAND "printenv"
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_ADDR		0xF003C000	/* End of 256K */
+#define CFG_ENV_SECT_SIZE	0x4000
+#define CFG_ENV_IS_IN_FLASH	1
+/*
+#define CFG_ENV_IS_EMBEDDED	1
+#define CFG_ENV_ADDR_REDUND		0xF0018000
+#define CFG_ENV_SECT_SIZE_REDUND	0x4000
+*/
+#else
+#define CFG_ENV_ADDR		0xFFE04000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#endif
+
+/*#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */
+#define CONFIG_COMMANDS  ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	5
+#define CFG_PROMPT		"\nEV123 U-Boot> "
+#define	CFG_LONGHELP				/* undef to save memory		*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_LOAD_ADDR		0x20000
+
+#define CFG_MEMTEST_START	0x100000
+#define CFG_MEMTEST_END		0x400000
+/*#define CFG_DRAM_TEST		1 */
+#undef CFG_DRAM_TEST
+
+/* Clock and PLL Configuration */
+#define CFG_HZ			10000000
+#define	CFG_CLK			58982400       /* 9,8304MHz * 6 */
+
+/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
+
+#define CFG_MFD			0x01	/* PLL Multiplication Factor Devider */
+#define CFG_RFD			0x00	/* PLL Reduce Frecuency Devider */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define	CFG_MBAR		0x40000000
+
+#define	CFG_DISCOVER_PHY
+/* #define	CFG_ENET_BD_BASE	0x380000 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR       0x20000000
+#define CFG_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
+#define CFG_GBL_DATA_SIZE	64      	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE1		0x00000000
+#define	CFG_SDRAM_SIZE1		16		/* SDRAM size in MB */
+
+/*
+#define CFG_SDRAM_BASE0		CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
+#define	CFG_SDRAM_SIZE0		16	*/	/* SDRAM size in MB */
+
+#define CFG_SDRAM_BASE		CFG_SDRAM_BASE1
+#define	CFG_SDRAM_SIZE		CFG_SDRAM_SIZE1
+
+#define CFG_FLASH_BASE		0xFFE00000
+#define	CFG_INT_FLASH_BASE	0xF0000000
+
+/* If M5282 port is fully implemented the monitor base will be behind
+ * the vector table. */
+#if (TEXT_BASE !=  CFG_INT_FLASH_BASE)
+#define CFG_MONITOR_BASE	(TEXT_BASE + 0x400)
+#else
+#define CFG_MONITOR_BASE	(TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
+#endif
+
+#define CFG_MONITOR_LEN		0x20000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define	CFG_MAX_FLASH_SECT	35
+#define	CFG_MAX_FLASH_BANKS	2
+#define	CFG_FLASH_ERASE_TOUT	10000000
+#define	CFG_FLASH_PROTECTION
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+#define CFG_CS0_BASE		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		2*1024*1024
+#define CFG_CS0_WIDTH		16
+#define CFG_CS0_RO 		0
+#define CFG_CS0_WS		6
+
+#define CFG_CS3_BASE		0xE0000000
+#define CFG_CS3_SIZE		1*1024*1024
+#define CFG_CS3_WIDTH		16
+#define CFG_CS3_RO 		0
+#define CFG_CS3_WS		6
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_PACNT		0x0000000	/* Port A D[31:24] */
+#define CFG_PADDR		0x0000000
+#define CFG_PADAT		0x0000000
+
+#define CFG_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CFG_PBDDR		0x0000000
+#define CFG_PBDAT		0x0000000
+
+#define CFG_PCCNT		0x0000000	/* Port C D[15:08] */
+#define CFG_PCDDR		0x0000000
+#define CFG_PCDAT		0x0000000
+
+#define CFG_PDCNT		0x0000000	/* Port D D[07:00] */
+#define CFG_PCDDR		0x0000000
+#define CFG_PCDAT		0x0000000
+
+#define CFG_PEHLPAR		0xC0
+#define CFG_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
+#define CFG_DDRUA		0x05
+#define CFG_PJPAR 		0xFF;
+
+/*-----------------------------------------------------------------------
+ * CCM configuration
+ */
+
+#define	CFG_CCM_SIZ		0
+
+/*---------------------------------------------------------------------*/
+#endif	/* _CONFIG_M5282EVB_H */
+/*---------------------------------------------------------------------*/

include/configs/EP1C20.h

@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_EP1C20		1		/* EP1C20 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR	(CFG_RESET_ADDR + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
+ * epcs device access is enabled. The base address is the epcs
+ * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
+ * The register base is currently at offset 0x600 from the memory base.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- leds are, after all,
+ * board-specific, no?
+ *----------------------------------------------------------------------*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
+#define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP				/* Provide extended help*/
+#define CFG_PROMPT		"==> "		/* Command prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O buf size */
+#define CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_H */

include/configs/EP1S10.h

@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_EP1S10		1		/* EP1S10 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB			*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 256*1024) /* 256k heap */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
+ * of flash memory. This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- None for stratix.
+ *----------------------------------------------------------------------*/
+#undef CFG_NIOS_EPCSBASE
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- since leds are board-specific.
+ *----------------------------------------------------------------------*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
+#define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP				/* Provide extended help*/
+#define CFG_PROMPT		"==> "		/* Command prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O buf size */
+#define CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_H */

include/configs/EP1S40.h

@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_EP1S40		1		/* EP1S40 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CFG_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CFG_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CFG_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CFG_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CFG_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB			*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
+#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 256*1024) /* 256k heap */
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
+#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
+ * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
+ * of flash memory. This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CONSOLE_JTAG)
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#else
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#endif
+
+#define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CFG_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- None for stratix.
+ *----------------------------------------------------------------------*/
+#undef CFG_NIOS_EPCSBASE
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, we can slow it down to 10 msec using TMRCNT. If the default
+ * period is acceptable, TMRCNT can be left undefined.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
+#define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
+#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+#define CFG_HZ		(CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- since leds are board-specific.
+ *----------------------------------------------------------------------*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CFG_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
+#define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+/*------------------------------------------------------------------------
+ * COMMANDS
+ *----------------------------------------------------------------------*/
+#define CONFIG_COMMANDS		(CFG_CMD_BDI	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_ECHO	| \
+				 CFG_CMD_ENV	| \
+				 CFG_CMD_FLASH	| \
+				 CFG_CMD_IMI	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_LOADS	| \
+				 CFG_CMD_LOADB	| \
+				 CFG_CMD_MEMORY | \
+				 CFG_CMD_MISC	| \
+				 CFG_CMD_NET	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_RUN	| \
+				 CFG_CMD_SAVES	)
+#include <cmd_confdefs.h>
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CFG_LONGHELP				/* Provide extended help*/
+#define CFG_PROMPT		"==> "		/* Command prompt	*/
+#define CFG_CBSIZE		256		/* Console I/O buf size */
+#define CFG_MAXARGS		16		/* Max command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot arg buf size	*/
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
+#define CFG_LOAD_ADDR		CFG_SDRAM_BASE	/* Default load address */
+#define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
+#define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
+
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_H */

include/configs/PK1C20.h

@@ -32,7 +32,7 @@
 
 #define CFG_RESET_ADDR		0x00000000	/* Hard-reset address	*/
 #define CFG_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CFG_NIOS_SYSID_BASE	0x00920828	/* System id address	*/
+#define CFG_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
 
 /*------------------------------------------------------------------------
@@ -51,7 +51,7 @@
 #define CFG_FLASH_SIZE		0x00800000	/* 8 MByte		*/
 #define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
 #define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
-#define CFG_SRAM_BASE		0x00800000	/* SRAM base addr	*/
+#define CFG_SRAM_BASE		0x02000000	/* SRAM base addr	*/
 #define CFG_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
 
 /*------------------------------------------------------------------------
@@ -61,7 +61,7 @@
  *	-Global data is placed below the heap.
  *	-The stack is placed below global data (&grows down).
  *----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
 #define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/
 #define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
 
@@ -95,9 +95,9 @@
  * CONSOLE
  *----------------------------------------------------------------------*/
 #if defined(CONFIG_CONSOLE_JTAG)
-#define CFG_NIOS_CONSOLE	0x00920820	/* JTAG UART base addr	*/
+#define CFG_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
 #else
-#define CFG_NIOS_CONSOLE	0x009208a0	/* UART base addr	*/
+#define CFG_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
 #endif
 
 #define CFG_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
@@ -110,9 +110,9 @@
  * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
  * epcs device access is enabled. The base address is the epcs
  * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
- * The register base is currently at offset 0x400 from the memory base.
+ * The register base is currently at offset 0x600 from the memory base.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_EPCSBASE	0x00900400	/* EPCS register base	*/
+#define CFG_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
 
 /*------------------------------------------------------------------------
  * DEBUG
@@ -126,7 +126,7 @@
  * registers, we can slow it down to 10 msec using TMRCNT. If the default
  * period is acceptable, TMRCNT can be left undefined.
  *----------------------------------------------------------------------*/
-#define CFG_NIOS_TMRBASE	0x00920860	/* Tick timer base addr */
+#define CFG_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
 #define CFG_NIOS_TMRIRQ		3		/* Timer IRQ num	*/
 #define CFG_NIOS_TMRMS		10		/* 10 msec per tick	*/
 #define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
@@ -137,7 +137,7 @@
  * must implement its own led routines -- leds are, after all,
  * board-specific, no?
  *----------------------------------------------------------------------*/
-#define CFG_LEDPIO_ADDR		0x00920840	/* LED PIO base addr	*/
+#define CFG_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
 #define CONFIG_STATUS_LED			/* Enable status driver */
 
 #define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
@@ -150,7 +150,7 @@
  * way out to avoid changes there -- define the base address to ensure
  * cache bypass so there's no need to monkey with inx/outx macros.
  *----------------------------------------------------------------------*/
-#define CONFIG_SMC91111_BASE	0x80910300	/* Base addr (bypass)	*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
 #define CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/
 #undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
 #define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/

include/configs/pcs440ep.h

@@ -0,0 +1,412 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************************************
+ * pcs440ep.h - configuration for PCS440EP board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_PCS440EP		1	/* Board is PCS440EP            */
+#define CONFIG_440EP		1	/* Specific PPC440EP support    */
+#define CONFIG_4xx		1	/* ... PPC4xx family	        */
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CFG_MONITOR_BASE	(-CFG_MONITOR_LEN)
+#define CFG_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
+#define CFG_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
+#define CFG_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
+#define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CFG_PERIPHERAL_BASE     0xef600000	    /* internal peripherals*/
+#define CFG_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CFG_USB_DEVICE          0x50000000
+#define CFG_BOOT_BASE_ADDR      0xf0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CFG_INIT_RAM_END	(8 << 10)
+#define CFG_GBL_DATA_SIZE	256			/* num bytes initial data*/
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#undef CFG_EXT_SERIAL_CLOCK		/* no external clk used		*/
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SERIAL_MULTI     1
+/*define this if you want console on UART1*/
+#undef CONFIG_UART1_CONSOLE
+
+#define CFG_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE	0x10000 	/* size of one complete sector	*/
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
+#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
+#undef CONFIG_DDR_ECC			/* don't use ECC			*/
+#define SPD_EEPROM_ADDRESS      {0x50}
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C		1	    /* I2C with hardware support	*/
+#undef	CONFIG_SOFT_I2C			    /* I2C bit-banged		*/
+#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CFG_I2C_SLAVE		0x7F
+
+#define CFG_I2C_EEPROM_ADDR	(0xa4>>1)
+#define CFG_I2C_EEPROM_ADDR_LEN 1
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+#define CFG_EEPROM_PAGE_WRITE_BITS 3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=pcs440ep\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+	        "bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/pcs440ep/uImage\0"				\
+	"kernel_addr=FFF00000\0"					\
+	"ramdisk_addr=FFF00000\0"					\
+	"load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0"		\
+	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
+		"cp.b 100000 FFFA0000 60000\0"			        \
+	"upd=run load;run update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_NET_MULTI        1	/* required for netconsole      */
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR        2
+
+#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG			/* watchdog */
+#endif
+
+#define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_DIAG	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_ELF	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_IRQ	| \
+				CFG_CMD_MII	| \
+				CFG_CMD_NET	| \
+				CFG_CMD_NFS	| \
+				CFG_CMD_PCI	| \
+				CFG_CMD_PING	| \
+				CFG_CMD_REGINFO	| \
+				CFG_CMD_SDRAM	| \
+				CFG_CMD_EXT2	| \
+				CFG_CMD_FAT	| \
+				CFG_CMD_USB	)
+
+
+#define CONFIG_SUPPORT_VFAT
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory		*/
+#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS	        16	/* max number of command args	*/
+#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI          1       /* support kdi files            */
+
+#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
+#define CFG_PCI_TARGET_INIT
+#define CFG_PCI_MASTER_INIT
+
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFF80000	/* FLASH bank #1	*/
+
+#define CFG_FLASH		FLASH_BASE0_PRELIM
+#define CFG_SRAM		0xF1000000
+#define CFG_FPGA		0xF2000000
+#define CFG_CF1			0xF0000000
+#define CFG_CF2			0xF0100000
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CFG_EBC_PB0AP		0x02010000	/* TWT=4,OEN=1			*/
+#define CFG_EBC_PB0CR		(CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 1 (SRAM) initialization						*/
+#define CFG_EBC_PB1AP		0x01810040	/* TWT=3,OEN=1,BEM=1		*/
+#define CFG_EBC_PB1CR		(CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 2 (FPGA) initialization						*/
+#define CFG_EBC_PB2AP		0x01010440	/* TWT=2,OEN=1,TH=2,BEM=1	*/
+#define CFG_EBC_PB2CR		(CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 3 (CompactFlash) initialization					*/
+#define CFG_EBC_PB3AP		0x080BD400
+#define CFG_EBC_PB3CR		(CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 4 (CompactFlash) initialization					*/
+#define CFG_EBC_PB4AP		0x080BD400
+#define CFG_EBC_PB4CR		(CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
+
+/*-----------------------------------------------------------------------
+ * PPC440 GPIO Configuration
+ */
+#define CFG_440_GPIO_TABLE { /*		GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6	EBC_CS_N(1)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7	EBC_CS_N(2)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8	EBC_CS_N(3)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9	EBC_CS_N(4)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO10	EBC_CS_N(5)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO11	EBC_BUS_ERR			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO12	ZII_p0Rxd(0)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO13	ZII_p0Rxd(1)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO14	ZII_p0Rxd(2)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO15	ZII_p0Rxd(3)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16	ZII_p0Txd(0)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17	ZII_p0Txd(1)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18	ZII_p0Txd(2)			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19	ZII_p0Txd(3)			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO20	ZII_p0Rx_er			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO21	ZII_p0Rx_dv			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO22	ZII_p0RxCrs			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23	ZII_p0Tx_er			*/	\
+{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24	ZII_p0Tx_en			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO25	ZII_p0Col			*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO26			USB2D_RXVALID	*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO27	EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO28			USB2D_TXVALID	*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO29	EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO30	EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{ GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO31	EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+},											\
+{											\
+/* GPIO Core 1 */									\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO32	USB2D_OPMODE0			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO33	USB2D_OPMODE1			*/	\
+{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34	UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT3 }, /* GPIO35	UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO36	UART0_8PIN_CTS_N		UART3_SIN*/ \
+{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37	UART0_RTS_N			*/	\
+{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38	UART0_DTR_N	UART1_SOUT	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT2 }, /* GPIO39	UART0_RI_N	UART1_SIN	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO40	UIC_IRQ(0)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO41	UIC_IRQ(1)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO42	UIC_IRQ(2)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO43	UIC_IRQ(3)			*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO44	UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO45	UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{ GPIO1_BASE, GPIO_BI,  GPIO_SEL },  /* GPIO46	UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO47	UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO48	UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{ GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		(32<<10) /* For AMCC 440 CPUs			*/
+#define CFG_CACHELINE_SIZE	32	/* ...			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+#endif	/* __CONFIG_H */

include/nios2-epcs.h

@@ -38,6 +38,11 @@ typedef struct epcs_devinfo_t {
 	unsigned char   prot_mask;	/* Protection mask */
 }epcs_devinfo_t;
 
+/* Resets the epcs controller -- to prevent (potential) soft-reset
+ * problems when booting from the epcs controller
+ */
+extern int epcs_reset (void);
+
 /* Returns the devinfo struct if EPCS device is found;
  * NULL otherwise.
  */

include/ppc440.h

@@ -1357,56 +1357,106 @@
 /******************************************************************************
  * GPIO macro register defines
  ******************************************************************************/
-#if defined(CONFIG_440GP)
-#define GPIO_BASE0             (CFG_PERIPHERAL_BASE+0x00000700)
+#define GPIO0			0
+#define GPIO1			1
 
-#define GPIO0_OR               (GPIO_BASE0+0x0)
-#define GPIO0_TCR              (GPIO_BASE0+0x4)
-#define GPIO0_ODR              (GPIO_BASE0+0x18)
-#define GPIO0_IR               (GPIO_BASE0+0x1C)
+#if defined(CONFIG_440GP)
+#define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000700)
+
+#define GPIO0_OR               (GPIO0_BASE+0x0)
+#define GPIO0_TCR              (GPIO0_BASE+0x4)
+#define GPIO0_ODR              (GPIO0_BASE+0x18)
+#define GPIO0_IR               (GPIO0_BASE+0x1C)
 #endif /* CONFIG_440GP */
 
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
-#define GPIO_BASE0             (CFG_PERIPHERAL_BASE+0x00000B00)
-#define GPIO_BASE1             (CFG_PERIPHERAL_BASE+0x00000C00)
+#define GPIO0_BASE             (CFG_PERIPHERAL_BASE+0x00000B00)
+#define GPIO1_BASE             (CFG_PERIPHERAL_BASE+0x00000C00)
 
-#define GPIO0_OR               (GPIO_BASE0+0x0)
-#define GPIO0_TCR              (GPIO_BASE0+0x4)
-#define GPIO0_OSRL             (GPIO_BASE0+0x8)
-#define GPIO0_OSRH             (GPIO_BASE0+0xC)
-#define GPIO0_TSRL             (GPIO_BASE0+0x10)
-#define GPIO0_TSRH             (GPIO_BASE0+0x14)
-#define GPIO0_ODR              (GPIO_BASE0+0x18)
-#define GPIO0_IR               (GPIO_BASE0+0x1C)
-#define GPIO0_RR1              (GPIO_BASE0+0x20)
-#define GPIO0_RR2              (GPIO_BASE0+0x24)
-#define GPIO0_RR3	       (GPIO_BASE0+0x28)
-#define GPIO0_ISR1L            (GPIO_BASE0+0x30)
-#define GPIO0_ISR1H            (GPIO_BASE0+0x34)
-#define GPIO0_ISR2L            (GPIO_BASE0+0x38)
-#define GPIO0_ISR2H            (GPIO_BASE0+0x3C)
-#define GPIO0_ISR3L            (GPIO_BASE0+0x40)
-#define GPIO0_ISR3H            (GPIO_BASE0+0x44)
+/* Offsets */
+#define GPIOx_OR    0x00	/* GPIO Output Register */
+#define GPIOx_TCR   0x04	/* GPIO Three-State Control Register */
+#define GPIOx_OSL   0x08	/* GPIO Output Select Register (Bits 0-31) */
+#define GPIOx_OSH   0x0C	/* GPIO Ouput Select Register (Bits 32-63) */
+#define GPIOx_TSL   0x10	/* GPIO Three-State Select Register (Bits 0-31) */
+#define GPIOx_TSH   0x14	/* GPIO Three-State Select Register  (Bits 32-63) */
+#define GPIOx_ODR   0x18	/* GPIO Open drain Register */
+#define GPIOx_IR    0x1C	/* GPIO Input Register */
+#define GPIOx_RR1   0x20	/* GPIO Receive Register 1 */
+#define GPIOx_RR2   0x24	/* GPIO Receive Register 2 */
+#define GPIOx_RR3   0x28	/* GPIO Receive Register 3 */
+#define GPIOx_IS1L  0x30	/* GPIO Input Select Register 1 (Bits 0-31) */
+#define GPIOx_IS1H  0x34	/* GPIO Input Select Register 1 (Bits 32-63) */
+#define GPIOx_IS2L  0x38	/* GPIO Input Select Register 2 (Bits 0-31) */
+#define GPIOx_IS2H  0x3C	/* GPIO Input Select Register 2 (Bits 32-63) */
+#define GPIOx_IS3L  0x40	/* GPIO Input Select Register 3 (Bits 0-31) */
+#define GPIOx_IS3H  0x44	/* GPIO Input Select Register 3 (Bits 32-63) */
 
-#define GPIO1_OR               (GPIO_BASE1+0x0)
-#define GPIO1_TCR              (GPIO_BASE1+0x4)
-#define GPIO1_OSRL             (GPIO_BASE1+0x8)
-#define GPIO1_OSRH             (GPIO_BASE1+0xC)
-#define GPIO1_TSRL             (GPIO_BASE1+0x10)
-#define GPIO1_TSRH             (GPIO_BASE1+0x14)
-#define GPIO1_ODR              (GPIO_BASE1+0x18)
-#define GPIO1_IR               (GPIO_BASE1+0x1C)
-#define GPIO1_RR1              (GPIO_BASE1+0x20)
-#define GPIO1_RR2              (GPIO_BASE1+0x24)
-#define GPIO1_RR3              (GPIO_BASE1+0x28)
-#define GPIO1_ISR1L            (GPIO_BASE1+0x30)
-#define GPIO1_ISR1H            (GPIO_BASE1+0x34)
-#define GPIO1_ISR2L            (GPIO_BASE1+0x38)
-#define GPIO1_ISR2H            (GPIO_BASE1+0x3C)
-#define GPIO1_ISR3L            (GPIO_BASE1+0x40)
-#define GPIO1_ISR3H            (GPIO_BASE1+0x44)
+#define GPIO_OS(x)	(x+GPIOx_OSL)	/* GPIO Output Register High or Low */
+#define GPIO_TS(x)	(x+GPIOx_TSL)	/* GPIO Three-state Control Reg High or Low */
+#define GPIO_IS1(x)	(x+GPIOx_IS1L)	/* GPIO Input register1 High or Low */
+#define GPIO_IS2(x)	(x+GPIOx_IS2L)	/* GPIO Input register2 High or Low */
+#define GPIO_IS3(x)	(x+GPIOx_IS3L)	/* GPIO Input register3 High or Low */
+
+#define GPIO0_OR               (GPIO0_BASE+0x0)
+#define GPIO0_TCR              (GPIO0_BASE+0x4)
+#define GPIO0_OSRL             (GPIO0_BASE+0x8)
+#define GPIO0_OSRH             (GPIO0_BASE+0xC)
+#define GPIO0_TSRL             (GPIO0_BASE+0x10)
+#define GPIO0_TSRH             (GPIO0_BASE+0x14)
+#define GPIO0_ODR              (GPIO0_BASE+0x18)
+#define GPIO0_IR               (GPIO0_BASE+0x1C)
+#define GPIO0_RR1              (GPIO0_BASE+0x20)
+#define GPIO0_RR2              (GPIO0_BASE+0x24)
+#define GPIO0_RR3	       (GPIO0_BASE+0x28)
+#define GPIO0_ISR1L            (GPIO0_BASE+0x30)
+#define GPIO0_ISR1H            (GPIO0_BASE+0x34)
+#define GPIO0_ISR2L            (GPIO0_BASE+0x38)
+#define GPIO0_ISR2H            (GPIO0_BASE+0x3C)
+#define GPIO0_ISR3L            (GPIO0_BASE+0x40)
+#define GPIO0_ISR3H            (GPIO0_BASE+0x44)
+
+#define GPIO1_OR               (GPIO1_BASE+0x0)
+#define GPIO1_TCR              (GPIO1_BASE+0x4)
+#define GPIO1_OSRL             (GPIO1_BASE+0x8)
+#define GPIO1_OSRH             (GPIO1_BASE+0xC)
+#define GPIO1_TSRL             (GPIO1_BASE+0x10)
+#define GPIO1_TSRH             (GPIO1_BASE+0x14)
+#define GPIO1_ODR              (GPIO1_BASE+0x18)
+#define GPIO1_IR               (GPIO1_BASE+0x1C)
+#define GPIO1_RR1              (GPIO1_BASE+0x20)
+#define GPIO1_RR2              (GPIO1_BASE+0x24)
+#define GPIO1_RR3              (GPIO1_BASE+0x28)
+#define GPIO1_ISR1L            (GPIO1_BASE+0x30)
+#define GPIO1_ISR1H            (GPIO1_BASE+0x34)
+#define GPIO1_ISR2L            (GPIO1_BASE+0x38)
+#define GPIO1_ISR2H            (GPIO1_BASE+0x3C)
+#define GPIO1_ISR3L            (GPIO1_BASE+0x40)
+#define GPIO1_ISR3H            (GPIO1_BASE+0x44)
 #endif
 
+#define GPIO_GROUP_MAX	    2
+#define GPIO_MAX	    32
+#define GPIO_ALT1_SEL	    0x40000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
+#define GPIO_ALT2_SEL	    0x80000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
+#define GPIO_ALT3_SEL	    0xC0000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
+#define GPIO_MASK	    0xC0000000	    /* GPIO_MASK */
+#define GPIO_IN_SEL	    0x40000000	    /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
+					    /* For the other GPIO number, you must shift */
+
+#ifndef __ASSEMBLY__
+
+typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
+typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
+
+typedef struct { unsigned long	add;	/* gpio core base address */
+	gpio_driver_t  in_out; /* Driver Setting */
+	gpio_select_t  alt_nb; /* Selected Alternate */
+} gpio_param_s;
+
+
+#endif /* __ASSEMBLY__ */
+
 /*
  * Macros for accessing the indirect EBC registers
  */

lib_nios2/board.c

@@ -31,6 +31,9 @@
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
 #endif
+#if defined(CFG_NIOS_EPCSBASE)
+#include <nios2-epcs.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -93,6 +96,9 @@ init_fnc_t *init_sequence[] = {
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 	board_early_init_f,	/* Call board-specific init code early.*/
 #endif
+#if defined(CFG_NIOS_EPCSBASE)
+	epcs_reset,
+#endif
 
 	env_init,
 	serial_init,
@@ -165,6 +171,10 @@ void board_init (void)
 	WATCHDOG_RESET ();
 	interrupt_init ();
 
+#if defined(CONFIG_BOARD_LATE_INIT)
+	board_late_init ();
+#endif
+
 	/* main_loop */
 	for (;;) {
 		WATCHDOG_RESET ();

nios2_config.mk

@@ -23,4 +23,4 @@
 #
 
 PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__
-PLATFORM_CPPFLAGS += -ffixed-r15
+PLATFORM_CPPFLAGS += -ffixed-r15 -G0