2011-04-13 13:37:44 +00:00
|
|
|
#
|
|
|
|
# Copyright 2009-2011 Freescale Semiconductor, Inc.
|
|
|
|
#
|
2013-07-08 07:37:19 +00:00
|
|
|
# SPDX-License-Identifier: GPL-2.0+
|
2011-04-13 13:37:44 +00:00
|
|
|
#
|
|
|
|
|
|
|
|
include $(TOPDIR)/config.mk
|
|
|
|
|
|
|
|
LIB := $(obj)libfm.o
|
|
|
|
|
|
|
|
ifdef CONFIG_FMAN_ENET
|
|
|
|
COBJS-y += dtsec.o
|
|
|
|
COBJS-y += eth.o
|
|
|
|
COBJS-y += fm.o
|
|
|
|
COBJS-y += init.o
|
|
|
|
COBJS-y += tgec.o
|
|
|
|
COBJS-y += tgec_phy.o
|
|
|
|
|
2012-10-08 07:44:21 +00:00
|
|
|
# Soc have FMAN v3 with mEMAC
|
|
|
|
COBJS-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
|
|
|
|
COBJS-$(CONFIG_SYS_FMAN_V3) += memac.o
|
|
|
|
|
2011-04-13 13:37:44 +00:00
|
|
|
# SoC specific SERDES support
|
|
|
|
COBJS-$(CONFIG_P1017) += p1023.o
|
|
|
|
COBJS-$(CONFIG_P1023) += p1023.o
|
|
|
|
# The P204x, P304x, and P5020 are the same
|
|
|
|
COBJS-$(CONFIG_PPC_P2041) += p5020.o
|
|
|
|
COBJS-$(CONFIG_PPC_P3041) += p5020.o
|
|
|
|
COBJS-$(CONFIG_PPC_P4080) += p4080.o
|
|
|
|
COBJS-$(CONFIG_PPC_P5020) += p5020.o
|
2012-10-23 09:40:22 +00:00
|
|
|
COBJS-$(CONFIG_PPC_P5040) += p5040.o
|
powerpc/t1040qds: Add T1040QDS board
T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.
T1040QDS board Overview
-----------------------
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch
- Four 1 Gbps Ethernet controllers
- SERDES Connections, 8 lanes supporting:
— PCI Express: supporting Gen 1 and Gen 2;
— SGMII
— QSGMII
— SATA 2.0
— Aurora debug with dedicated connectors
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 8-bit, async, up to 2GB.
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- GASIC: Simple (minimal) target within Qixis FPGA
- PromJET rapid memory download support
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- QIXIS System Logic FPGA
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- Video
- DIU supports video at up to 1280x1024x32bpp
- USB
- Supports two USB 2.0 ports with integrated PHYs
— Two type A ports with 5V@1.5A per port.
— Second port can be converted to OTG mini-AB
- SDHC
- SDHC port connects directly to an adapter card slot, featuring:
- Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
— Supporting eMMC memory devices
- SPI
- On-board support of 3 different devices and sizes
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: York Sun <yorksun@freescale.com>
2013-09-12 05:41:28 +00:00
|
|
|
COBJS-$(CONFIG_PPC_T1040) += t1040.o
|
2012-10-08 07:44:19 +00:00
|
|
|
COBJS-$(CONFIG_PPC_T4240) += t4240.o
|
2013-03-25 07:33:29 +00:00
|
|
|
COBJS-$(CONFIG_PPC_T4160) += t4240.o
|
2012-12-23 19:24:16 +00:00
|
|
|
COBJS-$(CONFIG_PPC_B4420) += b4860.o
|
powerpc/mpc85xx: Add B4860 and variant SoCs
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):
Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:20 +00:00
|
|
|
COBJS-$(CONFIG_PPC_B4860) += b4860.o
|
2011-04-13 13:37:44 +00:00
|
|
|
endif
|
|
|
|
|
|
|
|
COBJS := $(COBJS-y)
|
|
|
|
SRCS := $(COBJS:.o=.c)
|
|
|
|
OBJS := $(addprefix $(obj),$(COBJS))
|
|
|
|
|
|
|
|
all: $(LIB)
|
|
|
|
|
|
|
|
$(LIB): $(obj).depend $(OBJS)
|
|
|
|
$(call cmd_link_o_target, $(OBJS))
|
|
|
|
|
|
|
|
#########################################################################
|
|
|
|
|
|
|
|
include $(SRCTREE)/rules.mk
|
|
|
|
|
|
|
|
sinclude $(obj).depend
|
|
|
|
|
|
|
|
#########################################################################
|