2009-09-07 07:08:02 +00:00
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/*
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* (C) Copyright 2007-2009 Michal Simek
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* (C) Copyright 2003 Xilinx Inc.
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2008-03-28 11:41:56 +00:00
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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2013-10-07 11:07:26 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2009-09-07 07:08:02 +00:00
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*/
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2008-03-28 11:41:56 +00:00
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#include <common.h>
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#include <net.h>
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#include <config.h>
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2015-12-10 12:33:20 +00:00
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#include <console.h>
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2010-10-11 01:41:47 +00:00
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#include <malloc.h>
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2008-03-28 11:41:56 +00:00
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#include <asm/io.h>
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2015-12-10 12:33:20 +00:00
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#include <phy.h>
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#include <miiphy.h>
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2012-06-28 21:37:57 +00:00
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#include <fdtdec.h>
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2015-12-10 12:33:20 +00:00
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#include <asm-generic/errno.h>
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2012-06-28 21:37:57 +00:00
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2008-03-28 11:41:56 +00:00
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#undef DEBUG
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#define ENET_ADDR_LENGTH 6
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/* EmacLite constants */
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#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
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#define XEL_RSR_OFFSET 0x17FC /* Rx status */
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#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
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/* Xmit complete */
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#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
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/* Xmit interrupt enable bit */
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#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
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/* Program the MAC address */
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#define XEL_TSR_PROGRAM_MASK 0x00000002UL
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/* define for programming the MAC address into the EMAC Lite */
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#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
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/* Transmit packet length upper byte */
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#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
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/* Transmit packet length lower byte */
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#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
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/* Recv complete */
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#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
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/* Recv interrupt enable bit */
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#define XEL_RSR_RECV_IE_MASK 0x00000008UL
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2015-12-10 12:33:20 +00:00
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/* MDIO Address Register Bit Masks */
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#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
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#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
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#define XEL_MDIOADDR_PHYADR_SHIFT 5
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#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
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/* MDIO Write Data Register Bit Masks */
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#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
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/* MDIO Read Data Register Bit Masks */
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#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
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/* MDIO Control Register Bit Masks */
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#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
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#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
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2015-12-10 13:18:15 +00:00
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struct emaclite_regs {
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u32 tx_ping; /* 0x0 - TX Ping buffer */
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u32 reserved1[504];
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u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
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u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
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u32 mdiord;/* 0x7ec - MDIO Read Data Register */
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u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
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u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
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u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
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u32 tx_ping_tsr; /* 0x7fc - Tx status */
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u32 tx_pong; /* 0x800 - TX Pong buffer */
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u32 reserved2[508];
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u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
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u32 reserved3; /* 0xff8 */
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u32 tx_pong_tsr; /* 0xffc - Tx status */
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u32 rx_ping; /* 0x1000 - Receive Buffer */
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u32 reserved4[510];
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u32 rx_ping_rsr; /* 0x17fc - Rx status */
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u32 rx_pong; /* 0x1800 - Receive Buffer */
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u32 reserved5[510];
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u32 rx_pong_rsr; /* 0x1ffc - Rx status */
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};
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2011-08-25 10:47:56 +00:00
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struct xemaclite {
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2010-10-11 01:41:47 +00:00
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u32 nextrxbuffertouse; /* Next RX buffer to read from */
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2011-09-12 21:10:01 +00:00
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u32 txpp; /* TX ping pong buffer */
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u32 rxpp; /* RX ping pong buffer */
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2015-12-10 12:33:20 +00:00
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int phyaddr;
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2015-12-10 13:18:15 +00:00
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struct emaclite_regs *regs;
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2015-12-10 12:33:20 +00:00
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struct phy_device *phydev;
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struct mii_dev *bus;
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2011-08-25 10:47:56 +00:00
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};
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2008-03-28 11:41:56 +00:00
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2008-10-27 15:05:00 +00:00
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static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
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2008-03-28 11:41:56 +00:00
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2011-09-12 21:10:05 +00:00
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static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
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2008-03-28 11:41:56 +00:00
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{
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2010-10-11 01:41:47 +00:00
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u32 i;
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2008-03-28 11:41:56 +00:00
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u32 alignbuffer;
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u32 *to32ptr;
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u32 *from32ptr;
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u8 *to8ptr;
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u8 *from8ptr;
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from32ptr = (u32 *) srcptr;
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/* Word aligned buffer, no correction needed. */
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to32ptr = (u32 *) destptr;
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while (bytecount > 3) {
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*to32ptr++ = *from32ptr++;
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bytecount -= 4;
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}
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to8ptr = (u8 *) to32ptr;
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alignbuffer = *from32ptr++;
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2011-09-12 21:10:05 +00:00
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from8ptr = (u8 *) &alignbuffer;
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2008-03-28 11:41:56 +00:00
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2011-09-12 21:10:05 +00:00
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for (i = 0; i < bytecount; i++)
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2008-03-28 11:41:56 +00:00
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*to8ptr++ = *from8ptr++;
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}
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2015-12-10 15:01:50 +00:00
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static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
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2008-03-28 11:41:56 +00:00
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{
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2010-10-11 01:41:47 +00:00
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u32 i;
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2008-03-28 11:41:56 +00:00
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u32 alignbuffer;
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u32 *to32ptr = (u32 *) destptr;
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u32 *from32ptr;
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u8 *to8ptr;
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u8 *from8ptr;
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from32ptr = (u32 *) srcptr;
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while (bytecount > 3) {
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*to32ptr++ = *from32ptr++;
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bytecount -= 4;
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}
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alignbuffer = 0;
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2011-09-12 21:10:05 +00:00
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to8ptr = (u8 *) &alignbuffer;
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2008-03-28 11:41:56 +00:00
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from8ptr = (u8 *) from32ptr;
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2011-09-12 21:10:05 +00:00
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for (i = 0; i < bytecount; i++)
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2008-03-28 11:41:56 +00:00
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*to8ptr++ = *from8ptr++;
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*to32ptr++ = alignbuffer;
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}
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2015-12-10 12:33:20 +00:00
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
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static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
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bool set, unsigned int timeout)
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{
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u32 val;
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unsigned long start = get_timer(0);
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while (1) {
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val = readl(reg);
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if (!set)
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val = ~val;
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if ((val & mask) == mask)
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return 0;
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if (get_timer(start) > timeout)
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break;
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if (ctrlc()) {
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puts("Abort\n");
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return -EINTR;
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}
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udelay(1);
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}
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debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
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func, reg, mask, set);
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return -ETIMEDOUT;
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}
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2015-12-10 13:18:15 +00:00
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static int mdio_wait(struct emaclite_regs *regs)
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2015-12-10 12:33:20 +00:00
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{
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2015-12-10 13:18:15 +00:00
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return wait_for_bit(__func__, ®s->mdioctrl,
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2015-12-10 12:33:20 +00:00
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XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
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}
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2015-12-10 13:18:15 +00:00
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static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
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2015-12-10 12:33:20 +00:00
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u16 *data)
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{
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2015-12-10 13:18:15 +00:00
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struct emaclite_regs *regs = emaclite->regs;
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if (mdio_wait(regs))
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2015-12-10 12:33:20 +00:00
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return 1;
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2015-12-10 13:18:15 +00:00
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u32 ctrl_reg = in_be32(®s->mdioctrl);
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out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK |
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2015-12-10 12:33:20 +00:00
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((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
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2015-12-10 13:18:15 +00:00
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out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
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2015-12-10 12:33:20 +00:00
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2015-12-10 13:18:15 +00:00
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if (mdio_wait(regs))
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2015-12-10 12:33:20 +00:00
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return 1;
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/* Read data */
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2015-12-10 13:18:15 +00:00
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*data = in_be32(®s->mdiord);
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2015-12-10 12:33:20 +00:00
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return 0;
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}
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2015-12-10 13:18:15 +00:00
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static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
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2015-12-10 12:33:20 +00:00
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u16 data)
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{
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2015-12-10 13:18:15 +00:00
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struct emaclite_regs *regs = emaclite->regs;
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if (mdio_wait(regs))
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2015-12-10 12:33:20 +00:00
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return 1;
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/*
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* Write the PHY address, register number and clear the OP bit in the
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* MDIO Address register and then write the value into the MDIO Write
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* Data register. Finally, set the Status bit in the MDIO Control
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* register to start a MDIO write transaction.
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*/
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2015-12-10 13:18:15 +00:00
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u32 ctrl_reg = in_be32(®s->mdioctrl);
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out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
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2015-12-10 12:33:20 +00:00
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((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
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2015-12-10 13:18:15 +00:00
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out_be32(®s->mdiowr, data);
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out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
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2015-12-10 12:33:20 +00:00
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2015-12-10 13:18:15 +00:00
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if (mdio_wait(regs))
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2015-12-10 12:33:20 +00:00
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return 1;
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return 0;
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}
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#endif
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2010-10-11 01:41:47 +00:00
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static void emaclite_halt(struct eth_device *dev)
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2008-03-28 11:41:56 +00:00
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{
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2011-09-12 21:10:05 +00:00
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debug("eth_halt\n");
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2008-03-28 11:41:56 +00:00
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}
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2015-12-10 12:33:20 +00:00
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/* Use MII register 1 (MII status register) to detect PHY */
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#define PHY_DETECT_REG 1
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/* Mask used to verify certain PHY features (or register contents)
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* in the register above:
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* 0x1000: 10Mbps full duplex support
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* 0x0800: 10Mbps half duplex support
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* 0x0008: Auto-negotiation support
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*/
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#define PHY_DETECT_MASK 0x1808
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
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static int setup_phy(struct eth_device *dev)
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{
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int i;
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u16 phyreg;
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struct xemaclite *emaclite = dev->priv;
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struct phy_device *phydev;
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u32 supported = SUPPORTED_10baseT_Half |
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SUPPORTED_10baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full;
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if (emaclite->phyaddr != -1) {
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2015-12-10 13:18:15 +00:00
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phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
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2015-12-10 12:33:20 +00:00
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if ((phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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debug("Default phy address %d is valid\n",
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emaclite->phyaddr);
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} else {
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debug("PHY address is not setup correctly %d\n",
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emaclite->phyaddr);
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emaclite->phyaddr = -1;
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}
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}
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if (emaclite->phyaddr == -1) {
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/* detect the PHY address */
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for (i = 31; i >= 0; i--) {
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2015-12-10 13:18:15 +00:00
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phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
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2015-12-10 12:33:20 +00:00
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if ((phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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emaclite->phyaddr = i;
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debug("emaclite: Found valid phy address, %d\n",
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i);
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break;
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}
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}
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}
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/* interface - look at tsec */
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phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
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PHY_INTERFACE_MODE_MII);
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/*
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* Phy can support 1000baseT but device NOT that's why phydev->supported
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* must be setup for 1000baseT. phydev->advertising setups what speeds
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* will be used for autonegotiation where 1000baseT must be disabled.
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*/
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phydev->supported = supported | SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full;
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phydev->advertising = supported;
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emaclite->phydev = phydev;
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phy_config(phydev);
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|
|
|
phy_startup(phydev);
|
|
|
|
|
|
|
|
if (!phydev->link) {
|
|
|
|
printf("%s: No link.\n", phydev->dev->name);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Do not setup anything */
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-10-11 01:41:47 +00:00
|
|
|
static int emaclite_init(struct eth_device *dev, bd_t *bis)
|
2008-03-28 11:41:56 +00:00
|
|
|
{
|
2011-09-12 21:10:01 +00:00
|
|
|
struct xemaclite *emaclite = dev->priv;
|
2015-12-10 13:18:15 +00:00
|
|
|
struct emaclite_regs *regs = emaclite->regs;
|
|
|
|
|
2011-09-12 21:10:05 +00:00
|
|
|
debug("EmacLite Initialization Started\n");
|
2008-03-28 11:41:56 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* TX - TX_PING & TX_PONG initialization
|
|
|
|
*/
|
|
|
|
/* Restart PING TX */
|
2015-12-10 14:22:21 +00:00
|
|
|
out_be32(®s->tx_ping_tsr, 0);
|
2008-03-28 11:41:56 +00:00
|
|
|
/* Copy MAC address */
|
2015-12-10 15:01:50 +00:00
|
|
|
xemaclite_alignedwrite(dev->enetaddr, ®s->tx_ping,
|
2015-12-10 14:22:21 +00:00
|
|
|
ENET_ADDR_LENGTH);
|
2008-03-28 11:41:56 +00:00
|
|
|
/* Set the length */
|
2015-12-10 14:22:21 +00:00
|
|
|
out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH);
|
2008-03-28 11:41:56 +00:00
|
|
|
/* Update the MAC address in the EMAC Lite */
|
2015-12-10 14:22:21 +00:00
|
|
|
out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
|
2008-03-28 11:41:56 +00:00
|
|
|
/* Wait for EMAC Lite to finish with the MAC address update */
|
2015-12-10 14:22:21 +00:00
|
|
|
while ((in_be32 (®s->tx_ping_tsr) &
|
2011-08-25 10:36:39 +00:00
|
|
|
XEL_TSR_PROG_MAC_ADDR) != 0)
|
|
|
|
;
|
2008-03-28 11:41:56 +00:00
|
|
|
|
2011-09-12 21:10:01 +00:00
|
|
|
if (emaclite->txpp) {
|
|
|
|
/* The same operation with PONG TX */
|
2015-12-10 14:22:21 +00:00
|
|
|
out_be32(®s->tx_pong_tsr, 0);
|
2015-12-10 15:01:50 +00:00
|
|
|
xemaclite_alignedwrite(dev->enetaddr, ®s->tx_pong,
|
2015-12-10 14:22:21 +00:00
|
|
|
ENET_ADDR_LENGTH);
|
|
|
|
out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH);
|
|
|
|
out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
|
|
|
|
while ((in_be32(®s->tx_pong_tsr) &
|
|
|
|
XEL_TSR_PROG_MAC_ADDR) != 0)
|
2011-09-12 21:10:01 +00:00
|
|
|
;
|
|
|
|
}
|
2008-03-28 11:41:56 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* RX - RX_PING & RX_PONG initialization
|
|
|
|
*/
|
|
|
|
/* Write out the value to flush the RX buffer */
|
2015-12-10 14:24:23 +00:00
|
|
|
out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
|
2011-09-12 21:10:01 +00:00
|
|
|
|
|
|
|
if (emaclite->rxpp)
|
2015-12-10 14:24:23 +00:00
|
|
|
out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
|
2008-03-28 11:41:56 +00:00
|
|
|
|
2015-12-10 12:33:20 +00:00
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
|
2015-12-10 13:18:15 +00:00
|
|
|
out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
|
|
|
|
if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
|
2015-12-10 12:33:20 +00:00
|
|
|
if (!setup_phy(dev))
|
|
|
|
return -1;
|
|
|
|
#endif
|
2011-09-12 21:10:05 +00:00
|
|
|
debug("EmacLite Initialization complete\n");
|
2008-03-28 11:41:56 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-12-10 14:42:01 +00:00
|
|
|
static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
|
2008-03-28 11:41:56 +00:00
|
|
|
{
|
2015-12-10 14:42:01 +00:00
|
|
|
u32 tmp;
|
|
|
|
struct emaclite_regs *regs = emaclite->regs;
|
2011-08-25 10:47:56 +00:00
|
|
|
|
2008-03-28 11:41:56 +00:00
|
|
|
/*
|
|
|
|
* Read the other buffer register
|
|
|
|
* and determine if the other buffer is available
|
|
|
|
*/
|
2015-12-10 14:42:01 +00:00
|
|
|
tmp = ~in_be32(®s->tx_ping_tsr);
|
|
|
|
if (emaclite->txpp)
|
|
|
|
tmp |= ~in_be32(®s->tx_pong_tsr);
|
2008-03-28 11:41:56 +00:00
|
|
|
|
2015-12-10 14:42:01 +00:00
|
|
|
return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
|
2008-03-28 11:41:56 +00:00
|
|
|
}
|
|
|
|
|
2012-05-22 12:18:10 +00:00
|
|
|
static int emaclite_send(struct eth_device *dev, void *ptr, int len)
|
2010-10-11 01:41:47 +00:00
|
|
|
{
|
|
|
|
u32 reg;
|
2011-08-25 10:47:56 +00:00
|
|
|
struct xemaclite *emaclite = dev->priv;
|
2015-12-10 14:32:11 +00:00
|
|
|
struct emaclite_regs *regs = emaclite->regs;
|
2008-03-28 11:41:56 +00:00
|
|
|
|
2010-10-11 01:41:47 +00:00
|
|
|
u32 maxtry = 1000;
|
2008-03-28 11:41:56 +00:00
|
|
|
|
2011-09-12 21:10:04 +00:00
|
|
|
if (len > PKTSIZE)
|
|
|
|
len = PKTSIZE;
|
2008-03-28 11:41:56 +00:00
|
|
|
|
2015-12-10 14:42:01 +00:00
|
|
|
while (xemaclite_txbufferavailable(emaclite) && maxtry) {
|
2011-09-12 21:10:05 +00:00
|
|
|
udelay(10);
|
2008-03-28 11:41:56 +00:00
|
|
|
maxtry--;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!maxtry) {
|
2011-09-12 21:10:05 +00:00
|
|
|
printf("Error: Timeout waiting for ethernet TX buffer\n");
|
2008-03-28 11:41:56 +00:00
|
|
|
/* Restart PING TX */
|
2015-12-10 14:32:11 +00:00
|
|
|
out_be32(®s->tx_ping_tsr, 0);
|
2011-09-12 21:10:01 +00:00
|
|
|
if (emaclite->txpp) {
|
2015-12-10 14:32:11 +00:00
|
|
|
out_be32(®s->tx_pong_tsr, 0);
|
2011-09-12 21:10:01 +00:00
|
|
|
}
|
2011-03-08 04:25:53 +00:00
|
|
|
return -1;
|
2008-03-28 11:41:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Determine if the expected buffer address is empty */
|
2015-12-10 15:01:50 +00:00
|
|
|
reg = in_be32(®s->tx_ping_tsr);
|
2015-12-10 15:06:07 +00:00
|
|
|
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
|
2015-12-10 15:01:50 +00:00
|
|
|
debug("Send packet from tx_ping buffer\n");
|
2008-03-28 11:41:56 +00:00
|
|
|
/* Write the frame to the buffer */
|
2015-12-10 15:01:50 +00:00
|
|
|
xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
|
|
|
|
out_be32(®s->tx_ping_tplr, len &
|
|
|
|
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
|
|
|
|
reg = in_be32(®s->tx_ping_tsr);
|
2008-03-28 11:41:56 +00:00
|
|
|
reg |= XEL_TSR_XMIT_BUSY_MASK;
|
2015-12-10 15:01:50 +00:00
|
|
|
out_be32(®s->tx_ping_tsr, reg);
|
2011-03-08 04:25:53 +00:00
|
|
|
return 0;
|
2008-03-28 11:41:56 +00:00
|
|
|
}
|
2011-09-12 21:10:01 +00:00
|
|
|
|
|
|
|
if (emaclite->txpp) {
|
|
|
|
/* Determine if the expected buffer address is empty */
|
2015-12-10 15:01:50 +00:00
|
|
|
reg = in_be32(®s->tx_pong_tsr);
|
2015-12-10 15:06:07 +00:00
|
|
|
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
|
2015-12-10 15:01:50 +00:00
|
|
|
debug("Send packet from tx_pong buffer\n");
|
2011-09-12 21:10:01 +00:00
|
|
|
/* Write the frame to the buffer */
|
2015-12-10 15:01:50 +00:00
|
|
|
xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
|
|
|
|
out_be32(®s->tx_pong_tplr, len &
|
|
|
|
(XEL_TPLR_LENGTH_MASK_HI |
|
|
|
|
XEL_TPLR_LENGTH_MASK_LO));
|
|
|
|
reg = in_be32(®s->tx_pong_tsr);
|
2011-09-12 21:10:01 +00:00
|
|
|
reg |= XEL_TSR_XMIT_BUSY_MASK;
|
2015-12-10 15:01:50 +00:00
|
|
|
out_be32(®s->tx_pong_tsr, reg);
|
2011-09-12 21:10:01 +00:00
|
|
|
return 0;
|
2008-03-28 11:41:56 +00:00
|
|
|
}
|
|
|
|
}
|
2011-09-12 21:10:01 +00:00
|
|
|
|
2011-09-12 21:10:05 +00:00
|
|
|
puts("Error while sending frame\n");
|
2011-03-08 04:25:53 +00:00
|
|
|
return -1;
|
2008-03-28 11:41:56 +00:00
|
|
|
}
|
|
|
|
|
2010-10-11 01:41:47 +00:00
|
|
|
static int emaclite_recv(struct eth_device *dev)
|
2008-03-28 11:41:56 +00:00
|
|
|
{
|
2010-10-11 01:41:47 +00:00
|
|
|
u32 length;
|
|
|
|
u32 reg;
|
|
|
|
u32 baseaddress;
|
2011-08-25 10:47:56 +00:00
|
|
|
struct xemaclite *emaclite = dev->priv;
|
2008-03-28 11:41:56 +00:00
|
|
|
|
2011-08-25 10:47:56 +00:00
|
|
|
baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
|
2008-03-28 11:41:56 +00:00
|
|
|
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
|
2011-09-12 21:10:05 +00:00
|
|
|
debug("Testing data at address 0x%x\n", baseaddress);
|
2008-03-28 11:41:56 +00:00
|
|
|
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
|
2011-09-12 21:10:01 +00:00
|
|
|
if (emaclite->rxpp)
|
|
|
|
emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
|
2008-03-28 11:41:56 +00:00
|
|
|
} else {
|
2011-09-12 21:10:01 +00:00
|
|
|
|
|
|
|
if (!emaclite->rxpp) {
|
2011-09-12 21:10:05 +00:00
|
|
|
debug("No data was available - address 0x%x\n",
|
2011-09-12 21:10:01 +00:00
|
|
|
baseaddress);
|
2008-03-28 11:41:56 +00:00
|
|
|
return 0;
|
2011-09-12 21:10:01 +00:00
|
|
|
} else {
|
|
|
|
baseaddress ^= XEL_BUFFER_OFFSET;
|
|
|
|
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
|
|
|
|
if ((reg & XEL_RSR_RECV_DONE_MASK) !=
|
|
|
|
XEL_RSR_RECV_DONE_MASK) {
|
|
|
|
debug("No data was available - address 0x%x\n",
|
|
|
|
baseaddress);
|
|
|
|
return 0;
|
|
|
|
}
|
2008-03-28 11:41:56 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
/* Get the length of the frame that arrived */
|
2010-10-11 01:41:46 +00:00
|
|
|
switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
|
2008-03-28 11:41:56 +00:00
|
|
|
0xFFFF0000 ) >> 16) {
|
|
|
|
case 0x806:
|
|
|
|
length = 42 + 20; /* FIXME size of ARP */
|
2011-09-12 21:10:05 +00:00
|
|
|
debug("ARP Packet\n");
|
2008-03-28 11:41:56 +00:00
|
|
|
break;
|
|
|
|
case 0x800:
|
|
|
|
length = 14 + 14 +
|
2011-09-12 21:10:05 +00:00
|
|
|
(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
|
|
|
|
0x10))) & 0xFFFF0000) >> 16);
|
|
|
|
/* FIXME size of IP packet */
|
2008-03-28 11:41:56 +00:00
|
|
|
debug ("IP Packet\n");
|
|
|
|
break;
|
|
|
|
default:
|
2011-09-12 21:10:04 +00:00
|
|
|
debug("Other Packet\n");
|
|
|
|
length = PKTSIZE;
|
2008-03-28 11:41:56 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-09-12 21:10:05 +00:00
|
|
|
xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
|
2008-03-28 11:41:56 +00:00
|
|
|
etherrxbuff, length);
|
|
|
|
|
|
|
|
/* Acknowledge the frame */
|
|
|
|
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
|
|
|
|
reg &= ~XEL_RSR_RECV_DONE_MASK;
|
|
|
|
out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
|
|
|
|
|
2011-09-12 21:10:05 +00:00
|
|
|
debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
|
2015-04-08 06:41:06 +00:00
|
|
|
net_process_received_packet((uchar *)etherrxbuff, length);
|
2011-03-08 04:25:53 +00:00
|
|
|
return length;
|
2008-03-28 11:41:56 +00:00
|
|
|
|
|
|
|
}
|
2010-10-11 01:41:47 +00:00
|
|
|
|
2015-12-10 12:33:20 +00:00
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
|
|
|
|
static int emaclite_miiphy_read(const char *devname, uchar addr,
|
|
|
|
uchar reg, ushort *val)
|
|
|
|
{
|
|
|
|
u32 ret;
|
|
|
|
struct eth_device *dev = eth_get_dev();
|
|
|
|
|
2015-12-10 13:18:15 +00:00
|
|
|
ret = phyread(dev->priv, addr, reg, val);
|
2015-12-10 12:33:20 +00:00
|
|
|
debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int emaclite_miiphy_write(const char *devname, uchar addr,
|
|
|
|
uchar reg, ushort val)
|
|
|
|
{
|
|
|
|
struct eth_device *dev = eth_get_dev();
|
|
|
|
|
|
|
|
debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
|
2015-12-10 13:18:15 +00:00
|
|
|
return phywrite(dev->priv, addr, reg, val);
|
2015-12-10 12:33:20 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-10-12 23:23:22 +00:00
|
|
|
int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
|
|
|
|
int txpp, int rxpp)
|
2010-10-11 01:41:47 +00:00
|
|
|
{
|
|
|
|
struct eth_device *dev;
|
2011-08-25 10:47:56 +00:00
|
|
|
struct xemaclite *emaclite;
|
2015-12-10 13:18:15 +00:00
|
|
|
struct emaclite_regs *regs;
|
2010-10-11 01:41:47 +00:00
|
|
|
|
2011-08-25 10:28:47 +00:00
|
|
|
dev = calloc(1, sizeof(*dev));
|
2010-10-11 01:41:47 +00:00
|
|
|
if (dev == NULL)
|
2011-03-08 04:25:53 +00:00
|
|
|
return -1;
|
2010-10-11 01:41:47 +00:00
|
|
|
|
2011-08-25 10:47:56 +00:00
|
|
|
emaclite = calloc(1, sizeof(struct xemaclite));
|
|
|
|
if (emaclite == NULL) {
|
|
|
|
free(dev);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->priv = emaclite;
|
|
|
|
|
2011-10-12 23:23:22 +00:00
|
|
|
emaclite->txpp = txpp;
|
|
|
|
emaclite->rxpp = rxpp;
|
2011-09-12 21:10:01 +00:00
|
|
|
|
2011-10-12 23:23:21 +00:00
|
|
|
sprintf(dev->name, "Xelite.%lx", base_addr);
|
2010-10-11 01:41:47 +00:00
|
|
|
|
2015-12-10 13:18:15 +00:00
|
|
|
emaclite->regs = (struct emaclite_regs *)base_addr;
|
|
|
|
regs = emaclite->regs;
|
2010-10-11 01:41:47 +00:00
|
|
|
dev->iobase = base_addr;
|
|
|
|
dev->init = emaclite_init;
|
|
|
|
dev->halt = emaclite_halt;
|
|
|
|
dev->send = emaclite_send;
|
|
|
|
dev->recv = emaclite_recv;
|
|
|
|
|
2015-12-10 12:33:20 +00:00
|
|
|
#ifdef CONFIG_PHY_ADDR
|
|
|
|
emaclite->phyaddr = CONFIG_PHY_ADDR;
|
|
|
|
#else
|
|
|
|
emaclite->phyaddr = -1;
|
|
|
|
#endif
|
|
|
|
|
2010-10-11 01:41:47 +00:00
|
|
|
eth_register(dev);
|
|
|
|
|
2015-12-10 12:33:20 +00:00
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
|
|
|
|
miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write);
|
|
|
|
emaclite->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
|
2015-12-10 13:18:15 +00:00
|
|
|
out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
|
2015-12-10 12:33:20 +00:00
|
|
|
#endif
|
|
|
|
|
2011-03-08 04:25:53 +00:00
|
|
|
return 1;
|
2010-10-11 01:41:47 +00:00
|
|
|
}
|