linux/drivers/gpu/drm/msm/dsi
Archit Taneja ff73ff1940 drm/msm/dsi: Populate the 10nm PHY funcs
Populate the PHY ops with the downstream driver as reference.

There are a couple of TODOs which need to be resolved:
- The PHY timings are all hardcoded for now. This needs to be replaced
  with automatic calculations once we get/understand them.
- There are some lane configuration registers which use a new
  representation between physical and logical lane mappings. For now,
  we've hardcoced them to follow the default mapping (i.e
  logical 0 -> phy 0, logical 1 -> phy 1 etc).

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-02-20 10:41:21 -05:00
..
phy drm/msm/dsi: Populate the 10nm PHY funcs 2018-02-20 10:41:21 -05:00
pll drm/msm/dsi: Populate PLL 10nm clock ops 2018-02-20 10:41:20 -05:00
dsi_cfg.c drm/msm/dsi: convert to msm_clk_get() 2017-10-28 11:01:33 -04:00
dsi_cfg.h drm/msm/dsi: Add 8x96 info in dsi_cfg 2017-02-06 11:28:44 -05:00
dsi_host.c Linux 4.14-rc7 2017-11-02 12:40:41 +10:00
dsi_manager.c drm/msm/dsi: correct DSI id bounds check during registration 2018-02-20 10:41:20 -05:00
dsi.c drm/msm/dsi: check msm_dsi and dsi pointers before use 2018-02-20 10:41:20 -05:00
dsi.h drm/msm/dsi: Add skeleton 10nm PHY/PLL code 2018-02-20 10:41:20 -05:00
dsi.xml.h drm/msm/dsi: Update generated headers for 10nm PLL/PHY 2018-02-20 10:41:20 -05:00
mmss_cc.xml.h drm/msm: update generated headers 2017-06-16 11:16:07 -04:00
sfpb.xml.h drm/msm: update generated headers 2017-06-16 11:16:07 -04:00