Christoph Hellwig 9209fb5189 riscv: move sifive_l2_cache.c to drivers/soc ... The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. Fixes: a967a289f1 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Borislav Petkov <bp@suse.de> [paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-12-20 03:40:24 -08:00
..
cacheflush.c	riscv: add nommu support	2019-11-17 15:17:39 -08:00
context.c	riscv: add nommu support	2019-11-17 15:17:39 -08:00
extable.c	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
fault.c	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
hugetlbpage.c	riscv: Introduce huge page support for 32/64bit kernel	2019-07-03 15:23:38 -07:00
init.c	Merge branch 'next/misc2' into for-next	2019-11-22 18:59:17 -08:00
Makefile	riscv: move sifive_l2_cache.c to drivers/soc	2019-12-20 03:40:24 -08:00
tlbflush.c	RISC-V: Issue a tlb page flush if possible	2019-10-29 11:32:18 -07:00