forked from Minki/linux
6cb971114f
Use the simple-bus node to discover the io area, and remap the cached and bypass io ranges. The parent-bus-address value of the first triplet in the "ranges" property is used. This value is rounded down to the nearest 256MB boundary. The length of the io area is fixed at 256MB; the "ranges" property length value is ignored. Other limitations: (1) only the first simple-bus node is considered, and (2) only the first triplet of the "ranges" property is considered. See ePAPR 1.1 §6.5 for the simple-bus node description, and §2.3.8 for the "ranges" property description. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
/*
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* xtensa mmu stuff
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*
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* Extracted from init.c
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*/
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#include <linux/percpu.h>
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/cache.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <asm/page.h>
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#include <asm/initialize_mmu.h>
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#include <asm/io.h>
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void __init paging_init(void)
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{
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memset(swapper_pg_dir, 0, PAGE_SIZE);
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}
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/*
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* Flush the mmu and reset associated register to default values.
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*/
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void init_mmu(void)
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{
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#if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
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/*
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* Writing zeros to the instruction and data TLBCFG special
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* registers ensure that valid values exist in the register.
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*
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* For existing PGSZID<w> fields, zero selects the first element
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* of the page-size array. For nonexistent PGSZID<w> fields,
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* zero is the best value to write. Also, when changing PGSZID<w>
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* fields, the corresponding TLB must be flushed.
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*/
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set_itlbcfg_register(0);
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set_dtlbcfg_register(0);
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#endif
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#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF
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/*
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* Update the IO area mapping in case xtensa_kio_paddr has changed
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*/
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write_dtlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
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XCHAL_KIO_CACHED_VADDR + 6);
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write_itlb_entry(__pte(xtensa_kio_paddr + CA_WRITEBACK),
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XCHAL_KIO_CACHED_VADDR + 6);
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write_dtlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
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XCHAL_KIO_BYPASS_VADDR + 6);
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write_itlb_entry(__pte(xtensa_kio_paddr + CA_BYPASS),
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XCHAL_KIO_BYPASS_VADDR + 6);
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#endif
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local_flush_tlb_all();
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/* Set rasid register to a known value. */
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set_rasid_register(ASID_INSERT(ASID_USER_FIRST));
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/* Set PTEVADDR special register to the start of the page
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* table, which is in kernel mappable space (ie. not
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* statically mapped). This register's value is undefined on
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* reset.
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*/
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set_ptevaddr_register(PGTABLE_START);
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}
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