forked from Minki/linux
bfe16c894e
The change moves some of peripheral registrations and initializations (all peripherals dependent on GPIOs) from .init_machine to .init_late level, this allows to safely shift the shared GPIO controller driver initialization level after init level of i.MX IOMUXC driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
339 lines
8.5 KiB
C
339 lines
8.5 KiB
C
/*
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/physmap.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio.h>
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#include <linux/regulator/fixed.h>
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#include <linux/regulator/machine.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include "common.h"
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#include "devices-imx21.h"
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#include "hardware.h"
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#include "iomux-mx21.h"
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#define MX21ADS_CS8900A_REG (MX21_CS1_BASE_ADDR + 0x000000)
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#define MX21ADS_ST16C255_IOBASE_REG (MX21_CS1_BASE_ADDR + 0x200000)
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#define MX21ADS_VERSION_REG (MX21_CS1_BASE_ADDR + 0x400000)
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#define MX21ADS_IO_REG (MX21_CS1_BASE_ADDR + 0x800000)
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#define MX21ADS_MMC_CD IMX_GPIO_NR(4, 25)
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#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11)
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#define MX21ADS_MMGPIO_BASE (6 * 32)
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/* MX21ADS_IO_REG bit definitions */
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#define MX21ADS_IO_SD_WP (MX21ADS_MMGPIO_BASE + 0)
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#define MX21ADS_IO_TP6 (MX21ADS_IO_SD_WP)
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#define MX21ADS_IO_SW_SEL (MX21ADS_MMGPIO_BASE + 1)
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#define MX21ADS_IO_TP7 (MX21ADS_IO_SW_SEL)
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#define MX21ADS_IO_RESET_E_UART (MX21ADS_MMGPIO_BASE + 2)
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#define MX21ADS_IO_RESET_BASE (MX21ADS_MMGPIO_BASE + 3)
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#define MX21ADS_IO_CSI_CTL2 (MX21ADS_MMGPIO_BASE + 4)
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#define MX21ADS_IO_CSI_CTL1 (MX21ADS_MMGPIO_BASE + 5)
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#define MX21ADS_IO_CSI_CTL0 (MX21ADS_MMGPIO_BASE + 6)
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#define MX21ADS_IO_UART1_EN (MX21ADS_MMGPIO_BASE + 7)
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#define MX21ADS_IO_UART4_EN (MX21ADS_MMGPIO_BASE + 8)
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#define MX21ADS_IO_LCDON (MX21ADS_MMGPIO_BASE + 9)
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#define MX21ADS_IO_IRDA_EN (MX21ADS_MMGPIO_BASE + 10)
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#define MX21ADS_IO_IRDA_FIR_SEL (MX21ADS_MMGPIO_BASE + 11)
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#define MX21ADS_IO_IRDA_MD0_B (MX21ADS_MMGPIO_BASE + 12)
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#define MX21ADS_IO_IRDA_MD1 (MX21ADS_MMGPIO_BASE + 13)
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#define MX21ADS_IO_LED4_ON (MX21ADS_MMGPIO_BASE + 14)
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#define MX21ADS_IO_LED3_ON (MX21ADS_MMGPIO_BASE + 15)
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static const int mx21ads_pins[] __initconst = {
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/* CS8900A */
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(GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
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/* UART1 */
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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PE14_PF_UART1_CTS,
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PE15_PF_UART1_RTS,
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/* UART3 (IrDA) - only TXD and RXD */
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PE8_PF_UART3_TXD,
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PE9_PF_UART3_RXD,
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/* UART4 */
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PB26_AF_UART4_RTS,
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PB28_AF_UART4_TXD,
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PB29_AF_UART4_CTS,
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PB31_AF_UART4_RXD,
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/* LCDC */
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PA5_PF_LSCLK,
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PA6_PF_LD0,
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PA7_PF_LD1,
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PA8_PF_LD2,
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PA9_PF_LD3,
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PA10_PF_LD4,
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PA11_PF_LD5,
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PA12_PF_LD6,
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PA13_PF_LD7,
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PA14_PF_LD8,
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PA15_PF_LD9,
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PA16_PF_LD10,
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PA17_PF_LD11,
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PA18_PF_LD12,
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PA19_PF_LD13,
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PA20_PF_LD14,
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PA21_PF_LD15,
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PA22_PF_LD16,
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PA24_PF_REV, /* Sharp panel dedicated signal */
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PA25_PF_CLS, /* Sharp panel dedicated signal */
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PA26_PF_PS, /* Sharp panel dedicated signal */
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PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
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PA28_PF_HSYNC,
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PA29_PF_VSYNC,
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PA30_PF_CONTRAST,
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PA31_PF_OE_ACD,
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/* MMC/SDHC */
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PE18_PF_SD1_D0,
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PE19_PF_SD1_D1,
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PE20_PF_SD1_D2,
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PE21_PF_SD1_D3,
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PE22_PF_SD1_CMD,
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PE23_PF_SD1_CLK,
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/* NFC */
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PF0_PF_NRFB,
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PF1_PF_NFCE,
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PF2_PF_NFWP,
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PF3_PF_NFCLE,
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PF4_PF_NFALE,
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PF5_PF_NFRE,
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PF6_PF_NFWE,
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PF7_PF_NFIO0,
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PF8_PF_NFIO1,
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PF9_PF_NFIO2,
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PF10_PF_NFIO3,
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PF11_PF_NFIO4,
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PF12_PF_NFIO5,
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PF13_PF_NFIO6,
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PF14_PF_NFIO7,
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};
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/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
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static struct physmap_flash_data mx21ads_flash_data = {
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.width = 4,
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};
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static struct resource mx21ads_flash_resource =
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DEFINE_RES_MEM(MX21_CS0_BASE_ADDR, SZ_32M);
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static struct platform_device mx21ads_nor_mtd_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &mx21ads_flash_data,
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},
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.num_resources = 1,
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.resource = &mx21ads_flash_resource,
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};
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static struct resource mx21ads_cs8900_resources[] __initdata = {
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DEFINE_RES_MEM(MX21ADS_CS8900A_REG, SZ_1K),
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/* irq number is run-time assigned */
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DEFINE_RES_IRQ(-1),
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};
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static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
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.name = "cs89x0",
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.id = 0,
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.res = mx21ads_cs8900_resources,
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.num_res = ARRAY_SIZE(mx21ads_cs8900_resources),
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};
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static const struct imxuart_platform_data uart_pdata_rts __initconst = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static const struct imxuart_platform_data uart_pdata_norts __initconst = {
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};
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static struct resource mx21ads_mmgpio_resource =
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DEFINE_RES_MEM_NAMED(MX21ADS_IO_REG, SZ_2, "dat");
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static struct bgpio_pdata mx21ads_mmgpio_pdata = {
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.base = MX21ADS_MMGPIO_BASE,
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.ngpio = 16,
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};
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static struct platform_device mx21ads_mmgpio = {
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.name = "basic-mmio-gpio",
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.id = PLATFORM_DEVID_AUTO,
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.resource = &mx21ads_mmgpio_resource,
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.num_resources = 1,
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.dev = {
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.platform_data = &mx21ads_mmgpio_pdata,
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},
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};
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static struct regulator_consumer_supply mx21ads_lcd_regulator_consumer =
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REGULATOR_SUPPLY("lcd", "imx-fb.0");
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static struct regulator_init_data mx21ads_lcd_regulator_init_data = {
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.constraints = {
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.valid_ops_mask = REGULATOR_CHANGE_STATUS,
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},
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.consumer_supplies = &mx21ads_lcd_regulator_consumer,
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.num_consumer_supplies = 1,
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};
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static struct fixed_voltage_config mx21ads_lcd_regulator_pdata = {
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.supply_name = "LCD",
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.microvolts = 3300000,
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.gpio = MX21ADS_IO_LCDON,
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.enable_high = 1,
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.init_data = &mx21ads_lcd_regulator_init_data,
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};
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static struct platform_device mx21ads_lcd_regulator = {
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.name = "reg-fixed-voltage",
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.id = PLATFORM_DEVID_AUTO,
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.dev = {
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.platform_data = &mx21ads_lcd_regulator_pdata,
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},
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};
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/*
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* Connected is a portrait Sharp-QVGA display
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* of type: LQ035Q7DB02
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*/
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static struct imx_fb_videomode mx21ads_modes[] = {
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{
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.mode = {
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.name = "Sharp-LQ035Q7",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 188679, /* in ps (5.3MHz) */
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.hsync_len = 2,
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.left_margin = 6,
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.right_margin = 16,
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.vsync_len = 1,
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.upper_margin = 8,
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.lower_margin = 10,
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},
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.pcr = 0xfb108bc7,
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.bpp = 16,
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},
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};
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static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
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.mode = mx21ads_modes,
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.num_modes = ARRAY_SIZE(mx21ads_modes),
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.pwmr = 0x00a903ff,
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.lscr1 = 0x00120300,
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.dmacr = 0x00020008,
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};
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static int mx21ads_sdhc_get_ro(struct device *dev)
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{
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return gpio_get_value(MX21ADS_IO_SD_WP);
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}
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static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
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void *data)
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{
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int ret;
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ret = gpio_request(MX21ADS_IO_SD_WP, "mmc-ro");
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if (ret)
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return ret;
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return request_irq(gpio_to_irq(MX21ADS_MMC_CD), detect_irq,
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IRQF_TRIGGER_FALLING, "mmc-detect", data);
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}
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static void mx21ads_sdhc_exit(struct device *dev, void *data)
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{
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free_irq(gpio_to_irq(MX21ADS_MMC_CD), data);
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gpio_free(MX21ADS_IO_SD_WP);
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}
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static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
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.ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
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.get_ro = mx21ads_sdhc_get_ro,
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.init = mx21ads_sdhc_init,
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.exit = mx21ads_sdhc_exit,
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};
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static const struct mxc_nand_platform_data
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mx21ads_nand_board_info __initconst = {
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.width = 1,
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.hw_ecc = 1,
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};
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static struct platform_device *platform_devices[] __initdata = {
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&mx21ads_mmgpio,
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&mx21ads_lcd_regulator,
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&mx21ads_nor_mtd_device,
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};
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static void __init mx21ads_board_init(void)
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{
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imx21_soc_init();
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mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
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"mx21ads");
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imx21_add_imx_uart0(&uart_pdata_rts);
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imx21_add_imx_uart2(&uart_pdata_norts);
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imx21_add_imx_uart3(&uart_pdata_rts);
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imx21_add_mxc_nand(&mx21ads_nand_board_info);
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imx21_add_imx_fb(&mx21ads_fb_data);
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}
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static void __init mx21ads_late_init(void)
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{
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imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
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platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
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mx21ads_cs8900_resources[1].start =
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gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
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mx21ads_cs8900_resources[1].end =
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gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
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platform_device_register_full(&mx21ads_cs8900_devinfo);
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}
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static void __init mx21ads_timer_init(void)
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{
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mx21_clocks_init(32768, 26000000);
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}
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MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
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/* maintainer: Freescale Semiconductor, Inc. */
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.atag_offset = 0x100,
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.map_io = mx21_map_io,
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.init_early = imx21_init_early,
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.init_irq = mx21_init_irq,
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.init_time = mx21ads_timer_init,
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.init_machine = mx21ads_board_init,
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.init_late = mx21ads_late_init,
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.restart = mxc_restart,
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MACHINE_END
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