forked from Minki/linux
525ccc452c
More struct irq_chip conversions, this time the INTC2 handlers. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
742 lines
18 KiB
C
742 lines
18 KiB
C
#ifndef __ASM_SH_IRQ_H
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#define __ASM_SH_IRQ_H
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/*
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*
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* linux/include/asm-sh/irq.h
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2003 Paul Mundt
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*
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*/
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#include <asm/machvec.h>
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#include <asm/ptrace.h> /* for pt_regs */
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#if defined(CONFIG_SH_HP6XX) || \
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defined(CONFIG_SH_RTS7751R2D) || \
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defined(CONFIG_SH_HS7751RVOIP) || \
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defined(CONFIG_SH_HS7751RVOIP) || \
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defined(CONFIG_SH_SH03) || \
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defined(CONFIG_SH_R7780RP) || \
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defined(CONFIG_SH_LANDISK)
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#include <asm/mach/ide.h>
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#endif
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#ifndef CONFIG_CPU_SUBTYPE_SH7780
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#define INTC_DMAC0_MSK 0
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#if defined(CONFIG_CPU_SH3)
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#define INTC_IPRA 0xfffffee2UL
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#define INTC_IPRB 0xfffffee4UL
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#elif defined(CONFIG_CPU_SH4)
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#define INTC_IPRA 0xffd00004UL
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#define INTC_IPRB 0xffd00008UL
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#define INTC_IPRC 0xffd0000cUL
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#define INTC_IPRD 0xffd00010UL
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#endif
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#ifdef CONFIG_IDE
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# ifndef IRQ_CFCARD
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# define IRQ_CFCARD 14
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# endif
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# ifndef IRQ_PCMCIA
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# define IRQ_PCMCIA 15
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# endif
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#endif
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#define TIMER_IRQ 16
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#define TIMER_IPR_ADDR INTC_IPRA
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#define TIMER_IPR_POS 3
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#define TIMER_PRIORITY 2
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#define TIMER1_IRQ 17
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#define TIMER1_IPR_ADDR INTC_IPRA
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#define TIMER1_IPR_POS 2
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#define TIMER1_PRIORITY 4
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#define RTC_IRQ 22
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#define RTC_IPR_ADDR INTC_IPRA
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#define RTC_IPR_POS 0
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#define RTC_PRIORITY TIMER_PRIORITY
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#if defined(CONFIG_CPU_SH3)
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#define DMTE0_IRQ 48
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#define DMTE1_IRQ 49
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#define DMTE2_IRQ 50
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#define DMTE3_IRQ 51
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#define DMA_IPR_ADDR INTC_IPRE
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#define DMA_IPR_POS 3
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#define DMA_PRIORITY 7
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#if defined(CONFIG_CPU_SUBTYPE_SH7300)
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/* TMU2 */
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#define TIMER2_IRQ 18
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#define TIMER2_IPR_ADDR INTC_IPRA
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#define TIMER2_IPR_POS 1
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#define TIMER2_PRIORITY 2
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/* WDT */
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#define WDT_IRQ 27
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#define WDT_IPR_ADDR INTC_IPRB
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#define WDT_IPR_POS 3
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#define WDT_PRIORITY 2
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/* SIM (SIM Card Module) */
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#define SIM_ERI_IRQ 23
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#define SIM_RXI_IRQ 24
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#define SIM_TXI_IRQ 25
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#define SIM_TEND_IRQ 26
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#define SIM_IPR_ADDR INTC_IPRB
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#define SIM_IPR_POS 1
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#define SIM_PRIORITY 2
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/* VIO (Video I/O) */
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#define VIO_IRQ 52
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#define VIO_IPR_ADDR INTC_IPRE
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#define VIO_IPR_POS 2
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#define VIO_PRIORITY 2
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/* MFI (Multi Functional Interface) */
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#define MFI_IRQ 56
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#define MFI_IPR_ADDR INTC_IPRE
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#define MFI_IPR_POS 1
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#define MFI_PRIORITY 2
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/* VPU (Video Processing Unit) */
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#define VPU_IRQ 60
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#define VPU_IPR_ADDR INTC_IPRE
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#define VPU_IPR_POS 0
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#define VPU_PRIORITY 2
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/* KEY (Key Scan Interface) */
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#define KEY_IRQ 79
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#define KEY_IPR_ADDR INTC_IPRF
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#define KEY_IPR_POS 3
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#define KEY_PRIORITY 2
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/* CMT (Compare Match Timer) */
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#define CMT_IRQ 104
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#define CMT_IPR_ADDR INTC_IPRF
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#define CMT_IPR_POS 0
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#define CMT_PRIORITY 2
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/* DMAC(1) */
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#define DMTE0_IRQ 48
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#define DMTE1_IRQ 49
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#define DMTE2_IRQ 50
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#define DMTE3_IRQ 51
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#define DMA1_IPR_ADDR INTC_IPRE
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#define DMA1_IPR_POS 3
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#define DMA1_PRIORITY 7
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/* DMAC(2) */
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#define DMTE4_IRQ 76
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#define DMTE5_IRQ 77
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#define DMA2_IPR_ADDR INTC_IPRF
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#define DMA2_IPR_POS 2
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#define DMA2_PRIORITY 7
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/* SIOF0 */
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#define SIOF0_IRQ 84
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#define SIOF0_IPR_ADDR INTC_IPRH
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#define SIOF0_IPR_POS 3
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#define SIOF0_PRIORITY 3
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/* FLCTL (Flash Memory Controller) */
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#define FLSTE_IRQ 92
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#define FLTEND_IRQ 93
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#define FLTRQ0_IRQ 94
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#define FLTRQ1_IRQ 95
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#define FLCTL_IPR_ADDR INTC_IPRH
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#define FLCTL_IPR_POS 1
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#define FLCTL_PRIORITY 3
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/* IIC (IIC Bus Interface) */
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#define IIC_ALI_IRQ 96
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#define IIC_TACKI_IRQ 97
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#define IIC_WAITI_IRQ 98
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#define IIC_DTEI_IRQ 99
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#define IIC_IPR_ADDR INTC_IPRH
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#define IIC_IPR_POS 0
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#define IIC_PRIORITY 3
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/* SIO0 */
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#define SIO0_IRQ 88
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#define SIO0_IPR_ADDR INTC_IPRI
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#define SIO0_IPR_POS 3
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#define SIO0_PRIORITY 3
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/* SIU (Sound Interface Unit) */
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#define SIU_IRQ 108
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#define SIU_IPR_ADDR INTC_IPRJ
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#define SIU_IPR_POS 1
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#define SIU_PRIORITY 3
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#endif
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#elif defined(CONFIG_CPU_SH4)
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#define DMTE0_IRQ 34
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#define DMTE1_IRQ 35
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#define DMTE2_IRQ 36
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#define DMTE3_IRQ 37
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#define DMTE4_IRQ 44 /* 7751R only */
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#define DMTE5_IRQ 45 /* 7751R only */
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#define DMTE6_IRQ 46 /* 7751R only */
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#define DMTE7_IRQ 47 /* 7751R only */
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#define DMAE_IRQ 38
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#define DMA_IPR_ADDR INTC_IPRC
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#define DMA_IPR_POS 2
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#define DMA_PRIORITY 7
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#endif
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#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
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defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
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defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
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#define SCI_ERI_IRQ 23
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#define SCI_RXI_IRQ 24
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#define SCI_TXI_IRQ 25
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#define SCI_IPR_ADDR INTC_IPRB
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#define SCI_IPR_POS 1
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#define SCI_PRIORITY 3
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7300)
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#define SCIF0_IRQ 80
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#define SCIF0_IPR_ADDR INTC_IPRG
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#define SCIF0_IPR_POS 3
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#define SCIF0_PRIORITY 3
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709)
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#define SCIF_ERI_IRQ 56
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#define SCIF_RXI_IRQ 57
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#define SCIF_BRI_IRQ 58
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#define SCIF_TXI_IRQ 59
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#define SCIF_IPR_ADDR INTC_IPRE
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#define SCIF_IPR_POS 1
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#define SCIF_PRIORITY 3
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#define IRDA_ERI_IRQ 52
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#define IRDA_RXI_IRQ 53
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#define IRDA_BRI_IRQ 54
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#define IRDA_TXI_IRQ 55
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#define IRDA_IPR_ADDR INTC_IPRE
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#define IRDA_IPR_POS 2
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#define IRDA_PRIORITY 3
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
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#define SCIF_ERI_IRQ 40
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#define SCIF_RXI_IRQ 41
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#define SCIF_BRI_IRQ 42
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#define SCIF_TXI_IRQ 43
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#define SCIF_IPR_ADDR INTC_IPRC
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#define SCIF_IPR_POS 1
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#define SCIF_PRIORITY 3
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#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
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#define SCIF1_ERI_IRQ 23
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#define SCIF1_RXI_IRQ 24
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#define SCIF1_BRI_IRQ 25
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#define SCIF1_TXI_IRQ 26
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#define SCIF1_IPR_ADDR INTC_IPRB
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#define SCIF1_IPR_POS 1
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#define SCIF1_PRIORITY 3
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#endif /* ST40STB1 */
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#endif /* 775x / SH4-202 / ST40STB1 */
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#endif /* 7780 */
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/* NR_IRQS is made from three components:
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* 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
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* 2. PINT_NR_IRQS - number of PINT interrupts
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* 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
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*/
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/* 1. ONCHIP_NR_IRQS */
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#if defined(CONFIG_CPU_SUBTYPE_SH7604)
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# define ONCHIP_NR_IRQS 24 // Actually 21
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#elif defined(CONFIG_CPU_SUBTYPE_SH7707)
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# define ONCHIP_NR_IRQS 64
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# define PINT_NR_IRQS 16
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#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
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# define ONCHIP_NR_IRQS 32
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#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705)
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# define ONCHIP_NR_IRQS 64 // Actually 61
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# define PINT_NR_IRQS 16
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
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# define ONCHIP_NR_IRQS 104
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
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# define ONCHIP_NR_IRQS 48 // Actually 44
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#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
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# define ONCHIP_NR_IRQS 72
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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# define ONCHIP_NR_IRQS 112 /* XXX */
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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# define ONCHIP_NR_IRQS 72
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#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
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# define ONCHIP_NR_IRQS 144
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#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
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defined(CONFIG_CPU_SUBTYPE_SH73180) || \
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defined(CONFIG_CPU_SUBTYPE_SH7343)
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# define ONCHIP_NR_IRQS 109
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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# define ONCHIP_NR_IRQS 111
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#elif defined(CONFIG_SH_UNKNOWN) /* Most be last */
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# define ONCHIP_NR_IRQS 144
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#endif
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/* 2. PINT_NR_IRQS */
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#ifdef CONFIG_SH_UNKNOWN
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# define PINT_NR_IRQS 16
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#else
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# ifndef PINT_NR_IRQS
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# define PINT_NR_IRQS 0
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# endif
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#endif
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#if PINT_NR_IRQS > 0
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# define PINT_IRQ_BASE ONCHIP_NR_IRQS
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#endif
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/* 3. OFFCHIP_NR_IRQS */
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#if defined(CONFIG_HD64461)
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# define OFFCHIP_NR_IRQS 18
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#elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
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# define OFFCHIP_NR_IRQS 48
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#elif defined(CONFIG_HD64465)
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# define OFFCHIP_NR_IRQS 16
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#elif defined (CONFIG_SH_EC3104)
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# define OFFCHIP_NR_IRQS 16
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#elif defined (CONFIG_SH_DREAMCAST)
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# define OFFCHIP_NR_IRQS 96
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#elif defined (CONFIG_SH_TITAN)
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# define OFFCHIP_NR_IRQS 4
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#elif defined(CONFIG_SH_R7780RP)
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# define OFFCHIP_NR_IRQS 16
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#elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
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# define OFFCHIP_NR_IRQS 12
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#elif defined(CONFIG_SH_UNKNOWN)
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# define OFFCHIP_NR_IRQS 16 /* Must also be last */
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#else
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# define OFFCHIP_NR_IRQS 0
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#endif
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#if OFFCHIP_NR_IRQS > 0
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# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
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#endif
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/* NR_IRQS. 1+2+3 */
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#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
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extern void disable_irq(unsigned int);
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extern void disable_irq_nosync(unsigned int);
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extern void enable_irq(unsigned int);
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/*
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* Simple Mask Register Support
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*/
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extern void make_maskreg_irq(unsigned int irq);
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extern unsigned short *irq_mask_register;
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/*
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* PINT IRQs
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*/
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void init_IRQ_pint(void);
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/*
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* Function for "on chip support modules".
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*/
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extern void make_ipr_irq(unsigned int irq, unsigned int addr,
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int pos, int priority);
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extern void make_imask_irq(unsigned int irq);
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#if defined(CONFIG_CPU_SUBTYPE_SH7300)
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#undef INTC_IPRA
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#undef INTC_IPRB
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#define INTC_IPRA 0xA414FEE2UL
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#define INTC_IPRB 0xA414FEE4UL
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#define INTC_IPRC 0xA4140016UL
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#define INTC_IPRD 0xA4140018UL
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#define INTC_IPRE 0xA414001AUL
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#define INTC_IPRF 0xA4080000UL
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#define INTC_IPRG 0xA4080002UL
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#define INTC_IPRH 0xA4080004UL
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#define INTC_IPRI 0xA4080006UL
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#define INTC_IPRJ 0xA4080008UL
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#define INTC_IMR0 0xA4080040UL
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#define INTC_IMR1 0xA4080042UL
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#define INTC_IMR2 0xA4080044UL
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#define INTC_IMR3 0xA4080046UL
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#define INTC_IMR4 0xA4080048UL
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#define INTC_IMR5 0xA408004AUL
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#define INTC_IMR6 0xA408004CUL
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#define INTC_IMR7 0xA408004EUL
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#define INTC_IMR8 0xA4080050UL
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#define INTC_IMR9 0xA4080052UL
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#define INTC_IMR10 0xA4080054UL
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#define INTC_IMCR0 0xA4080060UL
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#define INTC_IMCR1 0xA4080062UL
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#define INTC_IMCR2 0xA4080064UL
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#define INTC_IMCR3 0xA4080066UL
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#define INTC_IMCR4 0xA4080068UL
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#define INTC_IMCR5 0xA408006AUL
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#define INTC_IMCR6 0xA408006CUL
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#define INTC_IMCR7 0xA408006EUL
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#define INTC_IMCR8 0xA4080070UL
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#define INTC_IMCR9 0xA4080072UL
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#define INTC_IMCR10 0xA4080074UL
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#define INTC_ICR0 0xA414FEE0UL
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#define INTC_ICR1 0xA4140010UL
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#define INTC_IRR0 0xA4140004UL
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#define PORT_PACR 0xA4050100UL
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#define PORT_PBCR 0xA4050102UL
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#define PORT_PCCR 0xA4050104UL
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#define PORT_PDCR 0xA4050106UL
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#define PORT_PECR 0xA4050108UL
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#define PORT_PFCR 0xA405010AUL
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#define PORT_PGCR 0xA405010CUL
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#define PORT_PHCR 0xA405010EUL
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#define PORT_PJCR 0xA4050110UL
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#define PORT_PKCR 0xA4050112UL
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#define PORT_PLCR 0xA4050114UL
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#define PORT_SCPCR 0xA4050116UL
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#define PORT_PMCR 0xA4050118UL
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#define PORT_PNCR 0xA405011AUL
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#define PORT_PQCR 0xA405011CUL
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#define PORT_PSELA 0xA4050140UL
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#define PORT_PSELB 0xA4050142UL
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#define PORT_PSELC 0xA4050144UL
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#define PORT_HIZCRA 0xA4050146UL
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#define PORT_HIZCRB 0xA4050148UL
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#define PORT_DRVCR 0xA4050150UL
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#define PORT_PADR 0xA4050120UL
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#define PORT_PBDR 0xA4050122UL
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#define PORT_PCDR 0xA4050124UL
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#define PORT_PDDR 0xA4050126UL
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#define PORT_PEDR 0xA4050128UL
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#define PORT_PFDR 0xA405012AUL
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#define PORT_PGDR 0xA405012CUL
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#define PORT_PHDR 0xA405012EUL
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#define PORT_PJDR 0xA4050130UL
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#define PORT_PKDR 0xA4050132UL
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#define PORT_PLDR 0xA4050134UL
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#define PORT_SCPDR 0xA4050136UL
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#define PORT_PMDR 0xA4050138UL
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#define PORT_PNDR 0xA405013AUL
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#define PORT_PQDR 0xA405013CUL
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#define IRQ0_IRQ 32
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#define IRQ1_IRQ 33
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#define IRQ2_IRQ 34
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#define IRQ3_IRQ 35
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#define IRQ4_IRQ 36
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#define IRQ5_IRQ 37
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#define IRQ0_IPR_ADDR INTC_IPRC
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#define IRQ1_IPR_ADDR INTC_IPRC
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#define IRQ2_IPR_ADDR INTC_IPRC
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#define IRQ3_IPR_ADDR INTC_IPRC
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#define IRQ4_IPR_ADDR INTC_IPRD
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#define IRQ5_IPR_ADDR INTC_IPRD
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#define IRQ0_IPR_POS 0
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#define IRQ1_IPR_POS 1
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#define IRQ2_IPR_POS 2
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#define IRQ3_IPR_POS 3
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#define IRQ4_IPR_POS 0
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#define IRQ5_IPR_POS 1
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#define IRQ0_PRIORITY 1
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#define IRQ1_PRIORITY 1
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#define IRQ2_PRIORITY 1
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#define IRQ3_PRIORITY 1
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#define IRQ4_PRIORITY 1
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#define IRQ5_PRIORITY 1
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extern int ipr_irq_demux(int irq);
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#define __irq_demux(irq) ipr_irq_demux(irq)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
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#define INTC_IPRA 0xfffffee2UL
|
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#define INTC_IPRB 0xfffffe60UL
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#define INTC_VCRA 0xfffffe62UL
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#define INTC_VCRB 0xfffffe64UL
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#define INTC_VCRC 0xfffffe66UL
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#define INTC_VCRD 0xfffffe68UL
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|
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#define INTC_VCRWDT 0xfffffee4UL
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#define INTC_VCRDIV 0xffffff0cUL
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#define INTC_VCRDMA0 0xffffffa0UL
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#define INTC_VCRDMA1 0xffffffa8UL
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|
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#define INTC_ICR 0xfffffee0UL
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|
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
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defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
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defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
|
defined(CONFIG_CPU_SUBTYPE_SH7710)
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|
#define INTC_IRR0 0xa4000004UL
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#define INTC_IRR1 0xa4000006UL
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#define INTC_IRR2 0xa4000008UL
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|
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#define INTC_ICR0 0xfffffee0UL
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#define INTC_ICR1 0xa4000010UL
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#define INTC_ICR2 0xa4000012UL
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#define INTC_INTER 0xa4000014UL
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|
|
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#define INTC_IPRC 0xa4000016UL
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|
#define INTC_IPRD 0xa4000018UL
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#define INTC_IPRE 0xa400001aUL
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|
#if defined(CONFIG_CPU_SUBTYPE_SH7707)
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|
#define INTC_IPRF 0xa400001cUL
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|
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
|
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#define INTC_IPRF 0xa4080000UL
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|
#define INTC_IPRG 0xa4080002UL
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|
#define INTC_IPRH 0xa4080004UL
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
|
|
/* Interrupt Controller Registers */
|
|
#undef INTC_IPRA
|
|
#undef INTC_IPRB
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|
#define INTC_IPRA 0xA414FEE2UL
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|
#define INTC_IPRB 0xA414FEE4UL
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|
#define INTC_IPRF 0xA4080000UL
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|
#define INTC_IPRG 0xA4080002UL
|
|
#define INTC_IPRH 0xA4080004UL
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#define INTC_IPRI 0xA4080006UL
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|
|
|
#undef INTC_ICR0
|
|
#undef INTC_ICR1
|
|
#define INTC_ICR0 0xA414FEE0UL
|
|
#define INTC_ICR1 0xA4140010UL
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|
|
|
#define INTC_IRR0 0xa4000004UL
|
|
#define INTC_IRR1 0xa4000006UL
|
|
#define INTC_IRR2 0xa4000008UL
|
|
#define INTC_IRR3 0xa400000AUL
|
|
#define INTC_IRR4 0xa400000CUL
|
|
#define INTC_IRR5 0xa4080020UL
|
|
#define INTC_IRR7 0xa4080024UL
|
|
#define INTC_IRR8 0xa4080026UL
|
|
|
|
/* Interrupt numbers */
|
|
#define TIMER2_IRQ 18
|
|
#define TIMER2_IPR_ADDR INTC_IPRA
|
|
#define TIMER2_IPR_POS 1
|
|
#define TIMER2_PRIORITY 2
|
|
|
|
/* WDT */
|
|
#define WDT_IRQ 27
|
|
#define WDT_IPR_ADDR INTC_IPRB
|
|
#define WDT_IPR_POS 3
|
|
#define WDT_PRIORITY 2
|
|
|
|
#define SCIF0_ERI_IRQ 52
|
|
#define SCIF0_RXI_IRQ 53
|
|
#define SCIF0_BRI_IRQ 54
|
|
#define SCIF0_TXI_IRQ 55
|
|
#define SCIF0_IPR_ADDR INTC_IPRE
|
|
#define SCIF0_IPR_POS 2
|
|
#define SCIF0_PRIORITY 3
|
|
|
|
#define DMTE4_IRQ 76
|
|
#define DMTE5_IRQ 77
|
|
#define DMA2_IPR_ADDR INTC_IPRF
|
|
#define DMA2_IPR_POS 2
|
|
#define DMA2_PRIORITY 7
|
|
|
|
#define IPSEC_IRQ 79
|
|
#define IPSEC_IPR_ADDR INTC_IPRF
|
|
#define IPSEC_IPR_POS 3
|
|
#define IPSEC_PRIORITY 3
|
|
|
|
/* EDMAC */
|
|
#define EDMAC0_IRQ 80
|
|
#define EDMAC0_IPR_ADDR INTC_IPRG
|
|
#define EDMAC0_IPR_POS 3
|
|
#define EDMAC0_PRIORITY 3
|
|
|
|
#define EDMAC1_IRQ 81
|
|
#define EDMAC1_IPR_ADDR INTC_IPRG
|
|
#define EDMAC1_IPR_POS 2
|
|
#define EDMAC1_PRIORITY 3
|
|
|
|
#define EDMAC2_IRQ 82
|
|
#define EDMAC2_IPR_ADDR INTC_IPRG
|
|
#define EDMAC2_IPR_POS 1
|
|
#define EDMAC2_PRIORITY 3
|
|
|
|
/* SIOF */
|
|
#define SIOF0_ERI_IRQ 96
|
|
#define SIOF0_TXI_IRQ 97
|
|
#define SIOF0_RXI_IRQ 98
|
|
#define SIOF0_CCI_IRQ 99
|
|
#define SIOF0_IPR_ADDR INTC_IPRH
|
|
#define SIOF0_IPR_POS 0
|
|
#define SIOF0_PRIORITY 7
|
|
|
|
#define SIOF1_ERI_IRQ 100
|
|
#define SIOF1_TXI_IRQ 101
|
|
#define SIOF1_RXI_IRQ 102
|
|
#define SIOF1_CCI_IRQ 103
|
|
#define SIOF1_IPR_ADDR INTC_IPRI
|
|
#define SIOF1_IPR_POS 1
|
|
#define SIOF1_PRIORITY 7
|
|
#endif /* CONFIG_CPU_SUBTYPE_SH7710 */
|
|
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
|
|
#define PORT_PACR 0xa4050100UL
|
|
#define PORT_PBCR 0xa4050102UL
|
|
#define PORT_PCCR 0xa4050104UL
|
|
#define PORT_PETCR 0xa4050106UL
|
|
#define PORT_PADR 0xa4050120UL
|
|
#define PORT_PBDR 0xa4050122UL
|
|
#define PORT_PCDR 0xa4050124UL
|
|
#else
|
|
#define PORT_PACR 0xa4000100UL
|
|
#define PORT_PBCR 0xa4000102UL
|
|
#define PORT_PCCR 0xa4000104UL
|
|
#define PORT_PFCR 0xa400010aUL
|
|
#define PORT_PADR 0xa4000120UL
|
|
#define PORT_PBDR 0xa4000122UL
|
|
#define PORT_PCDR 0xa4000124UL
|
|
#define PORT_PFDR 0xa400012aUL
|
|
#endif
|
|
|
|
#define IRQ0_IRQ 32
|
|
#define IRQ1_IRQ 33
|
|
#define IRQ2_IRQ 34
|
|
#define IRQ3_IRQ 35
|
|
#define IRQ4_IRQ 36
|
|
#define IRQ5_IRQ 37
|
|
|
|
#define IRQ0_IPR_ADDR INTC_IPRC
|
|
#define IRQ1_IPR_ADDR INTC_IPRC
|
|
#define IRQ2_IPR_ADDR INTC_IPRC
|
|
#define IRQ3_IPR_ADDR INTC_IPRC
|
|
#define IRQ4_IPR_ADDR INTC_IPRD
|
|
#define IRQ5_IPR_ADDR INTC_IPRD
|
|
|
|
#define IRQ0_IPR_POS 0
|
|
#define IRQ1_IPR_POS 1
|
|
#define IRQ2_IPR_POS 2
|
|
#define IRQ3_IPR_POS 3
|
|
#define IRQ4_IPR_POS 0
|
|
#define IRQ5_IPR_POS 1
|
|
|
|
#define IRQ0_PRIORITY 1
|
|
#define IRQ1_PRIORITY 1
|
|
#define IRQ2_PRIORITY 1
|
|
#define IRQ3_PRIORITY 1
|
|
#define IRQ4_PRIORITY 1
|
|
#define IRQ5_PRIORITY 1
|
|
|
|
#define PINT0_IRQ 40
|
|
#define PINT8_IRQ 41
|
|
|
|
#define PINT0_IPR_ADDR INTC_IPRD
|
|
#define PINT8_IPR_ADDR INTC_IPRD
|
|
|
|
#define PINT0_IPR_POS 3
|
|
#define PINT8_IPR_POS 2
|
|
#define PINT0_PRIORITY 2
|
|
#define PINT8_PRIORITY 2
|
|
|
|
extern int ipr_irq_demux(int irq);
|
|
#define __irq_demux(irq) ipr_irq_demux(irq)
|
|
#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */
|
|
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
|
defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
|
#define INTC_ICR 0xffd00000
|
|
#define INTC_ICR_NMIL (1<<15)
|
|
#define INTC_ICR_MAI (1<<14)
|
|
#define INTC_ICR_NMIB (1<<9)
|
|
#define INTC_ICR_NMIE (1<<8)
|
|
#define INTC_ICR_IRLM (1<<7)
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_SUBTYPE_SH7780
|
|
#include <asm/irq-sh7780.h>
|
|
#endif
|
|
|
|
/* SH with INTC2-style interrupts */
|
|
#ifdef CONFIG_CPU_HAS_INTC2_IRQ
|
|
#if defined(CONFIG_CPU_SUBTYPE_ST40STB1)
|
|
#define INTC2_BASE 0xfe080000
|
|
#define INTC2_FIRST_IRQ 64
|
|
#define INTC2_INTREQ_OFFSET 0x20
|
|
#define INTC2_INTMSK_OFFSET 0x40
|
|
#define INTC2_INTMSKCLR_OFFSET 0x60
|
|
#define NR_INTC2_IRQS 25
|
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
|
|
#define INTC2_BASE 0xfe080000
|
|
#define INTC2_FIRST_IRQ 48 /* INTEVT 0x800 */
|
|
#define INTC2_INTREQ_OFFSET 0x20
|
|
#define INTC2_INTMSK_OFFSET 0x40
|
|
#define INTC2_INTMSKCLR_OFFSET 0x60
|
|
#define NR_INTC2_IRQS 64
|
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
|
#define INTC2_BASE 0xffd40000
|
|
#define INTC2_FIRST_IRQ 21
|
|
#define INTC2_INTMSK_OFFSET (0x38)
|
|
#define INTC2_INTMSKCLR_OFFSET (0x3c)
|
|
#define NR_INTC2_IRQS 60
|
|
#endif
|
|
|
|
#define INTC2_INTPRI_OFFSET 0x00
|
|
|
|
struct intc2_data {
|
|
unsigned short irq;
|
|
unsigned char ipr_offset, ipr_shift;
|
|
unsigned char msk_offset, msk_shift;
|
|
unsigned char priority;
|
|
};
|
|
|
|
void make_intc2_irq(struct intc2_data *);
|
|
void init_IRQ_intc2(void);
|
|
#endif
|
|
|
|
extern int shmse_irq_demux(int irq);
|
|
|
|
static inline int generic_irq_demux(int irq)
|
|
{
|
|
return irq;
|
|
}
|
|
|
|
#ifndef __irq_demux
|
|
#define __irq_demux(irq) (irq)
|
|
#endif
|
|
#define irq_canonicalize(irq) (irq)
|
|
#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq))
|
|
|
|
#ifdef CONFIG_4KSTACKS
|
|
extern void irq_ctx_init(int cpu);
|
|
extern void irq_ctx_exit(int cpu);
|
|
# define __ARCH_HAS_DO_SOFTIRQ
|
|
#else
|
|
# define irq_ctx_init(cpu) do { } while (0)
|
|
# define irq_ctx_exit(cpu) do { } while (0)
|
|
#endif
|
|
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH73180)
|
|
#include <asm/irq-sh73180.h>
|
|
#endif
|
|
|
|
#if defined(CONFIG_CPU_SUBTYPE_SH7343)
|
|
#include <asm/irq-sh7343.h>
|
|
#endif
|
|
|
|
#endif /* __ASM_SH_IRQ_H */
|