Sowjanya Komatineni fa62228240 clk: tegra: pllout: Save and restore pllout context ... This patch implements save and restore of pllout context. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So during suspend entry the state of pllout is saved and on resume it is restored back to have pllout in same state as before suspend. pllout rate is saved and restore in clock divider so it will be at same rate as before suspend when pllout state is restored. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2019-11-11 14:53:02 +01:00
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clk-audio-sync.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-bpmp.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
clk-dfll.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
clk-dfll.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
clk-divider.c	clk: tegra: divider: Save and restore divider rate	2019-11-11 14:53:01 +01:00
clk-emc.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282	2019-06-05 17:36:37 +02:00
clk-id.h	clk: tegra: Rename sor0_lvds to sor0_out	2019-11-11 14:52:32 +01:00
clk-periph-fixed.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-periph-gate.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-periph.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-pll-out.c	clk: tegra: pllout: Save and restore pllout context	2019-11-11 14:53:02 +01:00
clk-pll.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-sdmmc-mux.c	clk: Remove io.h from clk-provider.h	2019-05-15 13:21:37 -07:00
clk-super.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-tegra20-emc.c	clk: tegra: Add Tegra20/30 EMC clock implementation	2019-11-11 14:01:22 +01:00
clk-tegra20.c	clk: tegra: Add Tegra20/30 EMC clock implementation	2019-11-11 14:01:22 +01:00
clk-tegra30.c	clk: tegra: Add Tegra20/30 EMC clock implementation	2019-11-11 14:01:22 +01:00
clk-tegra114.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-tegra124-dfll-fcpu.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
clk-tegra124.c	clk: tegra: Reimplement SOR clock on Tegra124	2019-11-11 14:52:44 +01:00
clk-tegra210.c	clk: tegra: Reimplement SOR clocks on Tegra210	2019-11-11 14:52:53 +01:00
clk-tegra-audio.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-tegra-fixed.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-tegra-periph.c	clk: tegra: Move SOR0 implementation to Tegra124	2019-11-11 14:52:18 +01:00
clk-tegra-pmc.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-tegra-super-gen4.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-utils.c	clk: tegra: Refactor fractional divider calculation	2018-07-25 13:43:34 -07:00
clk.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk.h	clk: tegra: Add Tegra20/30 EMC clock implementation	2019-11-11 14:01:22 +01:00
cvb.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
cvb.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
Kconfig	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
Makefile	clk: tegra: Add Tegra20/30 EMC clock implementation	2019-11-11 14:01:22 +01:00