fa374107c1
The enable register only masks the raw status bits to signal CPU interrupt only for enabled interrupts. The status bits are activated regardless of the enable register. This means that we might have an old interrupt event queued, which we are not interested in. To avoid getting a spurious interrupt signalled, we have to clear the old bit before we update the enable register. Signed-off-by: Tomasz Figa <tfiga@chromium.org> |
||
|---|---|---|
| .. | ||
| drm | ||
| host1x | ||
| ipu-v3 | ||
| vga | ||
| Makefile | ||