Sean Paul f892f24b37 clk: tegra124: Add init data for dsi lp clocks ... Set the parent of the dsi lp clocks to pll_p and the rate to 68MHz. The default parent is clk_m and rate is 12MHz, this is too slow to receive data from the peripheral. Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz will suffice. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>		2015-02-02 15:46:34 +02:00
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clk-audio-sync.c
clk-divider.c	clk: tegra: Implement memory-controller clock	2014-11-26 09:43:23 +01:00
clk-id.h	clk: tegra: Fix xusb_hs_src clock hierarchy	2014-05-22 22:14:52 -07:00
clk-periph-gate.c	ARM: tegra: Move includes to include/soc/tegra	2014-07-17 13:26:47 +02:00
clk-periph.c	clk: tegra: Staticize tegra_clk_periph_no_gate_ops	2014-02-23 14:46:05 -08:00
clk-pll-out.c
clk-pll.c	clk: tegra: Use XUSB-compatible SATA PLL sequence	2014-07-08 11:29:55 +03:00
clk-super.c	clk: tegra: Implement locking for super clock	2013-02-12 10:29:12 -07:00
clk-tegra20.c	clk: tegra: Implement memory-controller clock	2014-11-26 09:43:23 +01:00
clk-tegra30.c	clk: tegra: Implement memory-controller clock	2014-11-26 09:43:23 +01:00
clk-tegra114.c	clk: tegra: Implement memory-controller clock	2014-11-26 09:43:23 +01:00
clk-tegra124.c	clk: tegra124: Add init data for dsi lp clocks	2015-02-02 15:46:34 +02:00
clk-tegra-audio.c	clk: tegra: move audio clk to common file	2013-11-26 18:46:24 +02:00
clk-tegra-fixed.c	clk: tegra: move PMC, fixed clocks to common files	2013-11-26 18:46:49 +02:00
clk-tegra-periph.c	clk: tegra: SDMMC controllers are on APB	2015-02-02 15:46:14 +02:00
clk-tegra-pmc.c	clk: tegra: move PMC, fixed clocks to common files	2013-11-26 18:46:49 +02:00
clk-tegra-super-gen4.c	clk: tegra: cclk_lp has a pllx/2 divider	2014-02-17 16:18:28 +02:00
clk.c	clk: tegra: Make clock initialization more robust	2014-09-18 14:56:53 +03:00
clk.h	clk: tegra: Implement memory-controller clock	2014-11-26 09:43:23 +01:00
Makefile	clk: tegra124: Add support for Tegra124 clocks	2013-11-26 18:46:54 +02:00