f65aad4177
Drivers for EDAC on Cavium. Supported subsystems are: o CPU primary caches. These are parity protected only, so only error reporting. o Second level cache - ECC protected, provides SECDED. o Memory: ECC / SECDEC if used with suitable DRAM modules. The driver will will only initialize if ECC is enabled on a system so is safe to run on non-ECC memory. o PCI: Parity error reporting Since it is very hard to test this sort of code the implementation is very conservative and uses polling where possible for now. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
151 lines
3.1 KiB
C
151 lines
3.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Wind River Systems,
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* written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/edac.h>
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#include <asm/octeon/cvmx.h>
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#include "edac_core.h"
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#include "edac_module.h"
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#include "octeon_edac-lmc.h"
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#define EDAC_MOD_STR "octeon"
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static struct mem_ctl_info *mc_cavium;
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static void *lmc_base;
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static void co_lmc_poll(struct mem_ctl_info *mci)
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{
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union lmc_mem_cfg0 cfg0;
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union lmc_fadr fadr;
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char msg[64];
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fadr.u64 = readq(lmc_base + LMC_FADR);
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cfg0.u64 = readq(lmc_base + LMC_MEM_CFG0);
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snprintf(msg, sizeof(msg), "DIMM %d rank %d bank %d row %d col %d",
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fadr.fdimm, fadr.fbunk, fadr.fbank, fadr.frow, fadr.fcol);
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if (cfg0.sec_err) {
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
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msg, "");
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cfg0.intr_sec_ena = -1; /* Done, re-arm */
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}
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if (cfg0.ded_err) {
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
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msg, "");
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cfg0.intr_ded_ena = -1; /* Done, re-arm */
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}
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writeq(cfg0.u64, lmc_base + LMC_MEM_CFG0);
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}
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static int __devinit co_lmc_probe(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci;
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union lmc_mem_cfg0 cfg0;
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int res = 0;
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mci = edac_mc_alloc(0, 0, 0, 0);
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if (!mci)
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return -ENOMEM;
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mci->pdev = &pdev->dev;
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platform_set_drvdata(pdev, mci);
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mci->dev_name = dev_name(&pdev->dev);
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mci->mod_name = "octeon-lmc";
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mci->ctl_name = "co_lmc_err";
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mci->edac_check = co_lmc_poll;
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if (edac_mc_add_mc(mci) > 0) {
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pr_err("%s: edac_mc_add_mc() failed\n", __func__);
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goto err;
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}
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cfg0.u64 = readq(lmc_base + LMC_MEM_CFG0); /* We poll */
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cfg0.intr_ded_ena = 0;
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cfg0.intr_sec_ena = 0;
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writeq(cfg0.u64, lmc_base + LMC_MEM_CFG0);
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mc_cavium = mci;
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return 0;
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err:
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edac_mc_free(mci);
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return res;
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}
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static int co_lmc_remove(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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mc_cavium = NULL;
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edac_mc_del_mc(&pdev->dev);
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edac_mc_free(mci);
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return 0;
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}
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static struct platform_driver co_lmc_driver = {
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.probe = co_lmc_probe,
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.remove = co_lmc_remove,
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.driver = {
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.name = "co_lmc_edac",
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}
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};
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static int __init co_edac_init(void)
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{
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union lmc_mem_cfg0 cfg0;
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int ret;
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lmc_base = ioremap_nocache(LMC_BASE, LMC_SIZE);
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if (!lmc_base)
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return -ENOMEM;
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cfg0.u64 = readq(lmc_base + LMC_MEM_CFG0);
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if (!cfg0.ecc_ena) {
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pr_info(EDAC_MOD_STR " LMC EDAC: ECC disabled, good bye\n");
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ret = -ENODEV;
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goto out;
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}
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ret = platform_driver_register(&co_lmc_driver);
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if (ret) {
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pr_warning(EDAC_MOD_STR " LMC EDAC failed to register\n");
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goto out;
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}
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return ret;
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out:
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iounmap(lmc_base);
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return ret;
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}
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static void __exit co_edac_exit(void)
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{
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platform_driver_unregister(&co_lmc_driver);
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iounmap(lmc_base);
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}
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module_init(co_edac_init);
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module_exit(co_edac_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
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